Systems Programming

Programming Examples
&
RISC and CISC
 Data Movement operation SIC

 No Memory to Memory instructions

 3 byte word moved by loading it into
Reg. A
 Storing the Reg. at the destination
 Single byte char are also moved to
the desired destination
 LDCH loads the rightmost bits of
Reg. A
 4 different ways for defining storage
are shown
 Data Movement operation SIC/XE

 Value 5 loaded into Reg, A using

immediate addressing
 Flag # indicates immediate addressing
and 5 is the operand
 Also char Z loaded into Reg, A using
immediate addressing by the ASSCI
codeof z
 Arithmetic instructions SIC

 All done using Reg. A

 Sequence of instructions

BETA=ALPHA +
INCR-1

DELTA=GAMMA
+INCR-1
 Arithmetic instructions SIC/XE

 Sequence of instructions

BETA=ALPHA + INCR-1

DELTA=GAMMA +INCR-1

 INCR loaded to Reg. S (Avoid fetch INCR

each time)
 ADDR Reg. to Reg. addition
 Immediate addressing used for constant 1
in subtraction
 Looping and indexing SIC
 Copy 11-char. String to another
 (X) index Reg. initiated to 0 before loop
 LDCH target address is the 1st byte of Str1
 STCH target address is the 1st byte of Str2
 TIX do 2 functions
Add 1 to Reg. (X)
Compare new val. To operand (11)
 This comparison sets CC (condition code )
 JLT jumps if CC=less than
 In 2nd round (X) will be 1 then the target address
is the 2nd byte of str1 and str2
 Looping and indexing SIC/XE

 Copy 11-char. String to another

 TIXR is used instead of TIX
 It compare Reg. (X) with another Reg. (T) not
from memory (Faster)
 Immediate addressing used in initialize Reg.(T) to
11 and Reg. (X) to 0
 Input and Output SIC

 Reads one byte from device (F1) and copies it to

device (05)
 RD operand is a byte in memory contains input
device code
 TD checks the status of the device and sets CC
value
 If CC val. is the device not ready
 If ready load from input device to A and from A
to Memory (Data)
 Output performed the same way
 Subroutine calling SIC

 Reads 100 byte from an input device into

memory
 The read operation putted in subroutine
 JSUB is jump to subroutine instruction
 RSUB at the end return the control to the
first instruction after JSUB
 `
Subroutine calling SIC/XE
RISC and CISC
 Multiplying Two Numbers in Memory

 On the diagram the storage scheme for a generic computer.

 The main memory is divided into locations numbered from (row) 1: (column) 1 to
(row) 6: (column) 4.
 The execution unit is responsible for carrying out all computations.
 the execution unit can only operate on data that has been loaded into one of the
six registers (A, B, C, D, E, or F).
 Let's say we want to find the product of two numbers - one stored in location 2:3
and another stored in location 5:2 –
 Then store the product back in the location 2:3.

location 2:3 = location 2:3 × location 5:2

 Multiplying Two Numbers in Memory

 Famous CPU Manufacturers

 The CISC Approach

 Complex Instruction Set Computer

 primary goal : complete a task in as few lines of assembly as possible.
 For this particular task, a CISC processor would come prepared with a specific
instruction (we'll call it "MULT").
 When executed, this instruction loads the two values into separate registers,
multiplies the operands in the execution unit, and then stores the product in the
appropriate register.

MULT 2:3, 5:2

 MULT is what is known as a "complex instruction." It operates directly on the
computer's memory banks and does not require the programmer to explicitly call
any loading or storing functions.
 The CISC Approach

 One of the primary advantages of this system is that the compiler has to do very
little work to translate a high-level language statement into assembly.
 Because the length of the code is relatively short, Very Little RAM is required to
store instructions.
 The emphasis is put on building complex instructions directly into the hardware.
 Advantages of CISC Processors

 The compiler requires little effort to translate high-level programs or statement

languages into assembly or machine.
 The code length is quite short, which minimizes the memory requirement.
 it requires very less RAM.
 Execution of a single instruction requires several low-level tasks.
 CISC creates a process to manage power usage that adjusts clock speed and voltage.
 Disadvantages of CISC Processors

 CISC chips are slower than RSIC chips to execute per instruction cycle on each
program.
 Executing the pipeline in the CISC processor makes it complicated to use.
 The CISC chips require more transistors as compared to RISC design.
 This means that CISC processors need to access memory more often, which can
also lead to decreased performance.
 The RISC Approach

 Reduced Instruction Set Computer

 simple instructions can be executed within one clock cycle.
 "MULT" command divided into three separate commands:
 "LOAD" moves data from the memory bank to a register,
 "PROD" finds the product of two operands located within the registers,
 "STORE" which moves data from a register to the memory banks.
 The RISC Approach

 to perform the series of steps described in the CISC approach, a programmer would
need to code four lines of assembly:
 LOAD A, 2:3
 LOAD B, 5:2
 PROD A, B
 STORE 2:3, A
 At first, this may seem like a much less efficient way of completing the operation.
Because there are more lines of code, more RAM is needed to store the assembly
level instructions.
 The compiler must also perform more work to convert a high-level language
statement into code of this form.
 The RISC Approach
 However, the RISC strategy also brings some very important advantages.
 Because each instruction requires only one clock cycle to execute, the entire
program will execute in approximately the same amount of time as the multi-cycle
"MULT" command.
 These RISC "reduced instructions" require less transistors of hardware space than
the complex instructions, leaving more room for general purpose registers.
 Because all of the instructions execute in a uniform amount of time (i.e. one clock),
pipelining is possible.
 It supports a simple addressing mode and fixed length of instruction for executing
the pipeline.
 It uses LOAD and STORE instruction to access the memory location.
Fetch decode execute cycle diagram
Fetch stage
Decode stage
Execute stage
 Advantages of RISC Processor
 The RISC processor's performance is better due to the simple and
limited number of the instruction set.
 It requires several transistors that make it cheaper to design.
 RISC allows the instruction to use free space on a microprocessor
because of its simplicity.
 RISC processor is simpler than a CISC processor because of its simple
and quick design, and it can complete its work in one clock cycle.
 Disadvantages of RISC Processor
 The RISC processor's performance may vary according to the code
executed
 Programmers and compilers often use complex instructions.
 RISC processors require very fast memory to save various instructions
that require a large collection of cache memory to respond to the
instruction in a short time.
 The Performance Equation

 CISC approach attempts to minimize the number of

instructions per program, sacrificing the number of cycles per
instruction.
 RISC does the opposite, reducing the cycles per instruction at
the cost of the number of instructions per program.
 Difference between the RISC and CISC Processors

RISC CISC
1
It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.

2 It emphasizes on software to optimize the It emphasizes on hardware to optimize the instruction

instruction set. set.
3 It is a hard wired unit of programming in the RISC
Microprogramming unit in CISC Processor.
Processor.
4 It requires multiple register sets to store the
It requires a single register set to store the instruction.
instruction.
5
RISC has simple decoding of instruction. CISC has complex decoding of instruction.

6
Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.

7 It uses a limited number of instruction that It uses a large number of instruction that requires more
requires less time to execute the instructions. time to execute the instructions.
 Difference between the RISC and CISC Processors

RISC CISC
It uses LOAD and STORE that are independent It uses LOAD and STORE instruction in the memory-
8
instructions in the register-to-register to-memory.

9 has more transistors on memory registers. has transistors to store complex instructions.

10 The execution time of RISC is very short. The execution time of CISC is longer.

RISC architecture can be used with high-end

CISC architecture can be used with low-end applications
11 applications like telecommunication, image
like home automation, security system, etc.
processing, video processing, etc.

12 It has fixed format instruction. It has variable format instruction.

The program written for RISC architecture needs Program written for CISC architecture tends to take
13
to take more space in memory. less space in memory.
Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola 68000 family,
14
Architecture, Alpha, AVR, ARC and the SPARC. System/360, AMD and the Intel x86 CPUs.
 RISC Examples

 ARM (Advanced RISC Machines) Processors : ARM processors are one of the
most prevalent RISC architectures used in a wide range of devices, including smartphones,
tablets, embedded systems, and IoT devices. ARM processors are known for their power
efficiency, scalability, and versatility. They are designed by ARM Holdings and licensed to
numerous semiconductor manufacturers.
 MIPS (Microprocessor without Interlocked Pipeline Stages ): MIPS processors
have been widely used in various applications, including consumer electronics, networking
devices, and embedded systems. MIPS processors were developed by MIPS Technologies
(formerly MIPS Computer Systems). They are known for their simplicity, high
performance, and low power consumption.
 Power Architecture: The Power Architecture, originally developed by IBM and now
maintained by the OpenPOWER Foundation, is a RISC-based architecture that has been
used in a variety of systems, including servers, workstations, and embedded systems.
Power processors are known for their high performance, scalability, and reliability.
 RISC Examples

 SPARC (Scalable Processor Architecture): SPARC processors, developed by

Sun Microsystems (acquired by Oracle Corporation), are another notable
example of RISC architecture. They have been widely used in servers and high-
performance computing systems, providing features such as high scalability,
excellent floating-point performance, and multiprocessing capabilities.
 OpenRISC: OpenRISC is an open-source RISC architecture that aims to provide
a fully open and customizable processor design. It is based on the RISC
principles and is actively developed by the OpenRISC community. OpenRISC
processors are used in various research, educational, and hobbyist projects.
 CISC Examples

 Intel x86 Processors: Intel's x86 processors, including the popular Intel Core series,
Pentium, and Celeron processors, are perhaps the most well-known examples of CISC
architecture. x86 processors have been widely used in personal computers, laptops, and servers
for several decades.
 AMD x86 Processors: Advanced Micro Devices (AMD) also produces x86 processors that
follow the CISC architecture. AMD's processors, such as the AMD Ryzen and AMD Athlon
series, offer alternative options to Intel's x86 processors and are used in various computing
devices.
 IBM z/Architecture: IBM's z/Architecture, used in IBM's mainframe computers, is an
example of a CISC architecture. These processors are designed for high-performance
computing, scalability, and reliability, and are often used in mission-critical applications.
 CISC Examples

 Motorola 68000 Series: The Motorola 68000 series processors, including the 68000,
68020, and 68040, were widely used in early personal computers, workstations, and
game consoles. These processors were known for their rich instruction set and were
popular in the 1980s and 1990s.
 DEC VAX Processors: Digital Equipment Corporation's (DEC) VAX (Virtual
Address eXtension) processors used the VAX instruction set architecture, which is a
CISC architecture. VAX processors were widely used in DEC's VAX/VMS mainframe
computers and were known for their powerful instruction set and backward
compatibility.
 RISC Example : MIPS Architecture (Review):
 MIPS (Microprocessor without Interlocked Pipeline Stages) is generally classified
as a RISC (Reduced Instruction Set Computer) architecture.
 The MIPS architecture, which was developed in the 1980s
 Used in SGI (Silicon Graphics, Inc.) workstations.
 Load/store architecture; number of instructions is around 100
 Memory address = 32 bits; word size = 32 bits; processor can
 support both big endian and little endian ordering.
 Instruction length = 32 bits.
 Separate co-processors C0 (for exception handling) and C1 (floating
point operations).
 32 CPU registers for integer operations; each register is 32 bits long.
 RISC Example : MIPS Architecture (Review):
 32-bit (single precision) and 64-bit (double precision) floating point
 registers are available; floating point representation based on IEEE
 Floating Point Standard (FPS).
 Simple addressing modes (immediate, base + displacement and
PC-relative); load address (la) instruction to support indirect addressing.
 Supports all basic data types of C (int, char, float and double).
 CISC Example : IA-32 Architecture (Intel):
 Started with Intel 80386 in 1985 has undergone several iterations
and advancements since then.
 It is a complex instruction set computer (CISC) architecture,
characterized by a large set of instructions with varying
complexities.
 Memory address = 32 bits; little endian; word size = 32 bits.
 8 general purpose 32-bit registers (R0 through R7) and 8 floating
 point 64-bit registers (FP0 through FP7).
 CISC Example : IA-32 Architecture (Intel):
 Instruction Pointer (PC) and Status Register (containing condition code).
 More than 400 instructions; instruction lengths vary from 1 to 12 bytes (CISC).
 A variety of addressing modes (e.g. immediate, direct, register, register indirect,
base + displacement, base + index, etc).
 Supports all basic data types of C. Also supports quad precision for floating
point.
 Separate floating point processor.