

LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

1 TABLE OF CONTENTS

1 TABLE OF CONTENTS ……………………………………………………………. 0

2 REVISION HISTORY ……………………………………………………………. 1
3 FEATURES ……………………………………………………………………………... 2
4 SPECIFICATIONS ……………………………………………………………… 2
5 PIN CONFIGURATION …………………………………………………………… 2
6 PACKAGE OUTLINE DIMENSION …………………………………………………. 3/4
7 ORDERING INFORMATION …………………………………………………… 5
8 PIN DESCRIPTION ……………………………………………………………… 5
9 POWER‐UP INITIALIZATION …………………………………………………… 6
10 INTERFACE DESCRIPTION …………………………………………………… 7
10.1 Address Space ………………………………………………………………………… 7
10.2 Page Size …..…………………………………………………………………………. 7
10.3 Drive Strength ………………………………………………………………………… 7
10.4 Power-on Status ……………………………………………………………................ 7
10.5 Truth Table ……………………………………………………………………………... 8
10.6 Command Termination ……………………………………………………………. 9
11 WRAP BOUNDARY TOGGLE OPERATION …………………………………......... 10
12 SPI MODE OPERATIONS ……………………………………………………………. 11
12.1 SPI Read Operations …………………………………………………………..... 11/12
12.2 SPI Write Operations …………………………………………………………..... 12
12.3 SPI Quad Mode Enable Operation …………………………………………………… 13
12.4 SPI Read ID Operation ……..………………………………………………………… 13/14
13 QPI MODE OPERATIONS ……………………………………………………………. 14
13.1 QPI Read Operations ……………………………………………………………….. 14
13.2 QPI Write Operation(s) ……………………………………………………………….. 14
13.3 QPI Quad Mode Exit Operation ……………………………………………………. 15
14 RESET OPERATION ……………………………………………………………...... 16
15 INPUT / OUTPUT TIMING ……………………………………………………………. 17
16 ELECTRICAL SPECIFICATIONS ……………………………………………………. 18
16.1 Absolute Maximum Ratings …………………………………………………………… 18
16.2 Pin Capacitance ……………………………………………………………….. 18
16.3 Operating Conditions ……………………………………………………………….. 18
16.4 DC Electrical Characteristics ...………………………………………………………….. 19
16.5 AC Electrical Characteristics ……………………………………………………………. 19

Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
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 

LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

2 REVISION HISTORY

Revision Description Issue Date

Rev. 0.1 Initial Issue May.06.2016
Rev. 0.2 Revised typos May.19.2016
Rev. 0.3 Revised the address bit length from 32 bits to 24 bits Oct.13.2016
Rev. 0.4 Added Command Termination in page 7 May.03.2017
Revised Truth Table in page 7
Rev. 0.5 Reworded linear burst, renamed page toggle CMDs. Jul.20.2017
Updated timing parameters for 144MHz.
Removed QPI Read ‘h0B support.
Clarified termination section.
Added Pin Capacitance tables.
Extend tCHD to 20ns & tCPH to 50ns.
Rev. 0.6 Added Truth Table note: 2. Linear burst is prohibited. Aug.04.2017
Added Table 3: Burst Type / Length in page 10
Rev. 0.7 Revised temperature range to -40 ~ 85°C Nov.21.2017

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

3 FEATURES 4 SPECIFICATIONS
 50Ω Output Drive Strength LVCMOS.  Single Supply Voltage:
 Linear Burst (continuous) or 32 byte wrapped  VCC=2.7 to 3.6V
burst via toggle command.  Interface: SPI/QPI with SDR mode
 Linear Burst is supported up to 84MHz and can  Performance: Clock rate up to
cross page boundary as long as tCEM is met. 144MHz (non-page boundary crossing)
 Software reset. 84MHz (page boundary crossing)
 Green package available  Organization: 64Mb, 8M x 8bits
 Package : 8-pin 150mil SOP  Addressable bit range: A[22:0]
8-pin 5mm x 6mm WSON  Page size: 1024 bytes
 Refresh: Self-managed
 Operating temperature range
 TC = -40°C to +85°C
 Maximum Standby Current:
 400µA @ 85°C

5 PIN CONFIGURATION

CE# 1 8 Vcc
XXXXXX
LY68L6400
Lyontek

SO/SIO[1] 2 7 SIO[3]

SIO[2] 3 6 SCLK

Vss 4 5 SI/SIO[0]

SOP

1 8 CE# 1 8 VCC
XXXXXX
LY68L6400
Lyontek

2 7 SO/SIO[1] 2 7 SIO[3]

3 6 SIO[2] 3 6 SCLK

4 5 VSS 4 5 SI/SIO[0]

WSON(Top View) WSON(See Through with Top View)

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

6 PACKAGE OUTLINE DIMENSION

8-pin 150mil SOP Package Outline Dimension

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TEL: 886-3-6668838
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 

LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

8-pin 5mm x 6mm WSON Package Outline Dimension

Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

7 ORDERING INFORMATION
Table 1: Ordering Information

Package Type Maximum Temperature Packing Lyontek Item No.

Clock Rate(MHz) Range(℃) Type
8-pin (150mil) Tube LY68L6400SLI
144 -40℃~85℃
SOP Tape Reel LY68L6400SLIT
8-pin (5mm x 6mm) Tray LY68L6400BLI
144 -40℃~85℃
WSON Tape Reel LY68L6400BLIT

8 PIN DESCRIPTION

Table 2: Signals Table

SYMBOL TYPE SPI Mode Function QPI Mode Function COMMENTS

VCC Power Core supply 3V
VSS Ground Core supply ground
CE# Input Chip select, active low. When CE#=1, chip is in standby state.
CLK Input Clock Signal
SI/SIO[0] I/O Serial Input I/O[0]
SO/SIO[1] I/O Serial Output I/O[1]
SIO[2] I/O - I/O[2]
SIO[3] I/O - I/O[3]

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

9 POWER‐UP INITIALIZATION

SPI/QPI products include an on-chip voltage sensor used to start the self-initialization process.
When VCC reaches a stable level at or above minimum VCC, the device will require 150µs and
user-issued RESET Operation (see section 14) to complete its self-initialization process. From the
beginning of power ramp to the end of the 150µs period, CLK should remain LOW, CE# should remain
HIGH (track VCC within 200mV) and SI/SO/SIO[3:0] should remain LOW.

After the 150µs period the device is ready for normal operation.

VCCMIN

VCC tPU ≧ 150μs Device

Device Initialization Reset Device ready for normal operation

CE#

Figure 1 : Power-Up Initialization Timing

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

10 INTERFACE DESCRIPTION

10.1 Address Space

SPI/QPI PSRAM device is byte-addressable. 64M device is addressed with A[22:0].

10.2 Page Size

Page size is 1K (CA[9:0]). Default burst setting is Linear Bursting that crosses page boundary in a
continuous manner. Note however that burst operations which cross page boundary have a lower max
input clock frequency of 84MHz. Optionally the device can also be set to wrap 32 (CA[4:0]) via the
Wrap Boundary Toggle command and is not allowed to cross page boundary in this configuration.

10.3 Drive Strength

The device powers up in 50Ω.

10.4 Power-on Status

The device powers up in SPI Mode. It is required to have CE# high before beginning any operations.

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

10.5 Truth Table

The device recognizes the following commands specified by the various input methods.

SPI Mode (QE=0) QPI Mode (QE=1)

COMMAND CODE Wait MAX. Wait MAX.
CMD Addr DIO CMD Addr DIO
Cycle Freq. Cycle Freq.
Read ‘h03 S S 0 S 33 N/A
Fast Read ‘h0B S S 8 S 144 N/A
Fast Read Quad ‘hEB S Q 6 Q 144 Q Q 64 Q 144*1
Write ‘h02 S S 0 S 144* 2
Q Q 0Q Q 144*1
Quad Write ‘h38 S Q 0 Q 144 66
Same as ‘h02
Enter Quad Mode ‘h35 S - - - 144 N/A
Exit Quad Mode ‘hF5 N/A Q - - - 144
Reset Enable ‘h66 S - - - 144 Q - - - 144
Reset ‘h99 S - - - 144 Q - - - 144
Set Burst Length ‘hC0 S - - - 144 Q - - - 144
Read ID ‘h9F S S 0 S 144 N/A
Remarks: S = Serial I/O, Q = Quad I/O

Note: 1. 144MHz max without crossing page boundary, and 84MHz max when burst commands cross page boundary.
2. Linear burst is prohibited.

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

10.6 Command Termination

All Reads & Writes must be completed by raising CE# high immediately afterwards in order to
terminate the active command and set the device into standby. Not doing so will block internal refresh
operations and cause memory failure.

Write Terminated
CLK

tCHD
CE#
tHD
SI/SIO[#]
tSP
Data In

Don't Care

Figure 2 : Write Command Termination

For a memory controller to correctly latch the last piece of data prior to read termination, it is
recommended to provide a longer CE# hold time (tCHD > tACLK + tCLK) for a sufficient data window.

Read Terminated
CLK

tCHD
CE#
tHZ
tACLK
SO/SIO[#] High-Z

Data Out

Don't Care Undefined

Figure 3 : Read Command Termination

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

11 WRAP BOUNDARY TOGGLE OPERATION

The Wrap Boundary Toggle Operation switches the device’s wrapped boundary between Linear
Burst which crosses the 1K page boundary (CA[9:0]) and wrap 32 (CA[4:0]) bytes. Default setting is
Linear Burst.

Linear Burst allows the device to burst through page boundary. Page boundary crossing is invisible
to the memory controller and limited to lower max CLK frequency of 84MHz. Table 3 shows an
example of the sequence of bytes.

0 1 2 3 4 5 6 7
CLK

CE#

SI 1 1 0 0 0 0 0 0

SO High-Z

Wrap Boundary Toggle(‘hC0)

Don't Care Undefined

Figure 4 : SPI Wrap Boundary Toggle ‘hC0

0 1
CLK

CE#

SIO[3:0] C 0

CMD
WB Toggle(‘hC0)

Don't Care

Figure 5 : QPI Wrap Boundary Toggle ‘hC0

Table 3: Burst Type / Length

Burst Type / Length Starting Address Byte Sequence

Linear Burst 4 [4,5,6,…1023,1024,1025,1026,…]
Wrap 32 4 [4,5,6,…31,0,1,2,…]

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TEL: 886-3-6668838
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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

12 SPI MODE OPERATIONS

The device powers up into SPI mode by default but can also be switched into QPI mode.

12.1 SPI Read Operations

For all reads, data will be available tACLK after the falling edge of CLK.

SPI Reads can be done in three ways:

1. ‘h03: Serial CMD, Serial I/O, slow frequency, with linear or burst wrap of 32 byte configurability.
2. ‘h0B: Serial CMD, Serial I/O, fast frequency, with burst wrap of 32/1K byte configurability.
3. ‘hEB: Serial CMD, Quad I/O, fast frequency, with burst wrap of 32/1K byte configurability.

0 1 2 3 4 5 6 7 8 9 10 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CLK

tACLK
CE#

SI 0 0 0 0 0 0 1 1 23 22 21 2 1 0

SO High-Z 7 6 5 4 3 2 1 0 7 6 5 4

Read Command (‘h03) 24bit Address Data Out1 Data Out2

Don't Care Undefined

Figure 6 : SPI Read ‘h03 (MAX. freq. 33MHz)

0 1 2 3 4 5 6 7 8 9 10 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
CLK

tACLK
CE#

SI 0 0 0 0 1 0 1 1 23 22 21 2 1 0

SO High-Z 7 6 5 4 3 2 1 0 7 6 5

Fast Read Command(‘h0B) 24bit Address Wait Cycles Data Out1 Data Out2

Don't Care Undefined

Figure 7 : SPI Fast Read ‘h0B (MAX. freq. 104MHz)

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CLK

tACLK
CE#

SI/SIO[0] 1 1 1 0 1 0 1 1 20 16 12 8 4 0 High-Z 4 0 4 0

SO/SIO[1] High-Z 21 17 13 9 5 1 High-Z 5 1 5 1

SIO[2] High-Z 22 18 14 10 6 2 High-Z 6 2 6 2

SIO[3] High-Z 23 19 15 11 7 3 High-Z 7 3 7 3

Fast Quad Read CMD(‘hEB) 24bit Address Wait Cycles

Dout1 Dout2

Don't Care Undefined

Figure 8 : SPI Fast Quad Read ‘hEB (MAX. freq. 144MHz)

12.2 SPI Write Operations

0 1 2 3 4 5 6 7 8 9 10 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CLK

CE#

SI 0 0 0 0 0 0 1 0 23 22 21 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4

SO High-Z

Write Command(‘h02) 24bit Address Data In1 Data In2

Don't Care Undefined

Figure 9 : SPI Write ‘h02

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
CLK

CE#

SI/SIO[0] 0 0 1 1 1 0 0 0 20 16 12 8 4 0 4 0 4 0 4 0 4 0

SO/SIO[1] High-Z 21 17 13 9 5 1 5 1 5 1 5 1 5 1

SIO[2] High-Z 22 18 14 10 6 2 6 2 6 2 6 2 6 2

SIO[3] High-Z 23 19 15 11 7 3 7 3 7 3 7 3 7 3

Quad Write CMD(‘h38) 24bit Address

Data In1 Data In2 Data In3 Data In4

Don't Care Undefined

Figure 10 : SPI Quad Write ‘h38

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

12.3 SPI Quad Mode Enable Operation

This command switches the device into quad I/O mode.

0 1 2 3 4 5 6 7
CLK

CE#

SI 0 0 1 1 0 1 0 1

SO High-Z

Enter Quad Mode CMD(‘h35)

Don't Care Undefined

Figure 11 : Quad Mode Enable ‘h35

(available only in SPI mode)

12.4 SPI Read ID Operation

This command is similar to Fast Read, but without the wait cycles and the device outputs EID value
instead of data.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

CLK

tACLK
CE#

SI 1 0 0 1 1 1 1 1

SO High-Z 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Read ID(‘h9F) 24bit Address MF ID(‘h0D) KGD(‘h5D)

48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 100 101 102 103

CLK

CE#

SI

SO EID[47:0]

Don't Care Undefined

Figure 12 : SPI Read ID‘h9F (available only in SPI mode)

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

Table 4: Known Good Die (KGD)

KGD[7:0] Known Good Die

‘b0101_0101 FAIL
‘b0101_1101 PASS
*Note: Default is FAIL die, and only mark PASS after all tests passed.

13 QPI MODE OPERATIONS

13.1 QPI Read Operations

For all reads, data will be available tACLK after the falling edge of CLK.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLK

tACLK
CE#

SIO[3:0] E B 23:20 19:16 15:12 11:8 7:4 3:0 High-Z 7:4 3:0 7:4 3:0

24bit Address Wait Cycles

Fast Read Data Out1 Data Out2
CMD(‘hEB)

Don't Care

Figure 13 : QPI Fast Read‘hEB (MAX. freq. 144MHz)

13.2 QPI Write Operation(s)

QPI write command can be input as ‘h02 or ‘h38.

0 1 2 3 4 5 6 7 8 9 10 11
CLK

CE#

SIO[3:0] 3 8 23:20 19:16 15:12 11:8 7:4 3:0 7:4 3:0 7:4 3:0

24bit Address
QPI Write Data In1 Data In2
CMD(‘h02 or 38)

Don't Care

Figure 14 : QPI Write ‘h02 or ‘h38

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

13.3 QPI Quad Mode Exit Operation

This command will switch the device back into serial I/O mode.

0 1
CLK

CE#

SIO[3:0] F 5

Quad Mode Exit

CMD(‘hF5)

Don't Care

Figure 15 : Quad Mode Exit ‘hF5

(only available in QPI mode)

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

14 RESET OPERATION

The Reset operation is used as a system (software) reset that puts the device in SPI standby mode
which is also the default mode after power-up. This operation consists of two commands: Reset-Enable
(RSTEN) and Reset (RST).

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK

CE#

SI 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1

SO High-Z

Reset Enable CMD(‘h66) Reset CMD(‘h99)

Don't Care Undefined

Figure 16 : SPI Reset

0 1 2 3
CLK

CE#

SIO[3:0] 6 6 9 9

RSTEN RST
CMD(‘h66) CMD(‘h99)

Don't Care

Figure 17 : QPI Reset

Reset command has to immediately follow the Reset-Enable command in order for the reset
operation to take effect. Any command other than the Reset command after the Reset-Enable
command will cause the device to exit Reset-Enable state and abandon reset operation.

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

15 INPUT / OUTPUT TIMING

tKHKL
tCH tCL tCLK
CLK
tCSP tCHD
CE# tCEM
tCPH
tHD
SI MSB in LSB in

tSP
SO High-Z

Don't Care Undefined

Figure 18 : Input Timing

tCLK tCH tCL

CLK

CE#
tHZ
tACLK
SI ADDR LSB in
tKOH

SO High-Z MSB out LSB out

Don't Care Undefined

Figure 19 : Output Timing

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

16 ELECTRICAL SPECIFICATIONS

16.1 Absolute Maximum Ratings*

Table 5: Absolute Maximum Ratings*

PARAMETER SYMBOL RATING UNIT NOTES

Voltage to any pad except VCC relative to VSS VT ‐0.3 to VCC +0.3 V
Voltage on VCC supply relative to VSS VCC ‐0.2 to +4.2 V
Storage Temperature TSTG ‐55 to +150 °C 1
Note: 1. Storage temperature refers to the case surface temperature on the center/top side of the PSRAM.

* Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not
meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute
Maximum Rating conditions for extended periods may affect device reliability.

16.2 Pin Capacitance

Table 6: Package Pin Capacitance

PARAMETER SYMBOL MIN. MAX. UNIT NOTES

Input Pin Capacitance CIN - 6 pF VIN=0V
Output Pin Capacitance COUT - 8 pF VOUT=0V
Note: 1. Spec’d at 25°C.

16.3 Operating Conditions

Table 7: Operating Characteristics

PARAMETER MIN. MAX. UNIT

Operating Temperature ‐40 85 °C

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

16.4 DC Electrical Characteristics

Table 8: DC Characteristics

SYMBOL PARAMETER MIN. MAX. UNIT NOTES

VCC Supply Voltage 2.7 3.6 V
VIH Input high voltage VCC‐0.4 VCC+0.2 V
VIL Input low voltage ‐0.2 0.4 V
VOH Output high voltage (IOH=‐0.2mA) 0.8 VCC - V
VOL Output low voltage (IOL=+0.2mA) - 0.2 VCC V
ILI Input leakage current - 1 µA
ILO Output leakage current - 1 µA
ICC Read/Write - 40 mA
ISB Standby current - 400 µA 1
Note: 1. Standby current is measured when CLK is in DC low state.

16.5 AC Electrical Characteristics

Table 9: READ/WRITE Timing

SYMBOL PARAMETER MIN. MAX. UNIT NOTES

CLK period - SPI Read(’h03) 30.3 - 33MHz
tCLK ns
CLK period – all other operations 7 - 144MHz*1,2
tCH / tCL Clock high/low width 0.45 0.55 tCLK(min)
tKHKL CLK rise or fall time - 1.5 ns
tCPH CE# HIGH between subsequent burst operations 50 - ns
tCEM CE# low pulse width - 8 µs
tCSP CE# setup time to CLK rising edge 2.5 - ns
tCHD CE# hold time from CLK rising edge 20 - ns
tSP Setup time to active CLK edge 2 - ns
tHD Hold time from active CLK edge 2 - ns
tHZ Chip disable to DQ output high‐Z - 6 ns
tACLK CLK to output delay 2 6 ns
tKOH Data hold time from clock falling edge 1.5 - ns
Note: 1. Only Linear Burst allows page boundary crossing. Frequency limits are therefore
144MHz MAX. without crossing page boundary, and
84MHz MAX. when burst commands cross page boundary.

2. For operating frequencies > 84MHz, refer to JEDEC JESD84-B50 for data sampling training.

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LY68L6400
Rev. 0.7 Preliminary 64M Bits Serial Pseudo-SRAM with SPI and QPI

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Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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