Laboratory Report Cover Sheet

UET ABBOTABAD CAMPUS

ELE-408
FPGA BASED SYSTEM DESIGN
7th Semester fall 2018

Name:
Register No./C.NO :
Venue: Computer Laboratory # 1
Lab No. : 1
Lab Tile : Programming Xilinx SPARTAN 3 Board (Simulation
through Implementation)

Date of Conduction:

Date of Submission:

Particulars Maximum Marks Marks Obtained

Pre –lab 20

Post-lab/lab report 40

In lab performance 40

Total 100

REPORT VERIFICATION
Date:

Instructor Name: Engr. Mehmoona Gul

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LAB #1
PROGRAMMING XILINX SPARTAN 3 BOARD (SIMULATION THROUGH
IMPLEMENTATION)

1.1 AIM
This lab session will show you how to program Spartan 3 FPGA board using Xilinx ISE 8.2i. As an example,
a half adder circuit will be implemented on the Spartan 3 board. The session begins by showing you how
to create a new project and how to describe the digital circuit in Verilog. After the circuit’s functionality
has been verified, it is then downloaded to the Spartan 3 board for implementation.

1.2 OBJECTIVE
• Introduce you to the Xilinx ISE software.
• Introduce to HDL coding.
• Creating a project using ISE.
• Loading the project to Spartan-3 board.
1.3 THEORY
1.3.1 CREATING A NEW PROJECT AND SOURCE
Start the Xilinx ISE 8.2i project navigator by double clicking the Xilinx ISE 8.2i icon on your desktop.

Click on File and select New Project

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Select a project location and type the name you would like to call your project “HalfAdder”.

Click Next

Select the device family, device, package, and speed grade as shown below:

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Click Next Click New Source

Select Verilog Module in the New Source Wizard window:

Click Next

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Specify the inputs and outputs of your design (HalfAdder). This is used to generate a template for your
Verilog code.

Click Next

Click Finish if you are satisfied your specifications shown in the summary page

Click Next

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Click Next

Verify the information on the Project Summary window:

Click Finish.

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Double-click on “HalfAdder-Behavioral(HalfAdder.v)” tab in the “Sources” pane.

The source file will now be displayed in the Project Navigator window . The source file window can be
used as a text editor to make any necessary changes to the source file. All the input/output pins will be
displayed. Save your Verilog program periodically by selecting the File->Save from the menu. You can
also edit Verilog programs in any text editor and add them to the project directory using “Add Copy
Source”.

Then click on synthesis-XST

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1.3.2 SYNTHESIS AND IMPLEMENTATION OF THE DESIGN
The design has to be synthesized and implemented before it can be checked for correctness, by running
functional simulation or downloaded onto the prototyping board. With the top-level Verilog file opened
(can be done by double-clicking that file) in the HDL editor window in the right half of the Project
Navigator, and the view of the project being in the Module view , the implement design option can be
seen in the process view. Design entry utilities and Generate Programming File options can also be seen
in the process view. The former can be used to include user constraints, if any and the latter will be
discussed later.

To synthesize the design, double click on the Synthesize Design option in the Processes window. To
implement the design, double click the Implement design option in the Processes window. It will go
through steps like Translate, Map and Place & Route. If any of these steps could not be done or done
with errors, it will place a X mark in front of that, otherwise a tick mark will be placed after each of them
to indicate the successful completion. If everything is done successfully, a tick mark will be placed before
the Implement Design option. If there are warnings, one can see yellow mark in front of the option
indicating that there are some warnings. One can look at the warnings or errors in the Console window
present at the bottom of the Navigator window. Every time the design file is saved; all these marks
disappear asking for a fresh compilation.

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1.3.3 FUNCTIONAL SIMULATION OF COMBINATIONAL DESIGNS
To check the functionality of a design, we have to apply test vectors and simulate the circuit. In order
to apply test vectors, a test bench file is written. Essentially it will supply all the inputs to the module
designed and will check the outputs of the module. Example: For the 2 input OR Gate, the steps to
generate the test bench is as follows:

In the Sources window (top left corner) right click on the file that you want to generate the test bench
for and select ‘New Source’ Provide a name for the test bench in the file name text box and select
‘Verilog test fixture’ among the file types in the list on the right side as shown in figure.

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Click on ‘Next’ to proceed. In the next window select the source file with which you want to associate
the test bench.

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Click on Next to proceed. In the next window click on Finish. You will now be provided with a template
for your test bench. If it does not open automatically click the radio button next to select behavioural
level.

You should now be able to view your test bench template. The code generated would be

something like this:

module o_gate_tb_v;

// Inputs

reg a;

reg b;

// Outputs

wire z;

// Instantiate the Unit Un

o_gate uut (

.a(a),

.b(b),

.z(z)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

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 // Add stimulus here

end

endmodule

The Xilinx tool detects the inputs and outputs of the module that you are going to test and assigns them
initial values. In order to test the gate completely we shall provide all the different input combinations.
‘#100’ is the time delay for which the input has to maintain the current value. After 100 units of time
have elapsed the next set of values can be assign to the inputs.

1.4 IN LAB TASK

Create simple project for basic gates and create test fixture.

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