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6CS4-04 Cao

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22 views

6CS4-04 Cao

Uploaded by

Udit Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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POORNIMA INSTITUTE OF ENGINEERING & TECHNOLOGY, JAIPUR

III B.TECH. (VI Sem.) Roll No. __________________


SECOND MID TERM EXAMINATION 2022-23
Code: 6CS4-04 Category: PCC Subject Name– COMPUTER ARCHITECTURE AND ORGANIZATION
(BRANCH – COMPUTER ENGINEERING)
Max. Time: 2 hrs. Max. Marks: 60
NOTE:- Read the guidelines given with each part carefully.

CO statement:
3. Use appropriate tools to design verify and test the CPU architecture and Learn the concepts of
parallel processing, pipelining and inter processor communication
4. Binary addition and subtraction, 2’s complement representation and operations with this
representation.
5. Exemplify in a better way the I/O and memory organization.

PO Key Words:
1. Knowledge 2. Apply 3. Analyze 4. Design 5. Evaluate 6. Create

CO PO PART - A: (All questions are compulsory) Max. Marks (10)


Q.1 4 2 Compare programmed I/O & interrupt driven I/O. (2)
Q.2 4 2 Give the comparison between CISC and RISC Processor? (2)
Q.3 4 1 What is locality of reference problem? (2)
Q.4 5 5 Show why does DMA have priority over the CPU when both request a memory (2)
transfer?
Q.5 4 4 Design 128 x 8 bit RAM. (2)

PART - B: (Attempt 4 questions out of 6) Max. Marks (20)


Q.6 5 5 Discuss working procedure of Daisy-chain priority interrupt with the help of its block (5)
diagram.
Q.7 3 1 Draw the hardware diagram and flow chart for addition and subtraction operations. (5)
Q.8 4 4 Construct a memory systern having static 1k x 4 RAM. How many such RAM’s will (5)
required to
(i) Construct 1K x 8 RAM bank?
(ii) 4kx4 RAM memory bank? Show the block diagram and the address decoding
circuit.

Q.9 4 3 Draw a Space Time diagram for a six-segment pipeline showing the time it takes to (5)
process eight tasks.
Q.10 4 1 Draw the block diagram of DMA Controller and explain it briefly. (5)

Q.11 3 1 Explain the address mapping using pages with appropriate diagram? (5)

PART - C: (Attempt 3 questions out of 4) Max. Marks (30)


Q.12 5 1 Why the cache memory is required? Explain the various types of mapping along with (10)
suitable diagram?
Q.13 4 4 Draw flow chart for 4 segment CPU pipeline and explain its working principle. Also (10)
write pipeline conflicts.
Q.14 4 2 Multiply (+13) and (-8) using Booth’s algorithm. (10)
Q.15 3,4 2 A content addressable memory consists of a memory array, logic, argument (10)
register:, key register- Draw block diagram, where key register(k), argument register
each having n bits, match register(m) , has m bits, array and logic for m words with n
bits per word.

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