Experiment 3

BOOLEAN ALGEBRA AND LOGIC GATES

Objectives:

1. To be able to verify the truth tables of various logic gates.

2. To be able to implement different basic logic functions using a single type of gate.
3. To be able to validate De Morgan’s theorem using a digital logic trainer.
4. To familiarize the student on the use of the digital logic trainer in verifying logic functions.

Introductory Information:

All logic circuits are constructed based on the three most basic logic functions: NOT, OR,
and AND. It is from these functions and combinations thereof, that more complex functions are
implemented, even in Very Large Scale Integration (VLSI).

A logic variable is a binary variable, that is, it can acquire one of two states. Specific
combinations or occurrences of logic variables may be detected by the proper application of logic
functions.

To facilitate analysis of these circuits, truth tables are employed. These are tabular forms
showing corresponding output states for each combination of the input variables. Logic LOW or
FALSE conditions are indicated by a binary 0, while logic HIGH or TRUE conditions are
indicated by a binary 1.

Functions may be expressed in different ways: the minterm list form expresses a function
as the logical sum of all product terms which produce a high output, while the maxterm list form
expresses a function as a logical product of all sum terms which produce a low output, where
each term is represented by the decimal value of the combination of binary variables.

The minimal sum-of-product (SOP) form expresses functions as the sum of minterms.
The minimal product-of-sums (POS) form expresses a function as the product of maxterms.
These two forms are particularly useful because they allow us to derive minimal two-level
implementations.

Boolean Algebra allows us to simplify complex and often redundant logic circuits so that
they may be implemented using a minimum number of logic gates. On the other hand, engineers
are particularly interested in minimum chip count designs. This calls for the ability to implement
a desired function using specific logic gates. De Morgan’s theorem bridges the gap between the
AND and the OR function. The theorems and their duals are summarized below:
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Experiment No. 3: Boolean Algebra and Logic Gates
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 Commutative A+B = B+A AB = BA
Associative (A+B)+C = A+(B+C) (AB)C = A(BC)
Distributive A(B+C) = AB + AC A+BC = (A+B)(A+C)
Identity A+A = A AA = A
Negation (A)’ = A’ A’’ = A
Redundancy A+AB = A A(A+B) = A
Basic Relations 0+A = A 1A = A
1+A = 1 0A = 0
Useful Relations A’+A = 1 A’A = 0
A+A’B = A+B A(A’+B) = AB
De Morgan’s Theorem (A+B)’ = A’B’ (AB)’ = A’+B’

There are numerous tools that allow the engineer to simplify these logic functions, other
than algebraic manipulation. Among the graphical techniques, Karnaugh-Mapping (K-Map) is
the fastest. However, it becomes unmanageable as the number of variables exceeds six. On the
other hand, the Quine-McCluskey method lends itself to computerization, despite its tediousness.

As important as the ability to simplify and implement complex functions are, the design
of logic circuit begins with the translation of a problem or a situation into a valid workable
expression. Synthesis then becomes a mechanical procedure as the engineer gains experience
through practice.

Materials/Equipment:

1 Digital Logic Trainer including connecting wires with plugs

Procedure:

1. Digital Logic Trainer

The logic trainer consists of an internal +5 volts DC source, NAND gates, AND-OR gates,
JK flip-flops, and adjustable clock source, logic pulsers, switched outputs and LED driver
inputs. Notice that each terminal provides two sockets to allow multiple connections. Never
connect two outputs (be it gate, switch, clock or pulser outputs) together. The logic trainer
uses TTL devices with standard totem-pole outputs, which do not allow such connection.

If a fixed level is to be applied, derive this signal from the HIGH and GND sockets provided.
The HIGH sockets are derived from buffer outputs and cannot drive an external device, for
example, a logic probe.
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 The switch output is HIGH when up, and LOW when down. The LED glows when they
detect a HIGH input, and are otherwise off. The pulsers are normally LOW, but become
HIGH when the button is depressed. These outputs are debounced to prevent switching
spikes from being detected as multiple pulses.

2. Familiarize yourselves with the different parts of a Digital Logic Trainer. Take note of the
logic gates, switches, output led, pulses, etc.
Before starting to use the Digital Logic Trainer, plug-in the power cord into the mains. Once
plugged-in, the Digital Logic Trainer is ready to use.
3. Connect the circuit shown in Figure 1 and complete the given truth table. Use the switches to
set the input to either 1 or 0 and the lamps to determine the states of the output.
4. Based on the truth table obtained, what is the logic function of this circuit?

A B
0
1

Table 1 Figure 1

5. Modify the previous circuit by connecting one of the inputs to logic HIGH (Figure 2), and
complete the given truth table.
6. Based on the truth table obtained, what is the logic function of this circuit?

A B
0
1

Table 2 Figure 2

7. Remove the logic HIGH signal from the gate, leaving it floating (Figure 3), and complete the
given truth table.
8. Based on the truth table obtained, what is the logic function of this circuit?

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 A B
0
1

Table 3 Figure 3

As a general rule, unasserted inputs (no connections) are internally pulled up to logic
HIGH, but it is safer to tie unused or HIGH inputs to known levels.

Logic Gates
9. Connect the circuits shown in Figures 4 to 9 and complete the respective truth tables. Also
identify the function performed by each circuit through the completed truth tables.

A B C
0 0
0 1
1 0
1 1

Table 4 Figure 4

Function: _____________________________________________________________

A B C
0 0
0 1
1 0
1 1

Table 5 Figure 5

Function: _____________________________________________________________

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 A B C
0 0
0 1
1 0
1 1

Table 6 Figure 6

Function: _____________________________________________________________

A B C
0 0
0 1
1 0
1 1

Table 7 Figure 7

Function: _____________________________________________________________

A B C
0 0
0 1
1 0
1 1

Table 8 Figure 8

Function: _____________________________________________________________

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 A B C
0 0
0 1
1 0
1 1

Table 9 Figure 9

Function: _____________________________________________________________

10. Prove the equality of the circuits shown in Figures 6 to 9 using Boolean Algebra.

11. Connect and determine the truth tables of the remaining three input and four input functions
provided on the logic trainer as seen in Figure
A B C D 10, Figure 11 and Figure 12.
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 10 Figure 10

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 A B C D E
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Table 11 Figure 11

A B C D E
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table 12 Figure 12

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Implementation
12. Connect the circuit described by the following equation using NAND gates:

D(A,B,C) = ((AC)’  (B’+C’)  (A’B)’)’

Draw your circuit, and obtain its truth table.

A B C D
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 13

13. Simplify and express the above equation in canonical sum-of-products form or minterm list
form.

14. Does the minterm in procedure 13 matches Table 13?

Simplification of Circuits
15. Connect the circuit shown in Figure 13 and obtain its truth table.

Figure 13

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 A B C D
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 14

16. Connect the circuit shown in Figure 14 and obtain its truth table.

A B C D
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 15 Figure 14

17. Compare Table 14 and Table 15. Do they match?

Guide Questions:

1. Describe two ways by which an inverter can be implemented using a 3-input NOR gate.
2. Using only 2-input NOR gates, give minimal designs to implement all six basic 2-input
functions.
3. Is it possible to implement the same six functions using only OR gates or AND gates?
4. What are the disadvantages of higher-level implementations over 1-level and 2-level
implementations?
5. It can be shown that all logic functions may be implemented using two level designs. Some
two-level designs can be simplified to a single level, for example, a two-level AND-AND
circuit degenerates to an AND gate. Using the 16 possible two-level implementations given
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 below, identify the degenerate forms, and the resulting one-level function. Identify also the
non-degenerate forms, and determine where each two-level implementation below can be
derived from (SOP or POS form).

AND-AND AND-NAND NAND-AND NAND-NAND

AND-OR AND-NOR NAND-OR NAND-NOR
OR-AND OR-NAND NOR-AND NOR-NAND
OR-OR OR-NOR NOR-OR NOR-NOR

References:

Mano, Morris, Digital Design. Prentice-Hall, Inc. 1984

Taub, Herbert and Schilling, Donald. Digital Integrated Electronics. Mc Graw-Hill Book
Company. 1977

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