Vlsi - June 2022

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B 0300EcT30405220L

RegNo.: Name: :-gRD


APJ ABDUL K4.LAM TECHNOLOGICAL UNIVERS
Sixth Semester B.Tech Degree Examination June 2022 (2019

Course Code: ECT304


Course Name: VL$ CIRCUIT DESIGN
Max. Marks: 100 Duration: 3 Hours

PART A
Answer all qaestions, each carries 3 marks.
I FPGA
What is FPGA? What are the characteristics and applications of (3)

2 Compare Top down and Bottom up approach in VLSI design (3)

J Design a 2xl multiplexer using CMOS logic (3)

4 Draw the circuit of a MOS inverter with saturated NMOS load (3)

) What are the issues associated with NP domino logic (3)

6 Compare DRAM and SRAM cells (3)

7 What is the need for array multipliers (3)

8 Mention the worst-case delay associated with Carry-Bypass adder, Linear (3)

Carry-Select adder, Square- root carry select adder


9 What is meant by lithography? Explain various types of Lithography (3)

l0 With an example, explain the role of stick diagram in WSI design (3)

PART B
Answer onefull questionfrom each module, eoch corries 14 mnrks.
Module I
1l a) With neat diagram explain the design flow of FPGA (7)

b) What is SoC? What are the applications? Draw the internal architecture of6oC (7)

OR
12 a) Explain the term ASIC. Differentiate between full custom and semi custom ASIC (10)

b) Explain the significance of power considerations in VLSI (4)

Module II
13 4 Illustrate CMOS inverter DC characteristics with neat diagrams. Explain the (10)

different regions
b) Implement the 4xl multiplexer using Transmission gates (4)

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OR
14 a) What is meant by pass tmnsistor logic? What are the differences in transmission (10)
characteristics ofN MOS and P MOS transistors?

b) Realize the logic function X: ((A+B).(C+D))' using CMOS logic (4)

Module III
15 a) Design three transistor and one transistor DRAM cells and explain the working of (10)

each types

b) Explain the basic principle of operation of dynamic logic (4)

OR
16 a) Design a 4x4 NAND based MOS ROM Cell Array and explain its operation (10)

b) Compare the performance of dynamic and domino logic (4)


'l
Module IV
17 a) multiplier
With diagram illustrate the principle of operation of an array (4)

b) Design a l6-bit square-root carry select adder and indicate the worst-case delay (10)

OR
I 8 a) Design a 4X4 array multiplier. Show the critical path and also estimate the delay of ( l0)
the multiplier.
.
b) Write the advantages of square-root carry select adder compared to linear carry (4)

select adder

Module V
19 a) What are the steps in wafer preparation fabrication (4)
-
I
b) Desuibe in detail about the production of single crystalline silicon from CZ (10)

process

OR

* 20 a) With neat diagram explain molecular beam epitaxy (8)

b) What is meant by design rules? Write*rort notes on various rules in VLSI cfrip (6)

design.
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