EXP No. 3.

Study and Verify NAND gate as a Universal Gate

AIM
To Study and Verify NAND gate as a Universal Gate.

APPARATUS REQUIRED
SL NO. COMPONENT SPECIFICATION QUANTITY
1 NAND GATE IC 7400 1
Logisim Software - -

THEORY

Universal gate

The NAND and NOR gates are called Universal gates, because all the logic gates and logic
functions can be implemented using NAND and NOR gates.
NAND Gate as Universal gate

a. NAND GATE AS INVERTER: The circuit diagram of implementation of

NAND gate as inverter is shown below:

INPUT A OUTPUT
Y
0 1
1 0

b. NAND GATE AS AND GATE: The circuit diagram of implementation of

NAND gate as AND gate is shown below:

INPUT A INPUT B OUTPUT Y

0 0 0

Department of Electrical Engineering

Government College of Engineering, Keonjhar 1
 0 1 0
1 0 0
1 1 1

c. NAND GATE AS OR GATE: The circuit diagram of implementation of NAND

gate as OR gate is shown below:

INPUT A INPUT B OUTPUT Y

0 0 1
0 1 1
1 0 1
1 1 0

d. NAND GATE AS NOR GATE: The circuit diagram of implementation of

NAND gate as is shown below:

INPUT A INPUT B OUTPUT Y

0 0 1
0 1 0
1 0 0
1 1 0

SET_SU r2
 e. NAND GATE AS EX-OR GATE The circuit diagram of implementation of
NAND gate as is shown below:

INPUT A INPUT B OUTPUT Y

0 0 0
0 1 1
1 0 1
1 1 0

PROCEDURE:

1. Make the connections as per the logic diagram.

2. Apply diff combinations of inputs to the i/p terminals
3. Note o/p for NAND as universal gate.
4. Verify the truth table.

RESULT: - The NAND gate as a Universal Gate is verified.

SET_SU 3
 EXPERIMENT NO: -4

Realize binary adder circuits using logic gates.

AIM
To realize half adder using Logic gates.

APPARATUS REQUIRED
SL NO. COMPONENT SPECIFICATION QUANTITY
1 XOR GATE IC 7486 1
2 AND GATE IC 7408 1
3 Logisim Software - -

THEORY

Half-Adder: A combinational logic circuit that performs the addition of two data bits,
A and B, is called a half-adder. Addition will result in two output bits; one of which is
the sum bit S, and the other is the carry bit, C. The Boolean functions describing the
half-adder are:
𝑆 = 𝐴⨁𝐵

𝐶 = 𝐴. 𝐵

SET_SU r4
Truth Table

INPUT A INPUT B 𝑌 = 𝐴 ⊕ 𝐵 C=A.B

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

PROCEDURE: -

1. Connect the circuit as shown and get the output of Sum and Carry separately.
2. Take input from pin no. 1&2 of IC no.7486 and take output at pin no.3.
3. Short pin no.1 of IC no.7486 to pin no.1 of IC no.7408.
4. Similarly, short pin no.2 of IC no.7486 to pin no.2 of IC no.7408.
5. Take output at Pin no.3 of IC no.7408 and connect to LED.

OBSERVATION [L=logic 0, H=logic 1]

INPUT A INPUT B 𝑌 = 𝐴 ⊕ 𝐵 C=A.B

L L
L H
H L
H H

RESULT: -The truth table of half adder is verified.

SET_SU 5
 Experiment 5
AIM
To realize full adder using Logic gates.

APPARATUS REQUIRED
SL NO. COMPONENT SPECIFICATION QUANTITY
1 XOR GATE IC 7486 1
2 AND GATE IC 7408 1
3 OR GATE IC 7432
7 Logisim Software - -

THEORY

Full Adder: The half-adder does not take the carry bit from its previous stage into
account. This carry bit from its previous stage is called carry-in bit. A combinational
logic circuit that adds two data bits, A and B, and a carry-in bit,𝐶𝑖𝑛 is called a full-adder.
The Boolean functions describing the full-adder are:

𝑆 = 𝐴 ⊕ 𝐵⨁𝐶𝑖𝑛 𝐶 = 𝐴. 𝐵 + 𝐶𝑖𝑛(𝐴⨁𝐵)

SET_SU r6
Truth Table

INPUT INPUT INPUT 𝑆 = 𝐴 ⊕ 𝐵⨁𝐶𝑖𝑛 𝐶 = 𝐴. 𝐵 + 𝐶𝑖𝑛(𝐴⨁𝐵)

A B 𝐶𝑖𝑛
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

PROCEDURE: -

1. Connect the circuit as shown and get the output of Sum and Carry separately.
2. Make the connections as per the circuit diagram for the full adder circuit, on the trainer
kit.
3. Verify that the outputs are according to the expected results.

OBSERVATION [L=logic 0, H=logic 1]

INPUT INPUT INPUT 𝑆 = 𝐴 ⊕ 𝐵⨁𝐶𝑖𝑛 𝐶 = 𝐴. 𝐵 + 𝐶𝑖𝑛(𝐴⨁𝐵)

A B 𝐶𝑖𝑛
L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H

RESULT: -The truth table of full adder is verified.

SET_SU 7
 Exp 6 To realize subtractor circuits using Logic gates.

AIM
To realize half subtractor using Logic gates.

APPARATUS REQUIRED
SL NO. COMPONENT SPECIFICATION QUANTITY
1 XOR GATE IC 7486 1
2 AND GATE IC 7408 1
3 NOT GATE IC 7404

THEORY

Half- subtractor: Subtracting a single-bit binary value B from another A (i.e., A-B)
produces a difference bit D and a borrow out bit B0. This operation is called half
subtraction and the circuit to realize it is called a half subtractor. The Boolean functions
describing the halfsubtractor are:

𝐷 = 𝐴⨁𝐵
𝐵0 = 𝐴′𝐵
.

SET_SU r8
Truth Table

INPUT INPUT 𝐷 = 𝐴⨁𝐵 𝐵0 = 𝐴′𝐵

A B
0 0 0 0
0 1 0 1
1 0 1 0
1 1 0 0

PROCEDURE: -

1. Connect the circuit as shown and get the output of difference and borrow separately.
2. Take input from pin no. 1&2 of IC no.7486 and take output at pin no.3.
3. Pin no.3 is connected with LED.
4. Short pin no.1 of IC no.7486 to pin no.1 of IC no.7404 and take output at pin no.2 of
IC no 7404.
5. Short pin no.2 of IC no.7404 to pin no.1 of IC no.7408.
6. Similarly, short pin no.2 of IC no.7486 to pin no.2 of IC no.7408.
7. Take output at Pin no.3 of IC no.7408 and connect to LED.
OBSERVATION [L=logic 0, H=logic 1]

INPUT INPUT 𝐷 = 𝐴⨁𝐵 𝐵0 = 𝐴′𝐵

A B
L L
L H
H L
H H

RESULT: -The truth table of half subtractor is verified.

SET_SU 9
 EXP 7
AIM

To realize full subtractor using Logic gates.

APPARATUS REQUIRED
SL NO. COMPONENT SPECIFICATION QUANTITY
1 XOR GATE IC 7486 1
2 AND GATE IC 7408 1
3 OR GATE IC 7432
4 NOT GATE IC 7404

THEORY

Full-subtractor: Subtracting two single-bit binary values, B, C from a single-bit value

A produces a difference bit D and a borrow out B0 bit. This is called full subtraction.
The Boolean functions describing the full subtractor.

𝐷 = 𝐴⨁𝐵 ⊕ 𝐶
𝐵0 = 𝐴′𝐵 + 𝐴′𝐶 + 𝐵𝐶

Truth Table

SET_SU r 10
 INPUT INPUT INPUT 𝐷 = 𝐴⨁𝐵 ⊕ 𝐶 𝐵0 = 𝐴′𝐵 + 𝐴′𝐶 + 𝐵𝐶
A B 𝐶𝑖𝑛
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 0 1

PROCEDURE: -

1. Connect the circuit as shown and get the output of Difference and Borrow separately.
2. Make the connections as per the circuit diagram for the full substractor circuit, on the
trainer kit.
3. Switch on the VCC power supply and apply the various combinations of the inputs
according to the respective truth tables.
4. Verify that the outputs are according to the expected results.

OBSERVATION [L=logic 0, H=logic 1]

INPUT INPUT INPUT 𝐷 = 𝐴⨁𝐵 ⊕ 𝐶 𝐵0 = 𝐴′𝐵 + 𝐴′𝐶 + 𝐵𝐶

A B 𝐶𝑖𝑛
L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H

RESULT: -The truth table of full subtractor is verified.

SET_SU 11