Unit III

To understand the working of 555 timer

3.2.1 To list the features of 555 timer

3.2.2 To explain the functional block diagram of 555 timer

3.2.3 To explain the working of astable and monostable circuits using 555 timer

3.2.4 To write the expression for time period of astable and monostable circuits using 555

3.2.5 To describe LM 380 audio power amplifier

555 TIMER IC
The 555 Timer, designed by Hans Camenzind in 1971, can be found in many electronic devices
starting from toys and kitchen appliances to even a spacecraft. It is a highly stable integrated circuit
that can produce accurate time delays and oscillations. The 555 Timer has three operating modes,
bistable, monostable and astable mode.

The internal schematics of 555 Timer which consists of 25 transistors, 2 diodes and 15 resistors.

Functional diagram of 555 Timer IC

Represented with a block diagram it consists of 2 comparators, a flip-flop, a

voltage divider, a discharge transistor and an output stage.

The voltage divider consists of three identical 5k resistors which create two reference voltages at 1/3
and 2/3 of the supplied voltage, which can range from 5 to 15V.
Next are the two comparators. A comparator is a circuit element that compares two analog input
voltages at its positive (non-inverting) and negative (inverting) input terminal. If the input voltage at
the positive terminal is higher than the input voltage at the negative terminal the comparator will
output 1. Vice versa, if the voltage at the negative input terminal is higher than the voltage at the
positive terminal, the comparator will output 0.

The upper comparator negative input terminal is connected to the 2/3 reference voltage at the
voltage divider and the external “control” pin, while the positive input terminal to the external
“Threshold” pin. On the other hand, the lower comparator negative input terminal is connected to
the “Trigger” pin, while the positive input terminal to the 1/3 reference voltage at the voltage
divider.

So using the three pins, Trigger, Threshold and Control, we can control the output of the
two comparators which are then fed to the R and S inputs of the flip-flop. The flip-flop will output 1
when R is 0 and S is 1, and vice versa, it will output 0 when R is 1 and S is 0. Additionally the flip-flop
can be reset via the external pin called “Reset” which can override the two inputs, thus reset the
entire timer at any time.

The Q-bar output of the flip-flip goes to the output stage or the output
drivers which can either source or sink a current of 200mA to the load. The output stage is usually an
inverter. The output of the flip-flip is also connected to a transistor Q1 that connects the
“Discharge” pin to ground.

555 Timer – Monostable Mode

 In the stand by state, FF output is LOW making Q HIGH, holds the transistor Q1 ON, thus
clamping the external timing capacitor C to ground. The output remains at ground potential, i.e.,
LOW. As the trigger passes through Vcc/3, the lower comparator output becomes HIGH and S input of
the FF becomes 1, now the FF is set, i.e., Q = 0. This makes the transistor Q1 off and the short circuit
across the timing capacitor C released. As Q is LOW , the output goes HIGH. The timing cycle now
begins.
 Since C is unclamped, voltage across it rises exponentially through R towards Vcc with a time
constant RC . After a time period T, the capacitor voltage is just greater than (2/3)V CC and the upper
comparator resets the flip-flop, that is, R = 1, S = 0. This makes Q = 1, transistor Q1 goes ON, thereby
discharging the capacitor C rapidly to ground potential. The output returns to the standby state or
ground potential.

So we can notice that the amount of time the output of the 555 Timer is High,
depends on how much time the capacitor needs to charge to 2/3 of the supplied voltage, and that
depends on the values of both the capacitor C1 and the resistor R1.

The voltage across the capacitor is given by,

vc = VCC(1 – e-t/R1C1)

vc = (2/3) VCC

therefore, (2/3) VCC = VCC(1 – e-T/R1C1)

or, T = R1C1 ln(3)

or, T = 1.1 R1C1 seconds.

Once triggered, the output remains in the HIGH state until the time T elapses, which depends only
upon R1 and C1. Any additional trigger pulse coming during this time will not change the output state.
However , if a negative going reset pulse is applied to the reset terminal during the timing cycle,
transistor Q2 goes OFF, Q1 becomes ON and the external timing capacitor C1 is immediately
discharged. If the reset is released, the output will still remain LOW until a negative going trigger
pulse is again applied at pin 2.
555 Timer – Astable Multivibrator

In this mode the IC becomes an oscillator or also called Free Running Multivibrator. It doesn’t have a
stable state and continuously switches between High and Low without application of any external
trigger. Here’s an example circuit of the 555 Timer operating in astable mode.

We only need two resistors and a capacitor. The Trigger and Threshold pins are connected to each
other so there is no need of external trigger pulse.

Initially, the voltage source will start charging the capacitor through the Resistors R1 and R2. While
charging the lower comparator will output 1 because the input voltage at the Trigger pin is still lower
than 1/3 of the supplied voltage. That means that the Q-bar output is 0 and the discharge transistor
is closed. At this time the output of the 555 Timer is High.

Once the voltage across the capacitor reaches 1/3 of the supplied voltage, the lower comparator will
output 0 but at this point that won’t do any change as both R and S inputs of the flip-flop are 0. So
the voltage across the capacitor will keep rising, and once it reaches 2/3 of the supplied voltage, the
upper comparator will output 1 to the R input of the flip-flop. This will make Q = 0,and Q= 0 and now
the discharge transistor turns ON and the capacitor will start discharging through the resistor R2 and
the discharging transistor. At this moment the output of the 555 Timer is Low.

While discharging, the voltage across the capacitor starts to decline, and the upper comparator away
output becomes 0, which actually doesn’t do any change as now both R and S inputs of the flip-flop
are 0. But once the voltage across the capacitor drops to 1/3 of the supplied voltage, the lower
comparator will output 1. This will turn off the discharge transistor and the capacitor will start to
charge again. So this processes of charging and discharging between 2/3 and 1/3 of the supplied
voltage will keep running on its own, thus producing a square wave on the 555 Timer output.

We can calculate the time the output is High and Low. The High time depends the on the resistance
of both R1 and R2, as well as the capacitance C of the capacitor. On the other hand, the Low time
depends only on the resistance of R2 and the capacitance C of the capacitor. If we sum the High and
Low times we will get the Period of one cycle.

The voltage across the capacitor is given by

vc = VCC(1 – e-t/RC)

the time T1 taken by the circuit to charge from 0 to (2/3)VCC is,

(2/3) VCC = VCC(1 – e-T1/(R1 +R2)C)

or, T1 = (R1+R2 )C ln(3)

or, T1 = 1.09 (R1+R2 )C seconds.

And time T2 taken by the circuit to charge from 0 to (1/3)VCC is,

(1/3) VCC = VCC(1 – e-T2/( R2)C)

T2 = 0.405 R2C

So the time to charge from (1/3)VCCto (2/3)VCC is

THIGH = T1 – T2
 = 0.69 (RA+RB )C

The output is LOW while the capacitor discharges from (2/3)VCC to (1/3)Vcc and the voltage across the
capacitor is given by

1/3) VCC = (2/3)VCCe-TLOW/R2C

TLOW = 0.69 R2C

Both R1 and R2 are in the charge path, but only R2 is in the discharge path. Therefore , total time,

T = THIGH + TLOW.

T = 0.69(R1+2R2)C

f = 1/T.

The device 555 is a monolithic timing circuit that can produce accurate and highly stable time delays
or oscillations. Some important applications of this device are- monostable and astable
multivibrators, dc-dc converters, digital logic probes, waveform generators, analog frequency
meters and tachometers, temperature measurement and control , infrared transmitters, burglar and
toxic gas alarms, voltage regulators , etc. The 555 timer is reliable , easy to use and economical.

The timer 555 is available as a 8-pin metal can, a 8-pin mini DIP, or a
14-pin DIP. The SE 555 timer is designed for an operating temperature range from -55 0C to +1250C
while the NE 555 operates over a temperature range of 00C to 700C. The important features are:

1. Operating voltage range : +5 V to +18 V.

2. Adjustable duty cycle.
3. Timing from micro seconds to hours.
4. High current output.
5. Capacity to source or sink current of 200 µA.
6. Output can drive TTL gates.
7. Reliable, easy to use & low cost.

PIN Details :

Pin 1 : Ground – All voltages are measured with respect to this terminal.
Pin 2 : Trigger – The output of the timer depends on the amplitude of the external triggers pulse
applied to this pin .

Pin 3 : Output – There are two ways a load can be connected to the output terminal, either between
pin 3 and ground ( pin 1), or between pin 3 and supply voltage +Vcc(pin 8).

Pin 4 : Reset – The device 555 is reset by applying a negative pulse to this pin when the reset
function is not in use. The reset terminals should be connected to +Vcc to avoid any possibility of
false triggering.

Pin 5 : Control voltage –An external voltage applied to this terminal changes the threshold as well as
the trigger voltage. By imposing a voltage on this pin, the pulse width of the output waveform can
be varied. When not used, the control pin should be bypassed to ground with a 0.01 µF capacitor to
prevent any noise disturbances.

Pin 6 : Threshold – This is the non-inverting terminal of the upper comparator, which monitors the
voltage across the external capacitor. When the voltage at this pin exceeds (2/3)V cc, the output of
the upper comparator goes high, which in turn switches the output of the timer low.

Pin 7 : Discharge – This pin is connected internally to the collector of the discharge transistor Q 1.
When the output is high, Q1is off and acts as an open circuit to the external capacitor connected
between pin 7 and ground. When the output is low, Q1 is saturated and acts as a short circuit,
shorting at the external capacitor C to ground.

Pin 8 : +Vcc – The supply voltage of +5V to +18 V is applied to this pin with respect to ground.

Applications of monostable multivibrator :

Pulse width modulation, Missing pulse detector, Linear ramp generator,

Water level fill control, Frequency divider etc.

Applications of astable multivibrator :

FSK generator, Pulse position modulator, Square wave oscillator, Free running ramp
generator etc.

3.1.0 To comprehend the working of PLL

3.1.1 To explain the general block diagram of PLL

3.1.2 To define capture range lock-in range, and pull-in time of PLL
3.1.3 To explain the block diagram of NE/ SE 566 Voltage Controlled Oscillator

3.1.4 To list the important electrical characteristics of the 565 PLL

3.1.5 To explain the functional block diagram of PLL NE/ SE 565

3.1.6 To describe the applications of PLL as frequency multiplier and FM demodulator

Phase Locked Loops

A phase-locked loop, or more commonly known as PLL, is basically closed loop

feedback system. The action of PLL is to lock the output frequency and phase to the frequency and
phase of an input signal. The input signal can be sinusoidal or digital.

The PLL is used in communication system in two fundamentally different ways :

1. As a demodulator, where it is used to follow phase or frequency

2. To track a carrier or synchronizing signal which may vary in frequency with time.

The realization of the PLL as an inexpensive IC has made it one of the most
frequently used communication circuit. The PLL has been used for filtering,
frequency synthesis motor speed control, frequency modulation, demodulation,
signal detection and a variety of other applications.

BASIC PRINCIPLES

This feedback system consists of :

1. Phase detector / Comparator

2. Low Pass Filter
3. Error Amplifier
4. Voltage Controlled Oscillator (VCO)
 The VCO is a free running multivibrator and operates at a set frequency fo called free running
frequency. This frequency is determined by an external timing capacitor and an external resistor. It
can also be shifted to either side by applying a DC control voltage vc to the appropriate terminal of
the IC. The frequency deviation is directly proportional to the control voltage and hence it is called a
Voltage Controlled Oscillator.

If an input signal vs of frequency fs is applied to the PLL, the phase detector compares the phase and
frequency of the incoming signal to that of the the output vo the VCO. If the two signals differ in
frequency and / or phase, an error voltage ve is generated. The phase detector is basically a
multiplier and produces the sum (fs + fo) and difference (fs - fo) components at its output. The high
frequency component (fs + fo) is removed by the low pass filter and the difference frequency
component is amplified and then applied as control voltage vc to VCO. The signal vc shifts the VCO
frequency in a direction to reduce the frequency difference between f s and fo . once this action
starts, we say that the signal is in the capture range. The VCO continues to change frequency till its
output frequency is exactly the same as the input signal frequency. The circuit is then said to be
locked. Once locked , the output frequency fo of VCO is identical to fs except for a finite phase
difference. This phase difference generates a corrective control voltage v c to shift the VCO
frequency from fo to fs and thereby maintain the lock. Once locked , PLL tracks the frequency
changes of the input signal. Thus a PLL goes through three stages : free running, capture and locked
or tracking.

The low pass filter controls the capture range. If the VCO frequency is far away , the beat
frequency will be too high to pass through the filter and the PLL will not respond. We say that the
signal is out of the capture band. However, once locked, the filter no longer restricts the PLL. The
VCO can track the signal well beyond the capture band. Thus tracking range is always lager than the
capture range.

Lock – in - Range : Once the PLL is locked, it can track frequency changes in the incoming signals.

The range of frequencies over which the PLL can maintain lock with the incoming signals is called the
lock-in-range or tracking range . The lock range is usually expressed as a percentage of fo ,the VCO
frequency.

Capture Range : The range of frequencies over which a PLL can acquire lock with an input signal is
called the capture range . this is also expressed as a percentage of fo ,the VCO frequency.
Pull- in –Time : the total time taken by a PLL to establish lock is called pull-in-time. This depends on
initial phase and frequency difference between the two signals.

Voltage Controlled Oscillator VCO

The VCO is a free running multivibrator and operates at a set frequency called free running
frequency. This frequency is determined by an external timing capacitor and an external resistor. It
can also be shifted to either side by applying a DC control voltage vc. to the appropriate terminal of
the IC. The frequency deviation is directly proportional to the dc control voltage and hence it is
called Voltage Controlled Oscillator. The NE/SE 566 is a commonly available VCO.
 A timing capacitor CT is charged linearly or discharged by a constant current
source and 0.5 Vcc / sink. The current value can be controlled in two ways either by changing the
control voltage vc given at the modulating input (pin 5) or by changing the timing resistor R T
connected externally to IC chip. The voltage at pin 6 is same as that of pin 5. Suppose the modulating
voltage at pin 5 is increased, the voltage at pin 6 also increases. It causes less voltage across R T and
thereby decreasing the charging current.

The voltage across the capacitor CT is applied to the inverting input terminal of
Schmitt trigger A2 through a buffer amplifier A1. The output voltage swing of the Schmitt trigger is
designed to Vcc and 0.5 Vcc. . If Ra= Rb in the positive feedback loop, the voltage at the non-inverting
input terminal of A2 swings from 0.5 Vcc and 0.25 Vcc. When the voltage on the capacitor CT exceeds
0.5 Vcc during charging, the output of the Schmitt trigger goes LOW (0.5 Vcc). The capacitor now
discharges and when it is at 0.25 Vcc, the output of Schmitt trigger goes HIGH. Since the source and
sink are equal, capacitor charges and discharges forb the same amount of time. This gives a
triangular voltage waveform across CT Δv which is also available at pin 4. The square wave output of
the Schmitt trigger is inverted by the inverter A3 and is available at pin 3.

The output frequency of the VCO can be calculated as follows:

The total voltage on the capacitor changes from 0.25 Vcc to 0.5 Vcc .

Thus Δv = 0.25 Vcc

So Δv / Δt = i / CT

0.25 Vcc / Δt = i / CT

Δt = ( 0.25 Vcc CT) / i

The time period T of the triangular waveform = 2 Δt

The frequency of oscillation fo is, fo = 1 / T = 1 / 2Δt

= i / ( 0.5 Vcc CT)

But , i = (Vcc –vc )/ RT

Where vc is the voltage at pin 5. fo = 2 (Vcc –vc )/ CT RT VCC

The output frequency of the VCO can be changed either by : RT , CT , the voltage at pin 5.

Phase Locked Loop IC PLL 565

The SE/NE 565 is the most commonly used monolithic phase locked loop.

The important electrical characteristics of 565 PLL are :

Operating frequency range : 0.001 Hz to 500 KHz.

Operating voltage range : ± 6 V to ± 12 V

Input level : 10 m V rms to 3V

Input Impedance : 10 KΩ

Output sink current : 1 milli amp

Drift in VCO centre frequency

With temperature : 300 ppm/oC.

Drift in VCO centre frequency

With supply voltage : 1.5 % /V

Triangular wave amplitude : 2.4 VPP at ± 6 V supply voltage

Square wave amplitude : 5.4 VPP at ± 6 V supply voltage.

The device is available as a 14 pin DIP package or as a 10 pin metal can package. The output
frequency of the VCO can be written as, fo = (0.25 / CT RT) Hz, where CT and RT are external
capacitor and resistor connected to pin 8 and pin 9. A value between 2KΩ and 20 KΩ is
recommended for RT. The VCO running frequency is adjusted with RT and CT, to be at the centre
frequency of the input frequency range.
PLL loop is internally broken between the VCO output and the phase comparator input. A short
circuit between pins 4 and 5 connects the VCO output to the phase comparator input so as to
compare fo and the input signal fs. a comparator C is connected between pin 7 and pin 10 to make a
low pass filter with the internal resistance of 3.6 kΩ.

PLL Applications

The output from a PLL system can be obtained either as the voltage signal corresponding to the
error voltage in the feedback loop, or as a frequency signal at VCO. The voltage output is used in
frequency discriminator applications whereas the frequency output is used in signal conditioning,
frequency synthesis, or clock recovery applications.

Some of the typical applications of PLL are :

1. Frequency multiplication / Division 5. FSK Demodulator

2. Frequency translation 6. Frequency synthesizer
3. AM Detection
4. FM Demodulation
Frequency multiplier

The frequency multiplier using the 565 PLL is shown in figure.

A frequency divider is inserted between the VCO and the phase comparator. Since the
output of the divider is locked to the input frequency fin, the VCO is actually running at multiples of
the input frequency . The desired amount of multiplication can be obtained by selecting a proper
divide by N network, where N is an integer. To verify the operation of the circuit, one must
determine the input frequency range and then adjust the free running frequency f out of the VCO by
means of a frequency divider circuit.

FM Demodulator /Detector

The PLL set up can be used for FM demodulation. Let the PLL is locked to a FM signal. Under this
condition, the VCO follows the instantaneous frequency of the input signal. The VCO is controlled by
the filtered error voltage. The error voltage also maintains lock with the input signal.
LM 380 AUDIO POWER AMPLIFIER

A power amplifier is required to deliver large amount of power and hence it has to
handle large current, in order to achieve high power amplification. Thus the main features of a
large signal amplifier or a power amplifier are :

1. Large amount of power to be delivered to the load.

2. Power efficiency
3. Impedance matching to the output device.

The large signal amplifiers develop an ac power of the order of a few Watts. Similarly large
power gets dissipated in the form of heat, at the junction of the transistor used in the power
amplifiers. Hence the transistors used in such amplifiers are power transistors with heat sinks

LM 380 is a popular audio amplifier produced by National Semiconductors. It is

capable of delivering 2.5 W to 8Ω load. Hence it is very much ideal for consumer applications. It
requires minimum number of external components. A copper lead frame used with the central three
pins (3,4,5,10,11,12) on either side of the DIP package forms a heat sink. Thus there is no need to
use separate heat sink.

Features of LM 380 Audio Amplifier :

1. Internally fixed gain (34 dB)

2. Wide supply voltage range ( 5 to 22 V)
3. Output is automatically self centering to one half of the supply voltage.
4. Low quiescent power drain
5. High peak current capability (1.3 A)
6. High input impedance
7. Low total harmonic distortion
8. Standard dual-in-line package

Block diagram of LM 380

Figure shows the pin configuration and block diagram of LM 380.

The use of LM 380 as an audio amplifier is shown in figure.

The IC can be used in both inverting and non-inverting configuration.

In the above figure it is being used in non-inverting mode. The inverting terminal can be either
shorted to ground, left open or returned to ground through a resistor or capacitor.

The capacitor C2 is used to cancel the effects of inductance in the power supply leads. A lag
compensating RC network must be connected from the output to ground to avoid oscillations.