Chapter 8

Sequential Circuits

The technology enabling and supporting 8.1 Latches

modern digital devices is critically depen-
dent on electronic components that can
store information, i.e., have memory We A storage element in a digital circuit can
will examine the operation and control of maintain a binary state indefinitely (as long
these devices and their use in circuits and as power is delivered to the circuit), until
enables you to better understand what directed by an input signal to switch states
is happening in these devices when you Such a storage element is called a latch The
interact with them The digital circuits major differences among various types of
considered thus far have been combina- storage elements are in the number of in-
tional—their output depends only and im- puts they possess and in the manner in
mediately on their inputs—they have no which the inputs affect the binary state
memory, i.e., dependence on past values
of their inputs Sequential circuits, however,
act as storage elements and have memory,
i.e., their output depends on past inputs as 8.1.1 SR Latch
well

The main way sequential circuits remem-

ber things is through feedback paths and
memory elements We know how combina- The SR latch is a circuit with two cross-
tional circuits are created The simplest stor- coupled NOR gates or two cross-coupled
age elements (memory) used in sequential NAND gates, and two inputs labeled S and
circuits are called latches R Let’s analyze. . .

53
54 Chapter 8. Sequential Circuits

The SR latch with two cross-coupled

NAND gates behaves in a similar way
to NOR implementation It operates with
both inputs normally at 1, unless the state
of the latch has to be changed

The application of 0 to the S input causes

The latch has two stable states output Q to go to 1, putting the latch in the
When output Q = 1 and Q’ = 0, the latch set state When the S input goes back to
is said to be in the set state S 1, the circuit remains in the set state The
When Q = 0 and Q’ = 1, it is in the reset condition that is forbidden for the NAND
state latch is both inputs being equal to 0 at
We realize that the outputs Q and Q’ are the same time, an input combination that
normally the complement of each other should be avoided
Setting and resetting can be done through
the two inputs (SR) After setting or re- 8.1.3 Latch with enable
setting, applying 00 at the input retains
the previous state However, when both in-
puts are equal to 1 at the same time, a
condition in which both outputs are equal
to 0 (rather than be mutually comple-
mentary) occurs If both inputs are then
switched to 0 simultaneously, the device will
enter an unpredictable or undefined state or
a metastable state The operation of the basic SR latch can be
modified by providing an additional input
8.1.2 SR Latch – NAND implemen- signal that determines (controls) when the
tation state of the latch can be changed by de-
termining whether S and R (or S and R )
can affect the circuit It consists of the basic
SR latch and two additional NAND gates
The control input En acts as an enable sig-
nal for the other two inputs The outputs of
the NAND gates stay at the logic-1 level
as long as the enable signal remains at 0
8.1 Latches 55

This is the quiescent condition for the SR One way to eliminate the undesirable con-
latch dition of the indeterminate state in the SR
latch is to ensure that inputs S and R are
never equal to 1 at the same time This is
done in the D latch The D input goes di-
rectly to the S input, and its complement is
applied to the R input As long as the enable
input is at 0, the cross-coupled SR latch has
both inputs at the 1 level and the circuit
cannot change state regardless of the value
When the enable input goes to 1, infor- of D The D input is sampled when En = 1.
mation from the S or R input is allowed If D = 1, the Q output goes to 1, placing
to affect the latch The set state is reached the circuit in the set state If D = 0, output
with S = 1, R = 0, and En = 1 (active-high Q goes to 0, placing the circuit in the reset
enabled) and reset is reached with S = 0, state
R = 1, and En = 1 In either case, when The D latch receives that designation
En returns to 0, the circuit remains in its from its ability to hold data in its inter-
previous stable state Further, when En = 1 nal storage It is suited for use as a tempo-
and both the S and R inputs are equal to rary storage for binary information between
0, the state of the circuit does not change a unit and its environment The binary in-
An indeterminate condition occurs when formation present at the data input of the
all three inputs are equal to 1 This condi- D latch is transferred to the Q output when
tion places 0’s on both inputs of the basic the enable input is asserted The output fol-
SR latch, which puts it in the undefined lows changes in the data input as long as
state When the enable input goes back to 0, the enable input is asserted This situation
one cannot conclusively determine the next provides a path from input D to the out-
state, because it depends on whether the put, and for this reason, the circuit is often
S or R input goes to 0 first This indetermi- called a transparent latch
nate condition makes this circuit difficult to
manage, and it is seldom used in practice
Nevertheless, the SR latch is an important
circuit in conjunction with other modifica-
tions

8.1.4 D Latch When the enable input signal is de- as-

serted, the binary information that was
present at the data input at the time the
transition occurred is retained (i.e., stored)
at the Q output until the enable input is as-
serted again Note that an inverter could be
placed at the enable input Then, depend-
ing on the physical circuit, the external en-
56 Chapter 8. Sequential Circuits

abling signal will be a value of 0 (active low) through two transitions: from 0 to 1 and the
or 1 (active high) return from 1 to 0 The positive transition
(0-¿1) is defined as the positive edge and the
8.1.5 Problem with latches negative transition (1-¿0) as the negative
edge
A sequential circuit has a feedback path
from the outputs of the flip-flops to the
input of the combinational circuit Con-
sequently, the inputs of the latches are
derived in part from the outputs of the
same and other latches The state transi-
tions of the latches start as soon as the en-
able/data pulse changes to the logic-1 level
The new state of a latch appears at the out-
put while the pulse is still active This out-
put is connected to the inputs of the latches
through the combinational circuit If the in-
puts applied to the latches change again
while the enable pulse is still at the logic-1 We can implement flip flops using two
level, the latches will respond to new values latches The first latch is called the master
and a new output state may occur The re- and the second the slave The circuit sam-
sult is an unpredictable situation, since the ples the D input and changes its output Q
state of the latches may keep changing for as only at the negative edge of the synchro-
long as the enable pulse stays at the active nizing or controlling clock (designated as
level Because of this unreliable operation, Clk) When the Clk = 0, the slave latch
the output of a latch cannot be applied di- is enabled, and its output Q is equal to
rectly or through combinational logic to the the master output Y When the input pulse
input of the same or another latch when all changes, the data from the external D input
the latches are triggered by a enable signal are transferred to the master

8.2 Flip Flops The slave, however, is disabled as long as

the clock remains at the 1 level, because its
Flip-flops are constructed in such a way as enable input is equal to 0 Any change in
to make them operate properly when they the input changes the master output at Y,
are part of a sequential circuit that employs but cannot affect the slave output When
a common clock The problem with the latch the clock pulse returns to 0, the master is
is that it responds to a change in the level of disabled and is isolated from the D input
a clock pulse A positive level response in the At the same time, the slave is enabled and
enable input allows changes in the output the value of Y is transferred to the output
when the D input changes while the clock of the flip-flop at Q Thus, a change in the
pulse stays at logic 1 The key to the proper output of the flip-flop can be triggered only
operation of a flip-flop is to trigger it only by and during the transition of the clock
during a signal transition A clock pulse goes from 1 to 0 (-ve edge)
8.2 Flip Flops 57

are enabled, the output is complemented

This can be obtained if the D input is:

D = JQ′ + KQ

When J = 1 and K = 0, D = Q’ + Q = 1,
so the next clock edge sets the output to 1
When J = 0 and K = 1, D = 0, so the next
clock edge resets the output to 0 When both
J = K = 1 and D = Q’, the next clock edge
8.2.1 JK Flip Flop
complements the output When both J = K
= 0 and D = Q, the clock edge leaves the
output unchanged Because of their versa-
tility, JK flip-flops are called universal flip-
flops

8.2.2 D Flip Flop

Transparent flip-flop The bit at D is trans-
ferred to Q at the edge of the clock The
information is retained upto the next edge
of the clock
There are four operations we are looking to
perform in a flip-flop: Set it to 1, reset it 8.2.3 T Flip Flop
to 0, retain or complement its output With
only a single input, the D flip-flop can set or
reset the output, depending on the value of
the D input immediately before the clock
transition Synchronized by a clock signal,
the JK flip- flop has two inputs and per-
forms all four operations

The T (toggle) flip-flop is a complement-

ing flip-flop and can be obtained from a JK
flip-flop when inputs J and K are tied to-
gether When T = 0 (J = K = 0), a clock
edge does not change the output When T
= 1 (J = K = 1), a clock edge complements
The J input sets the flip-flop to 1, the K the output The complementing flip-flop is
input resets it to 0, and when both inputs useful for designing binary counters
58 Chapter 8. Sequential Circuits

The T flip-flop can also be constructed

using a D flip-flop The expression for the D
input is:

D = T ′ Q + T Q′

When T = 0, D = Q and there is no

change in the output When T = 1, D = Q’
The direct inputs are useful for bringing
and the output complements The graphic
all flip-flops in the system to a known start-
symbol for this flip-flop has a T symbol in
ing state prior to the clocked operation.
the input
When the reset input is 0, it forces output
Q’ to stay at 1, which, in turn, clears out-
put Q to 0, thus resetting the flip-flop

8.4 Analysis

Analysis describes what a given circuit will

do under certain operating conditions The
behavior of a clocked sequential circuit is
determined from the inputs, the outputs,
and the state of its flip-flops The outputs
8.3 Asynchronous inputs and the next state are both a function of the
inputs and the present state The analysis of
Some flip-flops have asynchronous inputs a sequential circuit consists of obtaining a
that are used to force the flip-flop to a par- table or a diagram for the time sequence
ticular state independently of the clock The of inputs, outputs, and internal states It is
input that sets the flip-flop to 1 is called pre- also possible to write Boolean expressions
set or direct set The input that clears the that describe the behavior of the sequential
flip-flop to 0 is called clear or direct reset circuit These expressions must include the
When power is turned on in a digital sys- necessary time sequence, either directly or
tem, the state of the flip-flops is unknown indirectly
8.4 Analysis 59

The Boolean expressions for the state

equations can be derived directly from the
gates that form the combinational circuit
part of the sequential circuit, since the D
values of the combinational circuit deter-
mine the next state Similarly, the present-
state value of the output can be expressed
algebraically as

y(t) = [A(t) + B(t)]x′ (t) (8.1)

By removing the symbol (t) for the present

state, we obtain the output Boolean equa-
Consider this sequential circuit It consists tion:
of two D flip-flops A and B, an input x and
an output y Since the D input of a flip-flop y = (A + B)x′ (8.2)
determines the value of the next state (i.e.,
the state reached after the clock transition),
it is possible to write a set of state equations
for the circuit as:
A(t + 1) = A(t)x(t) + B(t)x(t)
B(t + 1) = A′ (t)x(t) 8.4.2 State tables

Similar to truth tables, the derivation of a

8.4.1 State equations
state table requires listing all possible bi-
A state equation is an algebraic expression nary combinations of present states and in-
that specifies the condition for a flip-flop puts
state transition The left side of the equa-
In this case, we have eight binary com-
tion, with (t + 1), denotes the next state of
binations from 000 to 111 The next-state
the flip-flop one clock edge later The right
values are then determined from the logic
side of the equation is a Boolean expres-
diagram or from the state equations The
sion that specifies the present state and in-
next state of flip-flops must satisfy the state
put conditions Since all the variables in the
equations:
Boolean expressions are a function of the
present state, we can omit the designation
( t ) after each variable for convenience and A(t + 1) = Ax + Bx
can express the state equations in the more B(t + 1) = A′ x
compact form
A(t + 1) = Ax + Bx
B(t + 1) = A′ x Output is derived from:
y = (A + B)x’
60 Chapter 8. Sequential Circuits

8.4.3 State diagram

The information available in a state table
can be represented graphically in the form
of a state diagram In this type of diagram,
a state is represented by a circle, and the
(clock- triggered) transitions between states
are indicated by directed lines connecting
the circles

In general, a sequential circuit with m

flipflops and n inputs needs 2m+n rows in
the state table The binary numbers from
0 through 2m+n - 1 are listed under the
present-state and input columns The next-
state section has m columns, one for each
flip-flop The binary values for the next The binary number inside each circle
state are derived directly from the state identifies the state of the flip-flops The di-
equations The output section has as many rected lines are labeled with two binary
columns as there are output variables Its numbers separated by a slash The input
binary value is derived from the circuit or value during the present state is labeled
from the Boolean function in the same man- first, and the number after the slash gives
ner as in a truth table the output during the present state with the
It is sometimes convenient to express the given input
state table in a slightly different form hav- For example, the directed line from state
ing only three sections: present state, next 00 to 01 is labeled 1/0, meaning that when
state, and output The input conditions are the sequential circuit is in the present state
enumerated under the next-state and out- 00 and the input is 1, the output is 0 Af-
put sections ter the next clock cycle, the circuit goes to
the next state, 01 If the input changes to
0, then the output becomes 1, but if the in-
put remains at 1, the output stays at 0 This
information is obtained from the state dia-
gram along the two directed lines emanat-
ing from the circle with state 01 A directed
line connecting a circle with itself indicates
that no change of state occurs