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Lecture 5P1

The document discusses sequential logic circuits, which depend on present inputs and past outputs, and are categorized into synchronous and asynchronous types. It explains the function of flip-flops as basic memory elements and introduces latches, including SR latches and gated latches, highlighting their operational differences. The document also includes truth tables and examples for various latch configurations.

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7 views

Lecture 5P1

The document discusses sequential logic circuits, which depend on present inputs and past outputs, and are categorized into synchronous and asynchronous types. It explains the function of flip-flops as basic memory elements and introduces latches, including SR latches and gated latches, highlighting their operational differences. The document also includes truth tables and examples for various latch configurations.

Uploaded by

ff5352235
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CT 221 : DIGITAL ELECTRONICS 1

Unit 3: Sequential logic circuits


Introduction
 The logic circuits whose outputs at any instant of time
depend on the present inputs as well as on the past
outputs are called sequential circuits.
 In sequential circuits, the output signals are fed back to
the input side.
 A block diagram of a sequential circuit is shown in
A Z
External External
External
Inputs
Inputs Combinational Logic
Output
y Y
Internal Outputs (next
Internal state variables)
inputs Memory
(present state
variables)
Introduction
 Sequential circuits are classified broadly into synchronous
sequential circuits and asynchronous sequential circuits
 Synchronous sequential circuits are controlled by a master
clock
 The operation of asynchronous sequential circuits are not
controlled by any clock pulses. The output change
immediately to a change in input.
 Flip-flop is the basic memory element in sequential circuits.
 A flip-flop is a sequential circuit which can store a 1 or a 0
indefinitely.
Basic Bistable Element
 A circuit which indefinitely store a 1 or 0 is called a basic
bistable element.
a a
Q

b Q
b

Figure: basic bistable element


Basic Bistable Element
 A flip-flop is a bistable circuit with input lines.
 The flip-flop remains in one of its two stable states until
power is switched off or until an input signal triggers a
change in state.
 A flip-flop is said to be set or preset when an input
forced it to store a 1 and it is said to be reset or cleared
when an input signal causes the flip-flop to store a 0.
Latches
 A latch is a class of flip-flops whose output responds
immediately to appropriate changes in the input in spite
of the presence of an enable or clock input.
 There are several types of latches based on types of
inputs and enable lines.
 Latch are similar to flip-flops because they are bistable
devices.
 The main difference between latches and flip-flops is in
the method used for changing state.
Latches
SR Latch
 Two NOR gates are cross coupled in order to configure a SR latch.
 A NOR gate-based SR Latch is an active HIGH latch- is set or reset
with a HIGH logic
 S and R stand for the set and reset inputs of the latch while
𝑄 𝑎𝑛𝑑 𝑄 areRthe two outputs
R Q

Q
S
Latches
SR Latch
 The symbol and truth table of the SR latch are shown

Row S R 𝑸+ 𝑸+ S Q
no.
0 0 0 𝑄 𝑄
1 0 1 0 1
R Q
2 1 0 1 0
3 1 1 0 0* Third row is invalid

 𝑄 and 𝑄 represent the state of latch when the inputs are applied.
 𝑄 represent the present state of the latch while 𝑄 + and 𝑄 + denotes
the response of the output to the input applied.
Latches
SR Latch
 When 𝑆 = 𝑅 = 0, assume  When 𝑆 = 𝑅 = 0, assume
that 𝑄 = 0 and 𝑄 = 1 that 𝑄 = 1 and 𝑄 = 0

R 0 0 Q R 0 1 Q

1 0

0 1
1 Q 0 Q
S S
0 0
Latches
SR Latch
 When S=1, and R=0.
𝑄 =1
𝑄=0

R 0 Q R 0 Q

0 1 11
1 0 00

0 1 11
Q Q
S
S
1 0 00
1 1
Latches
SR Latch
 Let the inputs be S=0, R=1.

𝑄=0 𝑄 =1

R 1 Q R 1 Q
00 1 0
11 0 1

00 1 0
Q Q
S S
11 0 1
0 0
Latches
SR Latch
 Now let S=R=1 , the logic conditions of the latch is shown
below
R 1 Q R 1 Q
1 0 00 00 1 0

00 Q 1 0
S Q
S
1 1 0 00
1

 Observe that the outputs are no longer complementary but both


𝑄 and 𝑄 are 0
 Therefore the S=R=1 input is forbidden input
Latches
SR Latch
 Example: draw the waveforms at Q and 𝑄 if the following
signals are applied at S and R inputs of SR latch. Assume
Q is initially HIGH.
Latches
𝑆𝑅 Latch
 The set-reset latch can be configured using cross coupled
NAND gates as shown in figure below with its symbol
and truth table R# 𝑺 𝑹 𝑸+ 𝑸+
R𝑆 Q
0 0 0 1 1* (invalid)
S Q
1 0 1 1 0

2 1 0 0 1
R Q
Q 3 1 1 𝑄 𝑄
S𝑅

A NAND gate-based SR Latch is an active LOW latch- i.e., it is set or reset with a LOW logic
Latches
𝑆𝑅 Latch
 If the S’ and R’ waveform in figure below are applied to
the inputs of the latch, determine the waveform that will
be observed on the Q output. Assume that Q is initially
low
Latches
Gated SR Latch
 Inputs which cause a response only synchronous with enable or
clock input are called synchronous inputs.
 A gated SR latch has synchronous inputs S and R along with clock
or enable input E and is constructed as shown in figures below

A NAND gate-based SR Latch is now an active HIGH latch- i.e., it is set or reset with a HIGH logic
Latches
Gated SR Latch
 The symbol and truth table of gated SR latch are shown
below
S R E 𝑸+ 𝑸+
S Q
0 0 1 𝑄 𝑄
0 1 1 0 1 C𝐸
1 0 1 1 0
R Q
1 1 1 0 0*
X X 0 𝑄 𝑄
Latches
Gated SR Latch

S Q

C𝐸

R Q
Latches
Gated SR Latch

S Q

C𝐸

R Q
Latches
Gated D Latch
 The very structure of a D latch avoids the S=R=1
condition

D
X
Q

C𝐸

Q
Y
Latches
Gated D Latch
 The symbol and truth table are shown in figure below

D E 𝑸+ 𝑸+
D Q
0 1 0 1

1 1 1 0

Q X 0 𝑄 𝑄
C𝐸

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