INTEGRATED CIRCUITS

DATA SHEET

74LVC157A
Quad 2-input multiplexer
Product specification 2003 Dec 02
Supersedes data of 2003 Jun 17
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

FEATURES Inputs can be driven from either 3.3 or 5 V devices. This

feature allows the use of these devices as translators in a
• 5 V tolerant inputs for interfacing with 5 V logic
mixed 3.3 and 5 V environment.
• Wide supply voltage range from 1.2 to 3.6 V
The 74LVC157A is a quad 2-input multiplexer which select
• CMOS low power consumption
four bits of data from two sources under the control of a
• Direct interface with TTL levels common select input (S). The four outputs present the
• Inputs accept voltages up to 5.5 V selected data in the true (non-inverted) form. The enable
input (E) is active LOW. When pin E is HIGH, all of the
• Complies with JEDEC standard no. 8-1A
outputs (1Y to 4Y) are forced LOW regardless of all the
• ESD protection: other input conditions. Moving the data from two groups of
HBM EIA/JESD22-A114-A exceeds 2000 V registers to four common output buses is a common use of
MM EIA/JESD22-A115-A exceeds 200 V. the 74LVC157A. The state of the common data select
• Specified from −40 to +85 °C and −40 to +125 °C. input (S) determines the particular register from which the
data comes. It can also be used as function generator.
DESCRIPTION The device is useful for implementing highly irregular logic
by generating any 4 of the 16 different functions of two
The 74LVC157A is a high-performance, low-power,
variables with one variable common.
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families. The 74LVC157A is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to pin S.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

tPHL/tPLH propagation delay
nI0, nI1 to nY CL = 50 pF; VCC = 3.3 V 2.6 ns
E to nY CL = 50 pF; VCC = 3.3 V 2.8 ns
S to nY CL = 50 pF; VCC = 3.3 V 2.6 ns
CI input capacitance 5.0 pF
CPD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 15 pF

Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.

2003 Dec 02 2
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

FUNCTION TABLE
See note 1.
INPUT OUTPUT
E S nI0 nI1 nY
H X X X L
L L L X L
L L H X H
L H X L L
L H X H H

Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.

ORDERING INFORMATION

TEMPERATURE PACKAGE
TYPE NUMBER
RANGE PINS PACKAGE MATERIAL CODE
74LVC157AD −40 to +125 °C 16 SO16 plastic SOT109-1
74LVC157ADB −40 to +125 °C 16 SSOP16 plastic SOT338-1
74LVC157APW −40 to +125 °C 16 TSSOP16 plastic SOT403-1
74LVC157ABQ −40 to +125 °C 16 DHVQFN16 plastic SOT763-1

PINNING

PIN SYMBOL DESCRIPTION

1 S common data select input
2 1I0 data input from source 0
3 1I1 data input from source 1
4 1Y multiplexer output
5 2I0 data input from source 0
6 2I1 data input from source 1
7 2Y multiplexer output
8 GND ground (0 V)
9 3Y multiplexer output
10 3I1 data input from source 1
11 3I0 data input from source 0
12 4Y multiplexer output
13 4I1 data input from source 1
14 4I0 data input from source 0
15 E enable input (active LOW)
16 VCC supply voltage

2003 Dec 02 3
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

handbook, halfpage S VCC

1 16

handbook, halfpage 1I0 2 15 E

S 1 16 VCC

1I0 2 15 E 1I1 3 14 4I0

1I1 3 14 4I0
1Y 4 13 4I1
1Y 4 13 4I1 GND(1)
157 2I0 5 12 4Y
2I0 5 12 4Y

2I1 6 11 3I0 2I1 6 11 3I0

2Y 7 10 3I1 7 10 3I1
2Y
GND 8 9 3Y 8 9
MNA480
Top view GND 3Y MDB106

(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.

Fig.1 Pin configuration SO16 and (T)SSOP16. Fig.2 Pin configuration DHVQFN16.

handbook, halfpage 1
G1
15 EN
handbook, halfpage 2 3 5 6 11 10 14 13

2
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 1 MUX 4
1 S 3
1
5
15 E 7
6
1Y 2Y 3Y 4Y
11
9
4 7 9 12 10
MNA481
14
12
13

MNA482

Fig.3 Logic symbol. Fig.4 Logic symbol (IEEE/IEC).

2003 Dec 02 4
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

handbook, halfpage

2 1I0
1Y 4
3 1I1

5 2I0
2Y 7
6 2I1
MULTIPLEXER
3I0 SELECTOR
11 OUTPUTS
3Y 9
10 3I1

14 4I0
4Y 12
13 4I1

S E
1 15 MNA483

Fig.5 Functional diagram.

handbook, halfpage
S

1I1
1Y

1I0

2I1
2Y

2I0

3I1
3Y

3I0

4I1
4Y

4I0 MNA484

Fig.6 Logic diagram.

2003 Dec 02 5
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage for maximum speed performance 2.7 3.6 V
for low voltage applications 1.2 3.6 V
VI input voltage 0 5.5 V
VO output voltage 0 VCC V
Tamb operating ambient temperature −40 +125 °C
tr, tf input rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI < 0 − −50 mA
VI input voltage note 1 −0.5 +6.5 V
IOK output diode current VO > VCC or VO < 0 − ±50 mA
VO output voltage note 1 −0.5 VCC + 0.5 V
IO output source or sink current VO = 0 to VCC − ±50 mA
ICC, IGND VCC or GND current − ±100 mA
Tstg storage temperature −65 +150 °C
PD power dissipation Tamb = −40 to +125 °C; note 2 − 500 mW

Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO16 packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of PD derates linearly with 4.5 mW/K.

2003 Dec 02 6
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input 1.2 VCC − − V
voltage 2.7 to 3.6 2.0 − − V
VIL LOW-level input 1.2 − − GND V
voltage 2.7 to 3.6 − − 0.8 V
VOH HIGH-level output VI = VIH or VIL
voltage IO = −100 µA 2.7 to 3.6 VCC − 0.2 − − V
IO = −12 mA 2.7 VCC − 0.5 − − V
IO = −18 mA 3.0 VCC − 0.6 − − V
IO = −24 mA 3.0 VCC − 0.8 − − V
VOL LOW-level output VI = VIH or VIL
voltage IO = 100 µA 2.7 to 3.6 − − 0.2 V
IO = 12 mA 2.7 − − 0.4 V
IO = 24 mA 3.0 − − 0.55 V
ILI input leakage VI = 5.5 V or GND 3.6 − ±0.1 ±5 µA
current
ICC quiescent supply VI = VCC or GND; 3.6 − 0.1 10 µA
current IO = 0
∆ICC additional quiescent VI =VCC − 0.6 V; 2.7 to 3.6 − 5 500 µA
supply current per IO = 0
input pin

2003 Dec 02 7
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb = −40 to +125 °C
VIH HIGH-level input 1.2 VCC − − V
voltage 2.7 to 3.6 2.0 − − V
VIL LOW-level input 1.2 − − GND V
voltage 2.7 to 3.6 − − 0.8 V
VOH HIGH-level output VI = VIH or VIL
voltage IO = −100 µA 2.7 to 3.6 VCC − 0.3 − − V
IO = −12 mA 2.7 VCC − 0.65 − − V
IO = −18 mA 3.0 VCC − 0.75 − − V
IO = −24 mA 3.0 VCC − 1 − − V
VOL LOW-level output VI = VIH or VIL
voltage IO = 100 µA 2.7 to 3.6 − − 0.3 V
IO = 12 mA 2.7 − − 0.6 V
IO = 24 mA 3.0 − − 0.8 V
ILI input leakage VI = 5.5 V or GND 3.6 − − ±20 µA
current
ICC quiescent supply VI = VCC or GND; 3.6 − − 40 µA
current IO = 0
∆ICC additional quiescent VI =VCC − 0.6 V; 2.7 to 3.6 − − 5000 µA
supply current per IO = 0
input pin
Note
1. All typical values are measured at Tamb = 25 °C.

2003 Dec 02 8
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns.

TEST CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb = −40 to +85 °C; note 1
tPHL/tPLH propagation delay nI0, see Figs 8 and 9 1.2 − 16 − ns
nI1 to nY 2.7 1.0 3.0 5.9 ns
3.0 to 3.6 1.0 2.6(2) 5.2 ns
propagation delay E to nY see Figs 7 and 9 1.2 − 17 − ns
2.7 1.0 3.4 7.8 ns
3.0 to 3.6 1.0 2.8(2) 6.5 ns
propagation delay S to nY see Figs 8 and 9 1.2 − 16 − ns
2.7 1.0 3.0 7.3 ns
3.0 to 3.6 1.0 2.6(2) 6.3 ns
tsk(0) skew note 3 3.0 to 3.6 − − 1.0 ns
Tamb = −40 to +125 °C
tPHL/tPLH propagation delay nI0, see Figs 8 and 9 1.2 − − − ns
nI1 to nY 2.7 1.0 − 7.5 ns
3.0 to 3.6 1.0 − 6.5 ns
propagation delay E to nY see Figs 7 and 9 1.2 − − − ns
2.7 1.0 − 10.0 ns
3.0 to 3.6 1.0 − 8.5 ns
propagation delay S to nY see Figs 8 and 9 1.2 − − − ns
2.7 1.0 − 9.5 ns
3.0 to 3.6 1.0 − 8.0 ns
tsk(0) skew note 3 3.0 to 3.6 − − 1.5 ns

Notes
1. All typical values are measured at Tamb = 25 °C.
2. This typical value is measured at VCC = 3.3 V and Tamb = 25 °C.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.

2003 Dec 02 9
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

AC WAVEFORMS

handbook, halfpage VCC

E input VM

GND
t PHL t PLH
VOH

nY output VM

VOL MNA485

INPUT
VCC VM
VI tr = tf
1.2 V 0.5 × VCC VCC ≤ 2.5 ns
2.7 V 1.5 V 2.7 V ≤ 2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns

VOL and VOH are typical output voltage drop that occur with the output load.

Fig.7 Enable input (E) to output (nY) propagation delays.

handbook, halfpage VI
nI0, nI1, S
VM
input
GND
t PHL t PLH
VOH

nY output VM

VOL MNA486

INPUT
VCC VM
VI tr = tf
1.2 V 0.5 × VCC VCC ≤ 2.5 ns
2.7 V 1.5 V 2.7 V ≤ 2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns

VOL and VOH are typical output voltage drop that occur with the output load.

Fig.8 Data inputs (nI0, nI1) and common data select input (S) to output (nY) propagation delays.

2003 Dec 02 10
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

handbook, full pagewidth S1 2 × VCC

open
VCC
RL GND
VI VO 500 Ω
PULSE
D.U.T.
GENERATOR
CL RL
RT 50 pF 500 Ω
MNA368

VEXT
VCC VI CL RL
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
1.2 V VCC 50 pF 500 Ω(1) open GND 2 × VCC
2.7 V 2.7 V 50 pF 500 Ω open GND 2 × VCC
3.0 to 3.6 V 2.7 V 50 pF 500 Ω open GND 2 × VCC
Note
1. The circuit performs better when RL = 1000 Ω.

Definitions for test circuits:

RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig.9 Load circuitry for switching times.

2003 Dec 02 11
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

PACKAGE OUTLINES

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

D E A
X

y HE v M A

16 9

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 8 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ

0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0o
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT109-1 076E07 MS-012
03-02-19

2003 Dec 02 12
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

D E A
X

c
y HE v M A

16 9

Q
A2 A
A1 (A 3)

pin 1 index
θ
Lp
L

1 8 detail X

w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
o
0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.00 8
mm 2 0.25 0.65 1.25 0.2 0.13 0.1
0.05 1.65 0.25 0.09 6.0 5.2 7.6 0.63 0.7 0.55 0o

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT338-1 MO-150
03-02-19

2003 Dec 02 13
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

D E A
X

y HE v M A

16 9

Q
A2 (A 3)
A
A1
pin 1 index

θ
Lp
L
1 8
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
o
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8
mm 1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0o

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT403-1 MO-153
03-02-18

2003 Dec 02 14
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm SOT763-1

D B A

A
A1
E c

terminal 1 detail X
index area

terminal 1 C
e1
index area
e b v M C A B y1 C y
w M C
2 7

1 8

Eh e

16 9

15 10
Dh
X

0 2.5 5 mm

scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT
max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1

mm 0.05 0.30 3.6 2.15 2.6 1.15 0.5

1 0.2 0.5 2.5 0.1 0.05 0.05 0.1
0.00 0.18 3.4 1.85 2.4 0.85 0.3

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

02-10-17
SOT763-1 --- MO-241 ---
03-01-27

2003 Dec 02 15
Philips Semiconductors Product specification

Quad 2-input multiplexer 74LVC157A

DATA SHEET STATUS

DATA SHEET PRODUCT

LEVEL DEFINITION
STATUS(1) STATUS(2)(3)
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DEFINITIONS DISCLAIMERS
Short-form specification  The data in a short-form Life support applications  These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition  Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes  Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes in the products -
Characteristics sections of the specification is not implied. including circuits, standard cells, and/or software -
Exposure to limiting values for extended periods may described or contained herein in order to improve design
affect device reliability. and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information  Applications that are
communicated via a Customer Product/Process Change
described herein for any of these products are for
Notification (CPCN). Philips Semiconductors assumes no
illustrative purposes only. Philips Semiconductors make
responsibility or liability for the use of any of these
no representation or warranty that such applications will be
products, conveys no licence or title under any patent,
suitable for the specified use without further testing or
copyright, or mask work right to these products, and
modification.
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

2003 Dec 02 16
Philips Semiconductors – a worldwide company

Contact information

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For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

© Koninklijke Philips Electronics N.V. 2003 SCA75

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands R20/05/pp17 Date of release: 2003 Dec 02 Document order number: 9397 750 12371