74VHC74 Dual D-Type Flip-Flop with Preset and Clear

October 1992
Revised February 2005

74VHC74
Dual D-Type Flip-Flop with Preset and Clear
General Description Features
The VHC74 is an advanced high speed CMOS Dual D- ■ High Speed: fMAX 170 MHz (typ) at TA 25qC
Type Flip-Flop fabricated with silicon gate CMOS technol- ■ High noise immunity: VNIH VNIL 28% VCC (min)
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low ■ Power down protection is provided on all inputs
power dissipation. The signal level applied to the D input is ■ Low power dissipation: ICC 2 PA (max) at TA 25qC
transferred to the Q output during the positive going transi- ■ Pin and function compatible with 74HC74
tion of the CK pulse. CLR and PR are independent of the
CK and are accomplished by setting the appropriate input
LOW.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.

Ordering Code:
Package
Order Number Package Description
Number
74VHC74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC74MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC74MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 1) Wide
74VHC74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

© 2005 Fairchild Semiconductor Corporation DS011505 www.fairchildsemi.com

74VHC74
Logic Symbol Connection Diagram
IEEE/IEC

Pin Descriptions Truth Table

Pin Names Description Inputs Outputs Function

D1 , D2 Data Inputs CLR PR D CK Q Q

L H X X L H Clear
CK1, CK2 Clock Pulse Inputs
H L X X H L Preset
CLR1, CLR2 Direct Clear Inputs


L L X X H (Note 2) H (Note 2)
PR1, PR2 Direct Preset Inputs


H H L L H
Q1, Q1, Q2, Q2 Output

H H H H L
H H X Qn Qn No Change
Note 2: This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) state.

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 74VHC74
Absolute Maximum Ratings(Note 3) Recommended Operating
Supply Voltage (VCC ) 0.5V to 7.0V Conditions (Note 4)
DC Input Voltage (VIN) 0.5V to 7.0V Supply Voltage (VCC) 2.0V to 5.5V
DC Output Voltage (VOUT) 0.5V to VCC  0.5V Input Voltage (VIN) 0V to 5.5V
Input Diode Current (IIK) 20 mA Output Voltage (VOUT) 0V to VCC
Output Diode Current (IOK) r20 mA Operating Temperature (TOPR) 40qC to 85qC
DC Output Current (IOUT) r25 mA Input Rise and Fall Time (tr, tf)
DC VCC /GND Current (ICC ) r50 mA VCC 3.3V r 0.3V 0 a 100 ns/V
Storage Temperature (TSTG) 65qC to 150qC VCC 5.0V r 0.5V 0 a 20 ns/V
Lead Temperature (TL) Note 3: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
Soldering (10 seconds) 260qC tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading varai-
bles. Fairchild does not recommend operation outside databook specifica-
tions.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter Units Conditions
(V) Min Typ Max Min Max
VIH HIGH Level Input 2.0 1.50 1.50
V
Voltage 3.0  5.5 0.7 VCC 0.7 VCC
VIL LOW Level Input 2.0 0.50 0.50
V
Voltage 3.0  5.5 0.3 VCC 0.3 VCC
VOH HIGH Level Output 2.0 1.9 2.0 1.9 VIN VIH IOH 50 PA
Voltage 3.0 2.9 3.0 2.9 V or VIL
4.5 4.4 4.5 4.4
3.0 2.58 2.48 IOH 4 mA
V
4.5 3.94 3.80 IOH 8 mA
VOL LOW Level Output 2.0 0.0 0.1 0.1 VIN VIH IOL 50 PA
Voltage 3.0 0.0 0.1 0.1 V or VIL
4.5 0.0 0.1 0.1
3.0 0.36 0.44 IOL 4 mA
V
4.5 0.36 0.44 IOL 8 mA
IIN Input Leakage Current 0  5.5 r0.1 r1.0 PA VIN 5.5V or GND
ICC Quiescent Supply Current 5.5 2.0 20.0 PA VIN VCC or GND

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74VHC74
AC Electrical Characteristics
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter Units Conditions
(V) Min Typ Max Min Max
fMAX Maximum Clock 3.3 r 0.3 80 125 70 CL 15 pF
MHz
Frequency 50 75 45 CL 50 pF
5.0 r 0.5 130 170 110 CL 15 pF
MHz
90 115 75 CL 50 pF
tPLH Propagation Delay 3.3 r 0.3 6.7 11.9 1.0 14.0 CL 15 pF
ns
tPHL Time (CK-Q, Q) 9.2 15.4 1.0 17.5 CL 50 pF
5.0 r 0.5 4.6 7.3 1.0 8.5 CL 15 pF
ns
6.1 9.3 1.0 10.5 CL 50 pF
tPLH Propagation Delay Time 3.3 r 0.3 7.6 12.3 1.0 14.5 CL 15 pF
ns
tPHL (CLR, PR -Q, Q) 10.1 15.8 1.0 18.0 CL 50 pF
5.0 r 0.5 4.8 7.7 1.0 9.0 CL 15 pF
ns
6.3 9.7 1.0 11.0 CL 50 pF
CIN Input Capacitance 4 10 10 pF VCC Open
CPD Power Dissipation 25 pF (Note 5)
Capacitance
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: ICC (opr.) CPD * VCC * fIN  I CC/2 (per F/F).

AC Operating Requirements
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter (V) Units
Typ Guaranteed Minimum
(Note 6)
tW(L) Minimum Pulse Width (CK) 3.3 6.0 7.0
ns
tW(H) 5.0 5.0 5.0

tW(L) Minimum Pulse Width (CLR, PR) 3.3 6.0 7.0

ns
5.0 5.0 5.0
tS Minimum Setup Time 3.3 6.0 7.0
ns
5.0 5.0 5.0
tH Minimum Hold Time 3.3 0.5 0.5
ns
5.0 0.5 0.5

tREC Minimum Recovery Time (CLR, PR) 3.3 5.0 5.0

ns
5.0 3.0 3.0
Note 6: VCC is 3.3 r 0.3V or 5.0 r 0.5V

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 74VHC74
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A

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74VHC74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D

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 74VHC74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14

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74VHC74 Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

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