Dac 80508

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DAC80508, DAC70508, DAC60508

SLASEL1D – JUNE 2017 – REVISED AUGUST 2018
DACx0508 Octal, 16-, 14-, 12-Bit, SPI, Voltage Output DAC with Internal Reference
1 Features 3 Description
1• Performance The DACx0508 is a pin-compatible family of low
power, eight-channel, buffered voltage-output, digital-
– INL: ±1 LSB Maximum at 16-Bit Resolution to-analog converters (DACs) with 16-, 14- and 12-bit
– TUE: ±0.1% of FSR Maximum resolution. The DACx0508 includes a 2.5-V, 5-
• Integrated 2.5 V Precision Internal Reference ppm/°C internal reference, eliminating the need for an
external precision reference in most applications. A
– Initial Accuracy: ±5 mV Maximum
user selectable gain configuration provides full-scale
– Low Drift: 2 ppm/°C Typical, DAC80508 output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1)
• High Drive Capability: 20 mA with 0.5 V from or 5 V (gain = 2). The device operates from a single
Supply Rails 2.7-V to 5.5-V supply, is specified monotonic and
provides high linearity of ±1 LSB INL.
• Flexible Output Configuration
– User Selectable Gain: 2, 1 or ½ Communication to the DACx0508 is performed
through a serial interface that operates at clock rates
– Reset to Zero Scale or Midscale up to 50 MHz. The VIO pin enables serial interface
– Clear Output Function: DACx0508C operation from 1.7 V to 5.5 V. The DACx0508 flexible
• Wide Operating Range interface enables operation with a wide range of
industry-standard microprocessors and
– Power Supply: 2.7 V to 5.5 V
microcontrollers.
– Temperature Range: –40˚C to 125˚C
The DACx0508 incorporates a power-on-reset circuit
• 50 MHz SPI Compatible Serial Interface
that powers up and maintains the DAC outputs at
– 1.7 V to 5.5 V Operation either zero scale or midscale until a valid code is
– Daisy Chain Operation written to the device. The device consumes low
current of 0.6 mA/channel at 5.5 V, making it suitable
– CRC Error Check
for battery-operated equipment. A per-channel power-
• Low Power: 0.6 mA/Channel at 5.5 V down feature reduces the device current consumption
• Small Packages: to 15 µA.
– 3 mm × 3 mm, 16-Pin WQFN The DACx0508 is characterized for operation over
– 2.4 mm x 2.4 mm, 16-Pin DSBGA the temperature range of –40°C to 125°C and is
available in small packages.
2 Applications
Device Information(1)
• Optical Networking PART NUMBER PACKAGE BODY SIZE (NOM)
• Wireless Infrastructure WQFN (16) 3.00 mm × 3.00 mm
• Industrial Automation DACx0508
DSBGA (16) 2.40 mm x 2.40 mm
• Data Acquisition Systems (1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram

VIO VDD REF
INTERNAL
REFERENCE
+1 OR +2
Serial Interface
DAC DAC DAC BUF OUT0

SCLK Buffer Register
SDI GAIN
1 x1 OR x2
SDO/ALARM or CLR Channel 0
CS Channel 1 OUT1
Channel 2 OUT2
Channel 3 OUT3
Channel 4 OUT4
Channel 5 OUT5
Channel 6 OUT6
Channel 7 OUT7
Power Down Logic
Power On Reset
DACx0508 Resistive Network
GND
1
SDO/ALARM (DACx0508), CLR (DACx0508C)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC80508, DAC70508, DAC60508
SLASEL1D – JUNE 2017 – REVISED AUGUST 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.5 Programming........................................................... 28
2 Applications ........................................................... 1 8.6 Register Map........................................................... 30
3 Description ............................................................. 1 9 Application and Implementation ........................ 36
4 Revision History..................................................... 2 9.1 Application Information............................................ 36
9.2 Typical Application ................................................. 38
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions ......................... 5 10 Power Supply Recommendations ..................... 40
7 Specifications......................................................... 6 11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
7.1 Absolute Maximum Ratings ...................................... 6
11.2 Layout Examples................................................... 41
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6 12 Device and Documentation Support ................. 43
7.4 Thermal Information .................................................. 7 12.1 Related Links ........................................................ 43
7.5 Electrical Characteristics........................................... 7 12.2 Receiving Notification of Documentation Updates 43
7.6 Typical Characteristics ............................................ 10 12.3 Community Resources.......................................... 43
12.4 Trademarks ........................................................... 43
8 Detailed Description ............................................ 20
12.5 Electrostatic Discharge Caution ............................ 43
8.1 Overview ................................................................. 20
12.6 Glossary ................................................................ 43
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 21 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes........................................ 25
Information ........................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2018) to Revision D Page
• Changed TUE in Features from ±0.14% to 0.1% .................................................................................................................. 1

• Changed Low Drift in Features from 5 ppm/°C to 2 ppm/°C and added DAC80508 ............................................................. 1
• Added Clear Output Function: DACx0508C to Features........................................................................................................ 1
• Deleted 4-Wire Mode from Features ...................................................................................................................................... 1
• Deleted 4-wire from second paragraph in Description .......................................................................................................... 1
• Deleted DAC80508 Product Preview footnote from Device Information ................................................................................ 1
• Deleted Product Preview from DAC80508Z and DAC80508M in Device Comparison Table ............................................... 4
• Added DAC80508ZC and DAC80508MC to Device Comparison Table ............................................................................... 4
• Added DAC60508ZC and DAC60508MC to Device Comparison Table ............................................................................... 4
• Added DACx0508 to SDO/ALARM pin description in Pin Functions ..................................................................................... 5
• Added CLR pin (DACx0508C) in Pin Functions ..................................................................................................................... 5
• Changed SCLK, SDI, SDO/ALARM and CS to Digital pins for Pin voltage in Absolute Maximum Ratings ......................... 6
• Added Total unadjusted error, DAC80508. All Gains row in Electrical Characteristics ........................................................ 7
• Added Offset error, DAC80508. WQFN and BGA packages. All gains. row in Electrical Characteristics ............................ 7
• Added Full-scale error, DAC80508.All gains row in Electrical Characteristics ...................................................................... 7
• Added Gain error, DAC80508 row in Electrical Characteristics ............................................................................................ 7
• Changed Short circuit current, DAC code = full scale. Output shorted to GND TYP from 35 mA to 30 mA in
Electrical Characteristics ........................................................................................................................................................ 8
• Changed Short circuit current, DAC code = zero scale. Output shorted to VDD TYP from 30 mA to 35 mA in
Electrical Characteristics ....................................................................................................................................................... 8
• Added Channel to Channel DC crosstalk, DAC80508. Measured channel at midscale. Adjacent channel at full scale
in Electrical Characteristics ................................................................................................................................................... 8
• Added Channel to Channel DC crosstalk, DAC80508. Measured channel at midscale. All other channels at full scale
in Electrical Characteristics ................................................................................................................................................... 8
• Added Reference output drift, DAC80508 in Electrical Characteristics ................................................................................ 9
• Added Reference thermal hysteresis, DAC80508. First cycle in Electrical Characteristics .................................................. 9
2 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: DAC80508 DAC70508 DAC60508

DAC80508, DAC70508, DAC60508
www.ti.com SLASEL1D – JUNE 2017 – REVISED AUGUST 2018
Revision History (continued)

• Added SDO/ALARM to DIGITAL OUTPUTS heading in Electrical Characteristics ............................................................... 9
• Deleted IDD, Power-down max value in Electrical Characteristics ......................................................................................... 9
• Changed Figure 1 to Figure 18 ............................................................................................................................................ 10
• Changed Figure 20 to Figure 28 .......................................................................................................................................... 12
• Changed Figure 34 .............................................................................................................................................................. 14
• Changed Figure 35 .............................................................................................................................................................. 14
• Changed Figure 37 .............................................................................................................................................................. 15
• Changed Figure 38 .............................................................................................................................................................. 15
• Added Figure 43 .................................................................................................................................................................. 16
• Added Figure 44 .................................................................................................................................................................. 16
• Changed Figure 58 .............................................................................................................................................................. 18
• Deleted 4-wire from paragraph in Overview section ............................................................................................................ 20
• Added paragraph to Overview section ................................................................................................................................. 20
• Changed SDO/ALARM to SDO/ALARM or CLR in Functional Block Diagram ................................................................... 20
• Added CLEAR Operation (DACx0508C only) section.......................................................................................................... 22
• Added Figure 61 .................................................................................................................................................................. 23
• Deleted four-wire from Programming section ....................................................................................................................... 28
• Added CLR pulse in Table 7 ............................................................................................................................................... 28
• Added CLR delay and note in Table 7 ................................................................................................................................ 28
• Changed table note for Table 8 ........................................................................................................................................... 30
• Added CLR-4TO7-MSK and CLR-0TO3-MSK bits for DACx0508C only to Figure 71 ....................................................... 34
• Added table note to Figure 71 ............................................................................................................................................. 34
• Added CLR-4TO7-MSK and CLR-0TO3-MSK bits for DACx0508C only to Table 13 ........................................................ 34
Changes from Revision B (January 2018) to Revision C Page
• Changed DAC80508Z, DAC70508Z, DAC60508Z, DAC80508M, DAC70508M, DAC60508M to DAC80508,

DAC70508, DAC60508 in the data sheet header and footer ................................................................................................. 1
• Changed DAC80508Z and DAC80508M to DAC80508 in Device Information table note..................................................... 1
Changes from Revision A (December 2017) to Revision B Page
• Added 2.4 mm x 2.4 mm, 16-Pin DSBGA to Features .......................................................................................................... 1

• Added DSBGA (16) package to Device Information ............................................................................................................. 1
• Added DSBGA pinout ............................................................................................................................................................. 5
• Added DSBGA package pin number column to Pin Functions table .................................................................................... 5
• Added DSBGA package pin number column to Pin Functions table .................................................................................... 6
• Added YZF column to Thermal Information .......................................................................................................................... 7
• Added Offset error test conditions and DSBGA package specific row to Electrical Characteristics ..................................... 7
• Added DSBGA Layout Example .......................................................................................................................................... 42
Changes from Original (June 2017) to Revision A Page
• Changed from Advance Information to Mixed Status............................................................................................................. 1
Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 3

DAC80508, DAC70508, DAC60508
5 Device Comparison Table
SDO OR CLR
DEVICE RESOLUTION REFERENCE RESET
OPERATION
DAC80508Z SDO
Zero
DAC80508ZC CLR
16-Bit Internal (default) / External
DAC80508M SDO
Midscale
DAC80508MC CLR
DAC70508Z Zero SDO
DAC70508M Midscale SDO
DAC60508Z SDO
Zero
DAC60508ZC CLR
DAC60508M SDO
Midscale
DAC60508MC CLR

DAC80508, DAC70508, DAC60508
6 Pin Configuration and Functions
RTE Package YZF Package

16-Pin WQFN 16-Pin DSBGA
Top View Top View
SDO/ALARM
1 2 3 4
SCLK
VIO
SDI
A OUT3 GND VDD OUT4
16
15
14
13
REF 1 12 CS B OUT1 OUT2 OUT6 OUT5
OUT0 2 11 OUT7
Thermal
OUT1 3 Pad 10 OUT6
C REF OUT0 OUT7 CS
OUT2 4 9 OUT5
5
D VIO SDO/ALARM SDI SCLK

OUT3
GND
VDD
OUT4
Not to scale
Not to scale
Pin Functions
PIN
WQFN DSBGA TYPE DESCRIPTION
NAME
NO. NO.
When using internal reference, this is the reference output voltage pin (default). When
REF 1 C1 I/O
using an external reference, this is the reference input pin to the device.
OUT0 2 C2 O Analog output voltage from DAC 0.
OUT1 3 B1 O Analog output voltage from DAC 1.
OUT3 5 A1 O Analog output voltage from DAC 3.
GND 6 A2 GND Ground reference point for all circuitry on the device.
VDD 7 A3 PWR Analog supply voltage (2.7 V to 5.5 V).
OUT4 8 A4 O Analog output voltage from DAC 4.
OUT7 11 C3 O Analog output voltage from DAC 7.
Active low serial data enable. This input is the frame synchronization signal for the serial
CS 12 C4 I
data. When the signal goes low, it enables the serial interface input shift register.
SCLK 13 D4 I Serial interface clock.
Serial interface data input. Data are clocked into the input shift register on each falling
SDI 14 D3 I
edge of the SCLK pin.
DACx0508. Serial interface data output (default). The SDO pin is in high impedance
when CS pin is high. Data are clocked out of the input shift register on either rising or
SDO/ALARM O falling edges of the SCLK pin as specified by the FSDO bit. Alternatively the pin can be
configured as an ALARM open-drain output to indicate a CRC or reference alarm event.
15 D2 If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required.
DACx0508C. A low value on the CLR pin causes the DAC outputs of those channels
configured for clear operation to update their registers and output to the reset value: zero
CLR I
scale (DACx0508Z) or midscale (DACx0508M). Bringing the CLR pin high causes the
device to exit clear mode.

DAC80508, DAC70508, DAC60508
Pin Functions (continued)

PIN
WQFN DSBGA TYPE DESCRIPTION
NAME
NO. NO.
IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial
VIO 16 D1 PWR
interface.
The thermal pad is located on the bottom-side of the WQFN package. The thermal pad
Thermal Pad – – – should be connected to any internal PCB ground plane using multiple vias for good
thermal performance.
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD to GND –0.3 6
Suppy voltage V
VIO to GND –0.3 6
DAC outputs to GND –0.3 VDD + 0.3
Pin voltage REF to GND –0.3 VDD + 0.3 V
Digital pins to GND –0.3 VIO + 0.3
Input current Input current to any pin except supply pins –10 10 mA
Operating free-air, TA -40 125
Temperature Junction, TJ –40 150 °C
Storage, Tstg –60 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per JEDEC Standard 22 Test Method A114-
±3000
C.01 (1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC Standard 22 Test Method C101,
±1000
all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
VDD Analog supply voltage 2.7 5.5
V
VIO IO supply voltage 1.7 5.5
DIGITAL INPUTS
Digital input voltage 0 VIO V
REFERENCE INPUT
Reference divider disabled 1.2 (VDD – 0.2)/2
VDD = 2.7 V to 3.3 V
Reference divider enabled 2.4 VDD – 0.2
VREFIN V
Reference divider disabled 1.2 VDD/2
VDD = 3.3 V to 5.5 V
Reference divider enabled 2.4 VDD
TEMPERATURE
TA Operating free-air temperature –40 125 °C

DAC80508, DAC70508, DAC60508
7.4 Thermal Information

DACx0508
THERMAL METRIC (1) RTE (WQFN) YZF (DSBGA) UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 33.3 68.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.5 0.3 °C/W
RθJB Junction-to-board thermal resistance 7.3 16.9 °C/W
ψJT Junction-to-top characterization parameter 0.2 0.2 °C/W
ψJB Junction-to-board characterization parameter 7.4 16.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics

All minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, TA = –40°C to 125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE (1)
DAC80508 16
Resolution DAC70508 14 Bits
DAC60508 12
DAC80508 ±0.5 ±1
INL Integral nonlinearity DAC70508 ±0.5 ±1 LSB
DAC60508 ±0.5 ±1
DAC80508. Specified 16-bit monotonic ±0.5 ±1
DNL Differential nonlinearity DAC70508. Specified 14-bit monotonic ±0.5 ±1 LSB
DAC60508. Specified 12-bit monotonic ±0.5 ±1
DAC80508. All Gains ±0.05 ±0.1
TUE Total unadjusted error DAC70508 and DAC60508. Gain = 1 and Gain = 2 ±0.06 ±0.14 %FSR
DAC70508 and DAC60508. Gain = ½ ±0.1 ±0.2
DAC80508. WQFN and BGA packages. All gains. ±0.75 ±1.5
DAC70508 and DAC60508.
WQFN package: Gain = 1, Gain = 2 and Gain = ½. ±0.75 ±1.5
Offset error mV
DSBGA package: Gain = 2
DAC70508 and DAC60508.
±0.75 ±2.5
DSBGA package: Gain = 1 and Gain = ½
Zero-code error DAC code = zero scale 0.5 1.5 mV
DAC80508. All gains ±0.05 ±0.1
Full-scale error DAC70508 and DAC60508. Gain = 1 and Gain = 2 ±0.075 ±0.14 % FSR
DAC70508 and DAC60508. Gain = ½ ±0.1 ±0.22
DAC80508 ±0.05 ±0.1
Gain error % FSR
DAC70508 and DAC60508 ±0.05 ±0.14
Offset error drift ±1 µV/°C
Zero-code error drift ±2 µV/°C
Full-scale error drift ±2 ppm of FSR/°C
Gain error drift ±1 ppm of FSR/°C
Output voltage drift over time TA = 25°C, DAC code = midscale, 1600 hours 20 ppm of FSR
(1) Static performance specified with DAC outputs unloaded for all gain options, unless otherwise noted. End point fit between codes. 16-
bit: Code 256 to 65280, 14-bit: Code 128 to 16127, 12-bit: Code 16 to 4031

DAC80508, DAC70508, DAC60508
Electrical Characteristics (continued)

OUTPUT CHARACTERISTICS
Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0) 0 2 × VREF
Voltage range Gain = 1 (BUFF-GAIN = 1, REF-DIV = 1) 0 VREF V
Gain = ½ (BUFF-GAIN = 0, REF-DIV = 1) 0 ½ × VREF
to GND or VDD (unloaded) 0.004
to GND or VDD (-5 mA ≤ IOUT ≤ 5 mA) 0.15
Output voltage headroom V
DAC code = full scale. Output shorted to GND 30
Short circuit current (2) mA
DAC code = zero scale. Output shorted to VDD 35
Load regulation DAC code = midscale, -10 mA ≤ IOUT ≤ 10 mA 85 µV/mA
RLOAD = ∞ 0 2
Maximum capacitive load (3) nF
RLOAD = 2 kΩ 0 10
DAC code = midscale 0.085
DC output impedance Ω
DAC output at GND or VDD 15
DYNAMIC PERFORMANCE
¼ to ¾ scale and ¾ to ¼ scale settling time to ±2
Output voltage settling time 5 µs
LSB, VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2
Slew rate VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2 1.8 V/µs
DACx-PWDWN 1 to 0 transition. DAC code = full
Power-up time 12 µs
scale. VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2 (4)
DAC code = zero scale. VDD = 5.5 V, VREFIN = 2.5 V,
Power-up glitch magnitude 25 mV
Gain = 2. CLOAD = 50 pF
0.1 Hz to 10 Hz, DAC code = midscale, VDD = 5.5 V,
Output noise 14 µVpp
VREFIN = 2.5 V, Gain = 2
1 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =
78
2.5 V, Gain = 2
10 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =
74
2.5 V, Gain = 2
Output noise density nV/√Hz
1 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =
55
2.5 V, Gain = 1
10 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =
50
2.5 V, Gain = 1
DAC code = midscale, frequency = 60 Hz, amplitude
AC PSRR 85 dB
= 200 mVPP superimposed on VDD
DC PSRR DAC code = midscale, VDD = 5 V ± 10% 10 µV/V
Code change glitch impulse 1 LSB change around major carrier 4 nV-s
DAC code = midscale. Code 32 to full-scale swing on
Channel to Channel AC crosstalk 0.2 nV-s
adjacent channel
DAC80508. Measured channel at midscale. Adjacent
5
channel at full scale
DAC70508 and DAC60508. Measured channel at
10
midscale. Adjacent channel at full scale
Channel to Channel DC crosstalk µV
DAC80508. Measured channel at midscale. All other
10
channels at full scale
DAC70508 and DAC60508. Measured channel at
80
midscale. All other channels at full scale
Digital feedthrough DAC code = midscale. fSCLK = 1 MHz, SDO disabled 0.1 nV-s
EXTERNAL REFERENCE INPUT
Reference input current VREFIN = 2.5 V 25 µA
Reference input impedance 100 kΩ
Reference input capacitance 5 pF
(2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified
maximum junction temperature may impair device reliability.
(3) Specified by design and characterization. Not tested during production.
(4) Time to exit DAC power-down mode. Measured from CS rising edge to 90% of DAC final value.

DAC80508, DAC70508, DAC60508
Electrical Characteristics (continued)

INTERNAL REFERENCE
Reference output voltage, VREFOUT TA = 25°C 2.495 2.5 2.505 V
DAC80508 2 5
Reference output drift ppm/°C
DAC70508 and DAC60508 5 8
Reference output impedance 0.1 Ω
Reference output noise 0.1 Hz to 10 Hz 15 µVpp
Reference output noise density 10 kHz, REFLOAD = 10 nF 130 nV/√Hz
Reference load current ±5 mA
Reference load regulation Source and sink 100 µV/mA
Reference line regulation 20 µV/V
Reference output drift over time TA = 25°C, 1600 hours 4.8 ppm
DAC80508. First cycle 50
Reference thermal hysteresis DAC70508 and DAC60508. First cycle 190 ppm
Additional cycle 18
DIGITAL INPUTS
VIH High-level input voltage 0.7 × VIO V
VIL Low-level input voltage 0.3 × VIO V
Input current ±2 µA
Input pin capacitance 2 pF
DIGITAL OUTPUTS: SDO/ALARM
VOH High-level output voltage ILOAD = 0.2 mA VIO – 0.4 V
VOL Low-level output voltage ILOAD = -0.2 mA 0.4 V
Output pin capacitance 4 pF
POWER SUPPLY REQUIREMENTS
Active mode. Internal reference enabled. Gain = 1.
5 6
DAC code = full scale. Outputs unloaded. SPI static
mA
IDD VDD supply current Active mode. Internal reference disabled. Gain = 1.
4.5 5.5
DAC code = full scale. Outputs unloaded. SPI static
Power-down 15 µA
IIO VIO supply current 2 3 µA

DAC80508, DAC70508, DAC60508
7.6 Typical Characteristics

At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted.
1 1
DAC0 DAC4
0.8 DAC1 DAC5 0.8
0.6 DAC2 DAC6 0.6
DAC3 DAC7
0.4 0.4
DNL (LSB)
0.2 0.2
INL (LSB)
0 0
-0.2 -0.2
-0.4 -0.4
DAC0 DAC4
-0.6 -0.6 DAC1 DAC5
-0.8 -0.8 DAC2 DAC6
DAC3 DAC7
-1 -1
0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536
Code D001
Code D002
Figure 1. Integral Linearity Error vs Digital Input Code Figure 2. Differential Linearity Error vs Digital Input Code
0.14 1
DAC0 DAC4 INL Max
DAC1 DAC5 0.8 INL Min
0.105
Total Unadjusted Error (%FSR)
DAC2 DAC6 0.6

INL Error Max-Min (LSB)
0.07 DAC3 DAC7

0.4
0.035 0.2
0 0
-0.035 -0.2
-0.4
-0.07
-0.6
-0.105 -0.8
-0.14 -1
0 8192 16384 24576 32768 40960 49152 57344 65536 -40 -25 -10 5 20 35 50 65 80 95 110 125
Code D003
Temperature (oC) D004
Figure 3. Total Unadjusted Error vs Digital Input Code Figure 4. Integral Linearity Error vs Temperature
1 0.14
DNL Max
0.8 DNL Min 0.105
0.6
DNL Error Max-Min (LSB)
0.07
0.4
0.2 0.035
0 0
-0.2 -0.035
-0.4
-0.07
-0.6
-0.8 -0.105
-1 -0.14
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 5. Differential Linearity Error vs Temperature Figure 6. Total Unadjusted Error vs Temperature

DAC80508, DAC70508, DAC60508
Typical Characteristics (continued)

1.5 1.5
1 1.25
Zero Code Error (mV)

Offset Error (mV)
0.5 1
0 0.75
-0.5 0.5
-1 0.25
-1.5 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 7. Offset Error vs Temperature Figure 8. Zero Code Error vs Temperature

0.14 0.14
0.105 Full Scale Error (%FSR) 0.105
0.07 0.07
Gain Error (%FSR)
0.035 0.035
0 0
-0.035 -0.035
-0.07 -0.07
-0.105 -0.105
-0.14 -0.14
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 9. Gain Error vs Temperature Figure 10. Full Scale Error vs Temperature
1 1
INL Max DNL Max
0.8 INL Min 0.8 DNL Min
0.6 0.6
INL Error Max-Min (LSB)
0.4 0.4
0.2 0.2
0 0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD (V) D011
VDD (V) D012
Gain = 1 Gain = 1
Figure 11. Integral Linearity Error vs Supply Voltage Figure 12. Differential Linearity Error vs Supply Voltage

DAC80508, DAC70508, DAC60508

0.14 1.5
0.105
1
0.07
Offset Error (mV)

0.5
0.035
0 0
-0.035
-0.5
-0.07
-1
-0.105 REF-DIV = 1 REF-DIV = 1
REF-DIV = 0 REF-DIV = 0
-0.14 -1.5
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD (V) D013
VDD (V) D014
Gain = 1 Gain = 1
Figure 13. Total Unadjusted Error vs Supply Voltage Figure 14. Offset Error vs Supply Voltage
1.5 0.14
REF-DIV = 1
REF-DIV = 0 0.105
1.25
0.07
Zero Code Error (mV)
Gain Error (%FSR)
1
0.035
0.75 0
-0.035
0.5
-0.07
0.25
-0.105 REF-DIV = 1
REF-DIV = 0
0 -0.14
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD (V) VDD (V) D016
D015
Gain = 1 Gain = 1
Figure 15. Zero Code Error vs Supply Voltage Figure 16. Gain Error vs Supply Voltage
0.14 1
REF-DIV = 1 INL Max
0.105 REF-DIV = 0 0.8 INL Min
0.6
Full Scale Error (%FSR)
0.07
0.4
INL Error Max-Min
0.035
0.2
0 0
-0.035 -0.2
-0.4
-0.07
-0.6
-0.105
-0.8
-0.14 -1
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 1.25 2 2.75 3.5 4.25 5 5.5
VDD (V) D017
VREFIN (V) D018
Gain = 1 Gain = 1
Figure 17. Full Scale Error vs Supply Voltage Figure 18. Integral Linearity Error vs Reference Voltage

DAC80508, DAC70508, DAC60508

1 0.14
DNL Max REFDIV = 0
0.8 DNL Min 0.105 REFDIV = 1

0.6
0.07
0.4
0.2 0.035
0 0
-0.2
-0.035
-0.4
-0.07
-0.6
-0.8 -0.105
-1 -0.14
1.25 2 2.75 3.5 4.25 5 5.5 1.25 2 2.75 3.5 4.25 5 5.5
VREFIN (V) D019 VREFIN (V) D020
Gain = 1 Gain = 1
Figure 19. Differential Linearity Error vs Reference Voltage Figure 20. Total Unadjusted Error vs Reference Voltage
1.5 1.5
REFDIV = 0 REFDIV = 0
1 Zero Code Error (mV) 1.25
Offset Error (mV)
0.5 1
0 0.75
-0.5 0.5
-1 0.25
-1.5 0
1.25 2 2.75 3.5 4.25 5 5.5 1.25 2 2.75 3.5 4.25 5 5.5
VREFIN (V) D021
VREFIN (V) D022
Gain = 1 Gain = 1
Figure 21. Offset Error vs Reference Voltage Figure 22. Zero Code Error vs Reference Voltage
0.14 0.14
0.105 REFDIV = 1 0.105 REFDIV = 1
Full Scale Error (%FSR)
0.07 0.07
Gain Error (%FSR)
0.035 0.035
0 0
-0.035 -0.035
-0.07 -0.07
-0.105 -0.105
-0.14 -0.14
1.25 2 2.75 3.5 4.25 5 5.5 1.25 2 2.75 3.5 4.25 5 5.5
VREFIN (V) D023
VREFIN (V) D024
Gain = 1 Gain = 1
Figure 23. Gain Error vs Reference Voltage Figure 24. Full Scale Error vs Reference Voltage

DAC80508, DAC70508, DAC60508

6 3 6.5 3.25
5.5 2.75 6 3
5 2.5 5.5 2.75
4.5 2.25 5 2.5
4 2 4.5 2.25
4 2
3.5 1.75
IDD (mA)
IDD (mA)
IIO (PA)
IIO (PA)
3.5 1.75
3 1.5
IDD, Gain = 2 1.25 3 IDD, Gain = 2 1.5
2.5
IIO, Gain = 2 2.5 IIO, Gain = 2 1.25
2 IDD, Gain = 1 1 2 IDD, Gain = 1 1
1.5 IIO, Gain = 1 0.75 IIO, Gain = 1
1.5 0.75
1 0.5 1 0.5
0.5 0.25 0.5 0.25
0 0 0 0
0 8192 16384 24576 32768 40960 49152 57344 65536 0 8192 16384 24576 32768 40960 49152 57344 65536
Code D025
Data
Code D026
Gain = 1. External Reference = 2.5 V Gain = 1
Figure 25. Supply Current with External Reference vs Figure 26. Supply Current with Internal Reference vs
Digital Input Code Digital Input Code
6 3 6.5 3.25
6 3
5 2.5 5.5 2.75
5 2.5
4 2 4.5 2.25
4 2
IDD (mA)
IDD (mA)
IIO (PA)
IIO (PA)
3.5 1.75
3 1.5
3 1.5
IDD, Gain = 2 2.5 IDD, Gain = 2 1.25
2 IIO, Gain = 2 1 IIO, Gain = 2
IDD, Gain = 1 2 IDD, Gain = 1 1
IIO, Gain = 1 1.5 IIO, Gain = 1 0.75
1 0.5 1 0.5
0.5 0.25
0 0 0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (qC) D027
Temperature Temperature
5.5 3.3 6 3
5 3 5.5 2.75
4.5 2.7 5 2.5
4 2.4 4.5 2.25

4 2
3.5 2.1
3.5 1.75
IDD (mA)
IDD (mA)
IIO (PA)
IIO (PA)
3 1.8
3 1.5
2.5 1.5
2.5 1.25
IDD IDD
2 1.2
IIO 2 IIO 1
1.5 0.9 1.5 0.75
1 0.6 1 0.5
0.5 0.3 0.5 0.25
0 0 0 0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD (V) D029
VDD (V) D030
Supply Voltage Supply Voltage

DAC80508, DAC70508, DAC60508

25 2 25 0.5
IDD
22.5 IIO 1.8 22.5 0.45
20 1.6 20 0.4
17.5 1.4 17.5 0.35
15 1.2 15 0.3
IDD (PA)
IDD (PA)
IIO (PA)
IIO (PA)
12.5 1 12.5 0.25
10 0.8 10 IDD 0.2
IIO
7.5 0.6 7.5 0.15
5 0.4 5 0.1
2.5 0.2 2.5 0.05
0 0 0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD (V) D032
Figure 31. Power Down Current vs Temperature Figure 32. Power Down Current vs Supply Voltage
1 4
Code 0x0000
0.8 Code 0x4000
3 Code 0x8000
0.6
Code 0xC000
0.4 Code 0xFFFF
2
DAC Output (V)
0.2
'VOUT (V)
0 1
-0.2
0
-0.4
Sourcing 5.5V
-0.6 Sourcing 2.7V -1
-0.8 Sinking 5.5V
Sinking 2.7V
-1 -2
0 5 10 15 20 25 30 -60 -40 -20 0 20 40 60
Load Current (mA) D033
Figure 33. Headroom/Footroom vs Load Current Figure 34. Source and Sink Capability with Gain = ½
4 7
6
3 0x3FFF
0xFFFF 5
0xC000 0x3000
2 4
DAC Output (V)
DAC Output (V)
0x8000 3 0x2000
1
0x4000 2
0x1000
0x0000
0 1
0x0000
0
-1
-1
-2 -2
-60 -40 -20 0 20 40 60 -60 -40 -20 0 20 40 60
Figure 35. Source and Sink Capability with Gain = 1 Figure 36. Source and Sink Capability with Gain = 2

DAC80508, DAC70508, DAC60508

Small Singal VOUT (3 LSB/div) Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div) Large Singal VOUT (2 V/div)
CS (5 V/div) CS (5 V/div)
Time (2 Psec/div) Time (2 Psec/div)

D037 D038
Gain = 1 Gain = 1
Figure 37. Full-Scale Settling Time, Rising Edge Figure 38. Full-Scale Settling Time, Falling Edge
VOUT (2.5 mV/div) VOUT (2.5mV/div)

CS (5 V/div) CS (5 V/div)
Time (0.5 Ps/div) Time (0.5 Ps/div)

D039 D040
Gain = 1 Gain = 1
Figure 39. Glitch Impulse, Falling Edge, 1 LSB Step Figure 40. Glitch Impulse, Rising Edge, 1 LSB Step
VDD (1.5 V/div) VDD (1.5 V/div)

VOUT (10 mV/div) VOUT (1 V/div)
Time (600 Ps/div) Time (600Ps/div)

D041 D042
Gain = 1 Gain = 1
Figure 41. Power-On, Reset to Zero Scale Figure 42. Power-On, Reset to Midscale

DAC80508, DAC70508, DAC60508

CLEAR (5 V/div) CLEAR (5 V/div)
VOUT (2.5 V/div) VOUT (2.5 V/div)
Time (0.5 Ps/div) Time (0.5 Ps/div)

D059 D060
Gain = 1 Gain = 1
Figure 43. DACx0508C, Clear to Zero Scale Figure 44. DACx0508C, Clear to Midscale
VDD (1.5 V/div) VIO (1.5 V/div)

VOUT (1 V/div) VOUT (1 V/div)
Time (600Ps/div) Time (600Ps/div)

D044 D060
Gain = 1. DAC code at midscale Gain = 1. DAC code at midscale
Figure 45. VDD Power-Down Figure 46. VIO Power-Down
SCLK (5 V/div)
VOUT (1 mV/div)
VOUT (200 PV/div)

CS (5 V/div)
Time (2 Psec/div) Time (5 Psec/div)

D045 D046
Gain = 1. Measured DAC at midscale. All other DACs switch from Gain = 1. DAC code at midscale
code 32 to full scale
Figure 47. Channel to Channel Crosstalk Figure 48. Clock Feedthrough with SCLK = 1 MHz

DAC80508, DAC70508, DAC60508

0 300
-10 Gain = 1
Gain = 2
-20 250
-30
-40 200
Noise (nV/—Hz)
AC PSRR (dB)
-50
-60 150
-70
-80 100
-90
-100 50
-110
-120 0
1 10 100 1000 10000 100000 10 2030 50 100 200 5001000 10000 100000
Frequency (Hz) D047 Frequency (Hz) D048
Gain = 1. VDD = 5 V + 200 mVPP (Sinusoid). DAC code at fullscale External Reference = 2.5 V. DAC code at midscale
Figure 49. DAC Output AC PSRR vs Frequency Figure 50. DAC Output Noise Density vs Frequency
VNOISE (2 PV/div)
VNOISE (2 PV/div)
D049 D050
Gain = 1. External Reference = 2.5 V. DAC code at midscale Gain = 1. DAC code at midscale
Figure 51. DAC Output Noise with External Reference Figure 52. DAC Output Noise with Internal Reference
0.1 Hz to 10 Hz 0.1 Hz to 10 Hz
2.505 2.505
2.5025 2.5025
Internal Reference (V)
2.5 2.5
2.4975 2.4975
2.495 2.495
-40 -25 -10 5 20 35 50 65 80 95 110 125 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD (V) D053
Figure 53. Internal Reference Voltage vs Temperature Figure 54. Internal Reference Voltage vs Supply Voltage

DAC80508, DAC70508, DAC60508

2.505 800
700
2.5025 600
Noise (nV/—Hz)
500
2.5 400
300
2.4975 200
100
2.495 0
0 200 400 600 800 1000 1200 1400 1600 10 2030 50 100 200 5001000 10000 100000
Hours D055 Frequency (Hz) D056
Figure 55. Internal Reference Voltage vs Time Figure 56. Internal Reference Noise Density vs Frequency
45
40
35
VNOISE (2 PV/div)
Number of Units
30
25
20
15
10
0
0 1 2 3 4 5
D057 Temperature Drift (ppm/qC) D058
0.1 Hz to 10 Hz
Figure 57. Internal Reference Noise Figure 58. Internal Reference Temperature Drift Histogram

DAC80508, DAC70508, DAC60508
8 Detailed Description
8.1 Overview
The DACx0508 is a pin-compatible family of low-power, eight-channel, buffered voltage-output digital-to-analog
converters (DACs) with 16-, 14- and 12-bit resolution. The DACx0508 includes a 2.5 V internal reference and
user selectable gain configuration providing full scale output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1) or 5 V
(gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is specified monotonic, and provides high
linearity of ±1 LSB INL.
Communication to the DACx0508 is performed through a serial interface that supports stand-alone and daisy-
chain operation. The optional frame-error checking provides added robustness to the DACx0508 serial interface.
The DACx0508 incorporates a power-on-reset circuit that powers up and maintains the DAC outputs at either
zero scale or midscale until a valid code is written to the device.
A dedicated clear pin (DACx0508C) enables a simultaneous update of multiple DAC channels to their power-on-
reset value.
8.2 Functional Block Diagram
VIO VDD REF

INTERNAL
REFERENCE
+1 OR +2
Serial Interface
DAC DAC DAC BUF OUT0

SCLK Buffer Register
SDI GAIN
1 x1 OR x2
SDO/ALARM or CLR Channel 0
CS Channel 1 OUT1
Channel 2 OUT2
Channel 3 OUT3
Channel 4 OUT4
Channel 5 OUT5
Channel 6 OUT6
Channel 7 OUT7
Power Down Logic
Power On Reset
DACx0508 Resistive Network
GND
1
SDO/ALARM (DACx0508), CLR (DACx0508C)

DAC80508, DAC70508, DAC60508
8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC) Architecture
Each output channel in the DACx0508 consists of an R-2R ladder architecture followed by an output buffer
amplifier. Figure 59 shows a block diagram of the DAC architecture.
REF
2.5 V
Reference
REF Divider
DIV
(÷1 or ÷2)
Serial Interface
DAC Data Register
Gain
READ WRITE GAIN
(x1 or x2)
DAC DAC
R-2R VOUT DAC output
Buffer Register Active Register
(asynchronous mode)
LDAC Trigger
(synchronous mode)
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 59. DACx0508 DAC Block Diagram
8.3.1.1 DAC Transfer Function

The input data are written to the individual DAC Data registers in straight binary format. After a power-on or a
reset event, all DAC registers are set to either zero code (DACx0508Z) or midscale code (DACx0508M). The
DAC transfer function is given by Equation 1.
CODE VREF
VOUT u u GAIN
2n DIV (1)
where:
CODE = decimal equivalent of the binary code that is loaded to the DAC register. CODE ranges from 0 to
2n – 1.
VREF = DAC reference voltage. Either VREFOUT from the internal 2.5 V reference or VREFIN if using an external
one.
n = resolution in bits. Either 12 (DAC60508), 14 (DAC70508) or 16 (DAC80508).
DIV = 1 or 2 as set by the REF-DIV bit in the GAIN register. Set to 1 by default.
GAIN = 1 or 2 as set by the BUFF-GAIN bit for that DAC channel in the GAIN register. Set to 1 by default in
DACx0508Z and to 2 in DACx0508M.

DAC80508, DAC70508, DAC60508
Feature Description (continued)

8.3.1.2 Output Amplifiers
The DACx0508 output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a
maximum output range of 0 V to VDD. Each buffer amplifier is capable of driving a load of 2 kΩ in parallel with
10 nF to GND.
The full-scale output voltage for each channel is determined by the reference voltage (VREF), the reference
divider setting (DIV), and the output buffer gain for that channel (GAIN), as shown in Table 1. During normal
operation the DIV and GAIN settings can be reconfigured through the REF-DIV and BUFF-GAIN bit (See
Equation 1). The GAIN setting for each output channel can be individually configured thus enabling independent
output voltage ranges for each DAC output.
Table 1. DAC Output Range Configuration

DIV Setting GAIN Setting DAC OUTPUT RANGE
÷2 ×1 0 V to ½ × VREF
÷1 ×1 Not recommended
÷2 ×2 0 V to VREF
÷1 ×2 0 V to 2 × VREF
8.3.1.3 DAC Register Structure

Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the
DAC buffer registers to the active DAC registers can be configured to happen immediately (asynchronous mode)
or initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC
outputs change to their new values. When the host reads from a DAC Data register, the value held in the DAC
buffer register is returned (not the value held in the DAC active register).
8.3.1.3.1 DAC Register Synchronous and Asynchronous Updates

The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In
asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register
and DAC output on CS rising edge. In synchronous mode, writing to the DAC data register does not
automatically update the DAC output. Instead the update occurs only after an LDAC trigger event. An LDAC
trigger is generated through the LDAC bit in the TRIGGER register. The synchronous update mode enables
simultaneous update of multiple DAC outputs. In both update modes a minimum wait time of 1 µs is required
between DAC output updates.
8.3.1.3.2 Broadcast DAC Register

The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a
single register write. Each DAC channel can be configured to update or remain unaffected by a broadcast
command by setting the corresponding DAC-BRDCAST-EN bit in the SYNC register. A register write to the
BRDCAST-DATA register forces those DAC channels that have been configured for broadcast operation to
update their outputs. The DAC ouputs update to the broadcast value on CS rising edge independently of their
synchronous mode configuration.
8.3.1.3.3 CLEAR Operation (DACx0508C only)

The CLR pin enables a simultaneous update of multiple DAC channels to the clear value: zero code
(DACx0508ZC) or midscale code (DACx0508MC). DAC channels 0 through 3 and channels 4 through 7 can be
independently configured to update or remain unaffected by the CLR pin by setting the corresponding CLR-MSK
bit. A CLR pin logic low forces those DAC channels that have been configured for clear operation to clear the
contents of their buffer and active registers to the clear value and sets the analog outputs accordingly, regardless
of their synchronization setting. Those channels not configured for clear operation retain their buffer and active
register contents as well as the corresponding analog outputs even if a clear command is issued. While the CLR
pin is kept low, register writes to the DAC data registers of those channels set for clear operation are ignored. A
logic high on the CLR pin causes the device to exit clear mode.

DAC80508, DAC70508, DAC60508
8.3.2 Internal Reference

The DACx0508 includes a 2.5 V precision bandgap reference enabled by default. Operation from an external
reference is supported by disabling the internal reference in the CONFIG register. The internal reference is
externally available at the REF pin.
A minimum 150 nF capacitor is recommended between the reference output and GND for noise filtering.
8.3.2.1 Reference Divider

The reference voltage to the device, either from the internal reference or an external one can be divided by a
factor of two by setting the REF-DIV bit in the GAIN register to 1 during normal operation. The reference voltage
divider provides additional flexibility in setting the full-scale output voltage for each DAC output and must be
configured so that there is sufficient headroom from VDD to the DAC operating reference voltage (VREF/DIV). See
the Recommended Operating Conditions table for more information.
Improper configuration of the reference divider issues a reference alarm condition. In this case, the reference
buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm
condition thus enabling the DAC output to return to normal operation once the reference divider is configured
correctly. The reference alarm status can be read from the REF-ALM bit in the STATUS register. Additionally by
setting ALM-EN = 1 and ALM-SEL = 1 in the CONFIG register, the SDO/ALARM pin is configured as a reference
alarm pin.
8.3.2.2 Solder Heat Reflow

A known behavior of IC reference voltage circuits is the shift induced by the soldering process. Figure 60 and
Figure 61 show the effect of solder heat reflow for the DACx0508 internal reference.
70% 70%
Presolder Heat Reflow Presolder Heat Reflow
60% Postsolder Heat Reflow 60% Postsolder Heat Reflow
50% 50%
Precentage of Units
Precentage of Units
40% 40%
30% 30%
20% 20%
10% 10%
0 0
2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010
VREFOUT (V) D059 VREFOUT (V) D061
Figure 60. DAC70508 and DAC60508 Solder Heat Figure 61. DAC80508 Solder Heat Reflow
Reflow Reference Voltage Shift Reference Voltage Shift

DAC80508, DAC70508, DAC60508
8.3.3 Device Reset Options
8.3.3.1 Power-on-Reset (POR)

The DACx0508 includes a power-on reset function that controls the output voltage at power up. After the VDD
and VIO supplies have been established a POR event is issued. The POR causes all registers to initialize to their
default values and communication with the device is valid only after a 250 µs power-on-reset delay. The default
value for all DACs in the DACx0508Z devices is zero-code and midscale-code for the DACx0508M ones. Each
DAC channel remains at the power-up voltage until a valid command is written to it.
The POR circuit requires specific supply levels to discharge the internal capacitors and to reset the device on
power up, as indicated in Figure 62 and Figure 63. In order to ensure a POR event, VDD or VIO must be below
their corresponding low thresholds for at least 100 µs. If VDD and VIO remain above their specified high threshold
a POR event will not occur. When the supplies drop below their high threshold but remain over the lower one
(shown as the undefined region), the device may or may not reset under all specified temperature and power-
supply conditions.
VDD (V) VIO (V)
5.50 5.50
Specified Supply
Voltage Range
No Power-On Reset
Specified Supply
No Power-On Reset Voltage Range
2.70
2.20
Undefined 1.70
1.50
1.20
Undefined
0.70
Power-On Reset
Power-On Reset
0.00 0.00
Figure 62. Threshold Levels for VDD POR Circuit Figure 63. Threshold Levels for VIO POR Circuit
8.3.3.2 Software Reset

A device software reset event is initiated by writing the reserved code 0x1010 to SOFT-RESET in the TRIGGER
register. The software reset command is triggered on the CS rising edge of the instruction. A software reset
initiates a POR event.

DAC80508, DAC70508, DAC60508
8.4 Device Functional Modes

8.4.1 Stand-Alone Operation
A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is
24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay
low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the
access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle
contains more than the minimum clock edges, only the last 24 or 32 bits are used by the device. When CS is
high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state.
In an error checking disabled access cycle (24-bits long) the first byte input to SDI is the instruction cycle which
identifies the request as a read or write command and the 4-bit address to be accessed. The following bits in the
cycle form the data cycle, as shown in Table 2.
Table 2. Serial Interface Access Cycle

BIT FIELD DESCRIPTION
Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a
23 RW
write operation. R/W = 1 sets a read operation.
22:20 Reserved Reserved bits. Must be filled with zeros.
19:16 A[3:0] Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with
15:0 DI[15:0]
address A[3:0]. If a read command, the data cycle bits are don’t care values.
A read operation is initiated by issuing a read command access cycle. After the read command, a second access
cycle must be issued to get the requested data, as shown in Table 3. Data are clocked out on SDO pin either on
the falling edge or rising edge of SCLK according to the FSDO bit in the CONFIG register.
Table 3. SDO Output Access Cycle

23 RW Echo RW from previous access cycle.
22:20 Reserved Echo bits 22:20 from previous access cycle (all zeros).
19:16 A[3:0] Echo address from previous access cycle.
15:0 DO[15:0] Readback data requested on previous access cycle.
8.4.2 Daisy-Chain Operation

For systems that contain more than one DACx0508 devices, the SDO pin can be used to daisy-chain them
together. Daisy-chain operation is useful in reducing the number of serial interface lines.
The first falling edge on the CS pin starts the operation cycle. If more than 24 SCLK pulses are applied while the
CS pin is kept low, the data ripples out of the shift register and is clocked out on the SDO pin either on the falling
edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output of the first device to the
SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system
requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the
total number of DACx0508 devices in the daisy chain. When the serial transfer to all devices is complete the CS
signal is taken high. This action transfers the data from the serial peripheral interface (SPI) shift registers to the
internal registers of each device in the daisy chain and prevents any further data from being clocked into the
input shift register.

DAC80508, DAC70508, DAC60508
C B A
DACx0508 DACx0508 DACx0508
SDI SDO SDI SDO SDI SDO
SCLK SCLK SCLK
CS CS CS
Figure 64. Daisy-Chain Layout
8.4.3 Frame Error Checking

If the DACx0508 is used in a noisy environment, error checking can be used to check the integrity of SPI data
communication between the device and the host processor. This feature can be enabled by setting the CRC-EN
bit in the CONFIG register.
The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111).
When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data is
appended with an 8-bit CRC polynomial by the host processor before feeding it to the device, as shown in
Table 4. In all serial interface readback operations the CRC polynomial is output on the SDO pin as part of the
32-bit cycle.
Table 4. Error Checking Serial Interface Access Cycle

Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a
31 RW
write operation. R/W = 1 sets a read operation.
30 CRC-ERROR Reserved bit. Set to zero.
29:28 Reserved Reserved bits. Must be filled with zeros.
27:24 A[3:0] Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with
23:8 DI[15:0]
address A[3:0]. If a read command, the data cycle bits are don’t care values.
7:0 CRC 8-bit CRC polynomial.
The DACx0508 decodes the 32-bit access cycle to compute the CRC remainder on CS rising edges. If no error
exists, the CRC remainder is zero and data are accepted by the device.
A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a
second access cycle can be issued to determine the error checking result (CRC-ERROR bit) on the SDO pin, as
shown in Table 5. Additionally, by setting ALM-EN = 1 and ALM-SEL = 0 in the CONFIG register, the
SDO/ALARM pin is configured as a CRC alarm pin.
Table 5. Write Operation Error Checking Cycle

31 RW Echo RW from previous access cycle (RW = 0).
30 CRC-ERROR Returns a 1 when a CRC error is detected, 0 otherwise.
23:8 DO[15:0] Echo data from previous access cycle.
7:0 CRC Calculated CRC value of bits 31:8.

DAC80508, DAC70508, DAC60508
A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The
error check result (CRC-ERROR bit) from the read command is output on the SDO pin, as shown in Table 6. As
in the case of a write operation failing the CRC check, the SDO/ALARM pin if configured as a CRC alarm pin can
be used to indicate a read command CRC failure.
Table 6. Read Operation Error Checking Cycle

31 RW Echo RW from previous access cycle (RW = 1).
30 CRC-ERROR Returns a 1 when a CRC error is detected, 0 otherwise.
23:8 DO[15:0] Readback data requested on previous access cycle.
7:0 CRC Calculated CRC value of bits 31:8.
8.4.4 Power-Down Mode

The DACx0508 DAC output amplifiers and internal reference can be independently powered down through the
CONFIG register. At power-up all output channels and the device internal referece are active by defaul. A DAC
output channel in power-down mode is connected internally to GND through a 1 kΩ resistor.

DAC80508, DAC70508, DAC60508
8.5 Programming
The DACx0508 is controlled through a flexible serial interface that is compatible with SPI type interfaces used on
many microcontrollers and DSP controllers. Table 7 shows the SPI timing requirements. Figure 65 and Figure 66
show the SPI write and read timing diagrams, respectively.
Table 7. Programming Timing Requirements (1)

VIO = 1.7 V to 2.7 V VIO = 2.7 V to 5.5 V
UNIT
MIN NOM MAX MIN NOM MAX
SERIAL INTERFACE – WRITE OPERATION
fSCLK SCLK frequency 50 50 MHz
tSCLKHIGH SCLK high time 9 9 ns
tSCLKLOW SCLK low time 9 9 ns
tSDIS SDI setup 5 5 ns
tSDIH SDI hold 10 10 ns
tCSS CS to SCLK falling edge setup 13 13 ns
tCSH SCLK falling edge to CS rising edge 10 10 ns
tCSHIGH CS high time 15 15 ns
tCSIGNORE SCLK falling edge to CS ignore 7 7 ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 0
tSDODLY SDO output delay from SCLK rising edge 3.5 33.5 3.5 23 ns
tSDODZ SDO driven to tri-state 0 30 0 25 ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 1
tSDODLY SDO output delay from SCLK falling edge 3.5 45 3.5 32 ns
tSDODZ SDO driven to tri-state 0 30 0 25 ns
DIGITAL LOGIC
tRSTDLYPOR POR reset delay 170 250 170 250 µs
tDACWAIT Sequential DAC output updates 1 1 µs
tCLR CLR pulse 20 20 ns
tCLRD CLR delay (2) 100 100 ns
(1) All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VIO), timed from a voltage level of (VIL + VIH)/2, VDD = 2.7 V to 5.5 V,
VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, SDO loaded with 20 pF, TA = -40°C to +125°C
(2) Specified from a logic-low on CLR pin to when the DAC output starts to change. In the special case when the DAC output is at GND or
VDD, the CLR delay may be as long as 1 µs

DAC80508, DAC70508, DAC60508
tCSHIGH
tCSS tCSH
CS
tCSIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
SDI Bit 23 Bit 1 Bit 0
tSDIS tSDIH
Figure 65. Serial Interface Write Timing Diagram
tCSHIGH
tCSS tCSH
CS
tCSIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
FIRST READ COMMAND ANY COMMAND
SDI Bit 23 Bit 22 Bit 0 Bit 23 Bit 1 Bit 0
tSDIS tSDIH
SDO Bit 23 Bit 1 Bit 0

FSDO = 0
tSDODLY tSDODZ
DATA FROM FIRST READ COMMAND
SDO Bit 23 Bit 1 Bit 0 X

FSDO = 1
tSDODLY tSDODZ
DATA FROM FIRST READ COMMAND
Figure 66. Serial Interface Read Timing Diagram

DAC80508, DAC70508, DAC60508
8.6 Register Map
Table 8. Register Map

ADDRESS BITS DATA BITS
REGISTER TYPE RESET
A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOP W 0000 0 0 0 0 NOP
DEVICE ID R — 0 0 0 1 DEVICEID VERSIONID
SYNC R/W FF00 0 0 1 0 DACx-BRDCAST-EN DACx-SYNC-EN
REF
ALM ALM CRC F D
CONFIG R/W 0000 0 0 1 1 RESERVED PW DACx-PWDWN
SEL EN EN SDO SDO
DWN
CLR- CLR-
4TO 0TO REF
GAIN R/W 0000 0 1 0 0 RESERVED 7 3 DIV- BUFFx-GAIN
-MSK -MSK EN
(1) (1)
L
TRIGGER W 0000 0 1 0 1 RESERVED SOFT-RESET[3:0]
DAC
BRDCAST R/W 0000 0 1 1 0 BRDCAST-DATA[15:0]
REF
STATUS R/W 0000 0 1 1 1 RESERVED
ALM
DAC0 R/W 0000 1 0 0 0 DAC0-DATA[15:0]
DAC1 R/W 0000 1 0 0 1 DAC1-DATA[15:0]
DAC2 R/W 0000 1 0 1 0 DAC2-DATA[15:0]
DAC3 R/W 0000 1 0 1 1 DAC3-DATA[15:0]
DAC4 R/W 0000 1 1 0 0 DAC4-DATA[15:0]
DAC5 R/W 0000 1 1 0 1 DAC5-DATA[15:0]
DAC6 R/W 0000 1 1 1 0 DAC6-DATA[15:0]
DAC7 R/W 0000 1 1 1 1 DAC7-DATA[15:0]
All Others — — — — — — RESERVED
(1) DACx0508C only. Reserved bits in DACx0508.

DAC80508, DAC70508, DAC60508
8.6.1 NOP Register (address = 0x00) [reset = 0x0000]
Figure 67. NOP Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOP
W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. NOP Register Field Descriptions

Bit Field Type Reset Description
15:0 NOP W 0x0000 No operation. Write 0000h for proper no-operation command
8.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]
Figure 68. DEVICE ID Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEVICEID VERSIONID
R R
Table 10. DEVICE ID Field Descriptions

15:2 DEVICEID R ---- Device ID:
D15 Reserved - 0
D14:12 Resolution - 000 (16-bit); 001 (14-bit); 010 (12-bit)
D11:8 Channels - 1000 (8 channels)
D7 Reset - 0 (DACx0508Z: reset to zero); 1 (DACx0508M: reset-
to-midscale)
D6:2 Reserved - 00101
1:0 VERSIONID R 10 Version ID. Subject to change

DAC80508, DAC70508, DAC60508
8.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]
Figure 69. SYNC Register

15 14 13 12 11 10 9 8
DAC7- DAC6- DAC5- DAC4- DAC3- DAC2- DAC1- DAC0-
BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN BRDCAST-EN
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
DAC7-SYNC- DAC6-SYNC- DAC5-SYNC- DAC4-SYNC- DAC3-SYNC- DAC2-SYNC- DAC1-SYNC- DAC0-SYNC-
EN EN EN EN EN EN EN EN
Table 11. SYNC Register Field Descriptions

15 DAC7-BRDCAST-EN R/W 1 When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
14 DAC6-BRDCAST-EN R/W 1
When cleared to 0 the corresponding DAC output remains
13 DAC5-BRDCAST-EN R/W 1 unaffected after a serial interface write to the BRDCAST
12 DAC4-BRDCAST-EN R/W 1 register.
7 DAC7-SYNC-EN R/W 0 When set to 1 the corresponding DAC output is set to update in
response to an LDAC trigger (synchronous mode).
6 DAC6-SYNC-EN R/W 0
When cleared to 0 the corresponding DAC output is set to
5 DAC5-SYNC-EN R/W 0 update immediately on a CS rising edge (asynchronous mode).

DAC80508, DAC70508, DAC60508
8.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
Figure 70. CONFIG Register

15 14 13 12 11 10 9 8
Reserved ALM-SEL ALM-EN CRC-EN FSDO DSDO REF-PWDWN
— R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
DAC7-PWDWN DAC6-PWDWN DAC5-PWDWN DAC4-PWDWN DAC3-PWDWN DAC2-PWDWN DAC1-PWDWN DAC0-PWDWN
Table 12. CONFIG Register Field Descriptions

15:14 Reserved — 00 Reserved for factory use
13 ALM-SEL R/W 0 ALARM select.
0: ALARM pin is CRC-ERROR
1: ALARM pin is REF-ALARM
12 ALM-EN R/W 0 Configure SDO/ALARM pin. When 1: SDO/ALARM pin is an
active-low, open-drain, alarm pin. An external 10 kΩ pullup
resistor to VIO is required. FSDO and DSDO bits are ignored.
When 0: SDO/ALARM pin is a serial interface, push-pull, SDO
pin
11 CRC-EN R/W 0 CRC enable bit. Set to 1 to enable CRC. Set to 0 to disable
10 FSDO R/W 0 Fast SDO bit (half-cycle speedup). When 0, SDO updates on an
SCLK rising edge. When 1, SDO updates a half-cycle earlier,
during an SCLK falling edge.
9 DSDO R/W 0 Disable SDO bit. When 1, SDO is always tri-stated. When 0,
SDO is driven while CS is low, and tri-stated while CS is high
8 REF-PWDWN R/W 0 When set to 1 disables the device internal reference
7 DAC7-PWDWN R/W 0 When set to 1 the corresponding DAC is set in power-down
mode and its output is connected to GND through a 1 kΩ
6 DAC6-PWDWN R/W 0
internal resistor.
5 DAC5-PWDWN R/W 0
4 DAC4-PWDWN R/W 0
3 DAC3-PWDWN R/W 0
2 DAC2-PWDWN R/W 0
1 DAC1-PWDWN R/W 0
0 DAC0-PWDWN R/W 0

DAC80508, DAC70508, DAC60508
8.6.5 GAIN Register (address = 0x04) [reset = 0x---]
Figure 71. GAIN Register

15 14 13 12 11 10 9 8
Reserved Reserved/ Reserved/ REFDIV-EN
CLR-4TO7- CLR-0TO3-
MSK (1) MSK (1)
— R/W R/W R/W
7 6 5 4 3 2 1 0
BUFF7-GAIN BUFF6-GAIN BUFF5-GAIN BUFF4-GAIN BUFF3-GAIN BUFF2-GAIN BUFF1-GAIN BUFF0-GAIN
(1) DACx0508C only. Reserved bits in DACx0508.

Table 13. GAIN Register Field Descriptions
15:11 Reserved — 0 Reserved for factory use.
10 Reserved / CLR-4TO7-MSK R/W 0 DACx0508. Reserved for factory use.
DACx0508C. When cleared to 0 the corresponding DAC group
9 Reserved / CLR-0TO3-MSK R/W 0
is set to clear in response to a logic-low value on the CLR pin.
When set to 1 the corresponding DAC group remains unaffected
by the CLR pin.
8 REFDIV-EN R/W 0/1 When set to 1 the reference voltage is internally divided by a
factor of 2.
When cleared to 0 the reference voltage is unaffected.
7 BUFF7-GAIN R/W 0/1 When set to 1 the buffer amplifier for corresponding DAC has a
gain of 2. Default value for the DACx0508M devices.
6 BUFF6-GAIN R/W 0/1
When cleared to 0 the buffer amplifier for corresponding DAC
5 BUFF5-GAIN R/W 0/1 has a gain of 1. Default value for the DACx0508Z devices.
8.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]
Figure 72. TRIGGER Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved LDAC SOFT-RESET[3:0]
— W W
Table 14. TRIGGER Register Field Descriptions

4 LDAC W 0 Set this bit to 1 to synchronously load those DACs that have
been set in synchronous mode in the SYNC register.
3:0 SOFT-RESET[3:0] W 0x0 When set to the reserved code 1010 resets the device to its
default state.

DAC80508, DAC70508, DAC60508
8.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]
Figure 73. BRDCAST Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRDCAST-DATA[15:0]
R/W
Table 15. BRDCAST Register Field Descriptions

15:0 BRDCAST-DATA[15:0] R/W 0x0000 Writing to the BRDCAST register forces those DAC channels
that have been set to broadcast in the SYNC register to update
their active data register with the BRDCAST-DATA value.
Data are MSB aligned in straight binary format and follows the
format below:
DAC80508: { DATA[15:0] }
DAC70508: { DATA[13:0], x, x }
DAC60508: { DATA[11:0], x, x, x, x }
x – Don’t care bits
8.6.8 STATUS Register (address = 0x7) [reset = 0x0000]
Figure 74. STATUS Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved REF-
ALM
— R/W
Table 16. STATUS Register Field Descriptions

0 REF-ALM R 0 Reference alarm bit. Reads 1 when the difference between
VREF/DIV and VDD is below the required minimum analog
threshold. Reads 0 otherwise.
8.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]
Figure 75. DACx Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACx-DATA[15:0]
R/W
Table 17. DACx Register Field Descriptions

15:0 DACx-DATA[15:0] R/W 0x0000 or Stores the 16-, 14- or 12-bit data to be loaded to DACx in MSB
0x8000 aligned straight binary format. The default value is zero-code for
the DACx0508Z devices and midscale-code for the DACx0508M
ones.
Data follows the format below:
DAC80508: { DATA[15:0] }
DAC70508: { DATA[13:0], x, x }
DAC60508: { DATA[11:0], x, x, x, x }
x – Don’t care bits

DAC80508, DAC70508, DAC60508
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The high linearity, small package size and wide temperature range make the DACx0508 suitable in applications
such as optical networking, wireless infrastructure, industrial automation and data acquisition systems. The
device incorporates a 2.5 V internal reference with an internal reference divider circuit that enables full-scale
DAC output voltages of 1.25 V, 2.5 V, or 5 V.
9.1.1 Interfacing to Microcontroller

Figure 76 displays a typical serial interface that may be observed when connecting the DACx0508 SPI serial
interface to a (master) microcontroller type platform. The setup for the interface is as follows: The microcontroller
output SPI CLK drives the SCLK pin of the DACx0508, while the DACx0508 SDI pin is driven by the MOSI pin of
the microcontroller. The CS pin of the DACx0508 can be asserted from a general program input/output pin of the
microcontroller. When data are to be transmitted to the DACx0508, the CS pin is taken low. The data from the
microcontroller is then transmitted to the DACx0508, totaling 24 bits latched into the DACx0508 device through
the falling edge of SCLK. CS is then brought high after the completed write. The DACx0508 requires data with
the MSB as the first bit received.
microcontroller DACx0508
CS CS
SCLK SCLK
MOSI SDI
MISO SDO
Figure 76. Typical Serial Interface

DAC80508, DAC70508, DAC60508
Application Information (continued)

9.1.2 Programmable Current Source Circuit
The DACx0508 can be integrated into the circuit in Figure 77 to implement an improved Howland current pump
for precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two
features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 2.
R2 R3 / R1 CODE
IL u VREF u
R3 2n (2)
The value of R3 in Equation 2 can be reduced to increase the output current drive of U3. U3 can drive ±20 mV in
both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the circuit
compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance ZO,
according to Equation 3.
R1' R3 R1 R2
ZO
R1 R2' R3' R1' R2 R3
(3)
As shown in Equation 3, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
R2'
15kQ
C1
VDD VREF
10pF
VDD VREF R1'

R3'
150kQ
VDAC 50Q
DACx0508
U3
OPA277 VOUT
GND
R3
GND
R1 R2 50Q
150kQ 15kQ
IL
LOAD
Figure 77. Programmable Bidirectional Current Source Circuit

DAC80508, DAC70508, DAC60508
9.2 Typical Application

The DACx0508 is designed for single-supply operation; however, a bipolar output is also possible using the
circuit shown in Figure 78.
GND +15V
DACx0508 V DAC
R2 OPA192 V OUT
V REF
- 15V
R1 R3
V REF
NOTE: Some pins omitted for clarity.
Figure 78. Bipolar Operation Using the DACx0508
9.2.1 Design Requirements

The circuit shown in Figure 78 gives a bipolar output voltage at VOUT. When GAIN = 1, VOUT can be calculated
using Equation 4:
ª§ CODE · § R3 R3 · § R3 · º
VOUT CODE «¨ VREF u ¸ ¨ 1 ¸ ¨ VREF u ¸»
«¬© 2n ¹ © R2 R1 ¹ © R1 ¹ »¼ (4)
Where:
• VOUT(CODE) = output voltage versus code
• CODE = 0 to 2n – 1. This is the digital code loaded to the DAC
• VREF = reference voltage applied to the DACx0508
• n = resolution in bits. Either 12 (DAC60508), 14 (DAC70508) or 16 (DAC80508)
Table 18. Design Parameters

PARAMETER VALUE
VOUT ±10 V
VREF 2.5 V
n 12
9.2.2 Detailed Design Procedure

The bipolar output span can be calculated through Equation 4 by defining a few parameters, the first being the
value for the reference voltage. Once a reference voltage is chosen, the gain resistors can be set accordingly by
determining the desired VOUT at code 0 and code 2n. For a VREF of 2.5 V and a desired output voltage range of
±10 V the calculation is as follows.
CODE = 0:
§ R3 · § R3 ·
VOUT 0 ¨ VREF u ¸ ¨ 2.5V u ¸
© R1 ¹ © R1 ¹ (5)
Setting the equation to minimum output span, VOUT(0) = –10 V, will reduce the equation to: R3/R1 = 4:
CODE = 4096:
Setting the equation to maximum output scan, VOUT(4096) = 10 V, and R3/R1 = 4 will reduce the equation to:
R3/R2 = 3

DAC80508, DAC70508, DAC60508
It is important to note that the maximum code of a 12-bit DAC is 4095; code 4096 was used to simplify the
equation above. For practical use, the true output span will encompass a range of –10 V to (10 V – 1 LSB),
which in this case is –10 V to 9.995 V.
9.2.3 Application Curve

The ±10 V output span with a reference voltage of 2.5 V can be achieved by using values of 30 kΩ, 10 kΩ, and
7.5 kΩ for R3, R2, and R1 respectively. A curve to illustrate this output span is shown in Figure 79. Note: 1%
tolerance resistors were used in evaluating bipolar operation.
10
5
Output Voltage (V)
-5
-10
0 512 1024 1536 2048 2560 3072 3584 4096
DAC Code D001
Figure 79. Bipolar Operation

DAC80508, DAC70508, DAC60508
10 Power Supply Recommendations

The DACx0508 operates within the specified VDD supply range of 2.7 V to 5.5 V and VIO supply range of 1.7 V to
5.5 V. The DACx0508 does not require specific supply sequencing.
The VDD supply must be well-regulated and low-noise. Switching power supplies and dc/dc converters often have
high frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar
high frequency spikes. This noise can easily couple into the DAC output voltage through various paths between
the power connections and analog output. In order to further minimize noise from the power supply, include a 1-
μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin, the short-circuit
current limit, and the load current for the device is listed in the Electrical Characteristics. The power supply must
meet the aforementioned current requirements.

DAC80508, DAC70508, DAC60508
11 Layout
11.1 Layout Guidelines

A precision analog component requires careful layout, the list below provides some insight into good layout
practices.
• Bypass all power supply pins to ground with a low ESR ceramic bypass capacitor. The typical recommended
bypass capacitance is 0.1- to 0.22-µF ceramic with a X7R or NP0 dielectric.
• Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize
performance.
• Use a high-quality ceramic type NP0 or X7R for its optimal performance across temperature, and very low
dissipation factor.
• The digital and analog sections must have proper placement with respect to the digital pins and analog pins
of the DACx0508 device. The separation of analog and digital blocks minimizes coupling into neighboring
blocks, as well as interaction between analog and digital return currents.
11.2 Layout Examples
ANALOG SIDE GND POUR
BYPASS CAPACITOR
4 3 2 1
BYPASS CAPACITORS 5 16
6 15
7 14
8 13
9 10 11 12
GND POUR
DIGITAL SIDE
Figure 80. DACx0508 QFN Layout Example

DAC80508, DAC70508, DAC60508
Layout Examples (continued)
REF BYPASS
CAPACITOR
VDD BYPASS
CAPACITOR
VIO BYPASS D1 C1 B1 A1
CAPACITOR
D2 C2 B2 A2
D3 C3 B3 A3
D4 C4 B4 A4
DIGITAL ANALOG
Figure 81. DACx0508 DSBGA Layout Example

DAC80508, DAC70508, DAC60508
12 Device and Documentation Support
12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 19. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
DAC80508 Click here Click here Click here Click here Click here
12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
DAC60508MCRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 658MC
DAC60508MCRTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 658MC
DAC60508MCYZFR ACTIVE DSBGA YZF 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 65MC
DAC60508MCYZFT ACTIVE DSBGA YZF 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 65MC
DAC60508MRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 658M
DAC60508MRTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 658M
DAC60508MYZFR ACTIVE DSBGA YZF 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 65M
DAC60508MYZFT ACTIVE DSBGA YZF 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 65M
DAC60508ZCRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 658ZC
DAC60508ZCRTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 658ZC
DAC60508ZCYZFR ACTIVE DSBGA YZF 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 65ZC
DAC60508ZCYZFT ACTIVE DSBGA YZF 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 65ZC
DAC60508ZRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 658Z
DAC60508ZRTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 658Z
DAC60508ZYZFR ACTIVE DSBGA YZF 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 65Z
DAC60508ZYZFT ACTIVE DSBGA YZF 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 65Z
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
DAC80508MCRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 858MC
DAC80508MCRTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 858MC
DAC80508MCYZFR ACTIVE DSBGA YZF 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 85MC
DAC80508MCYZFT ACTIVE DSBGA YZF 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 85MC
DAC80508ZCRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 858ZC
DAC80508ZCRTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 858ZC
DAC80508ZCYZFR ACTIVE DSBGA YZF 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 85ZC
DAC80508ZCYZFT ACTIVE DSBGA YZF 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 85ZC
(1)
The marketing status values are defined as follows:
Addendum-Page 2
ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC60508MCRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC60508MCRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC60508MCYZFR DSBGA YZF 16 3000 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC60508MCYZFT DSBGA YZF 16 250 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC60508MRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC60508MRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC60508MYZFR DSBGA YZF 16 3000 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC60508MYZFT DSBGA YZF 16 250 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC60508ZCRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC60508ZCRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC60508ZCYZFR DSBGA YZF 16 3000 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC60508ZCYZFT DSBGA YZF 16 250 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC60508ZRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC60508ZRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC60508ZYZFR DSBGA YZF 16 3000 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC60508ZYZFT DSBGA YZF 16 250 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC80508MCRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC80508MCRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC80508MCYZFR DSBGA YZF 16 3000 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC80508MCYZFT DSBGA YZF 16 250 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC80508ZCRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC80508ZCRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
DAC80508ZCYZFR DSBGA YZF 16 3000 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
DAC80508ZCYZFT DSBGA YZF 16 250 180.0 8.4 2.54 2.54 0.76 4.0 8.0 Q1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC60508MCRTER WQFN RTE 16 3000 367.0 367.0 38.0
DAC60508MCRTET WQFN RTE 16 250 213.0 191.0 35.0
DAC60508MCYZFR DSBGA YZF 16 3000 182.0 182.0 20.0
DAC60508MCYZFT DSBGA YZF 16 250 182.0 182.0 20.0
DAC60508MRTER WQFN RTE 16 3000 367.0 367.0 38.0
DAC60508MRTET WQFN RTE 16 250 213.0 191.0 35.0
DAC60508MYZFR DSBGA YZF 16 3000 182.0 182.0 20.0
DAC60508MYZFT DSBGA YZF 16 250 182.0 182.0 20.0
DAC60508ZCRTER WQFN RTE 16 3000 367.0 367.0 38.0
DAC60508ZCRTET WQFN RTE 16 250 213.0 191.0 35.0
DAC60508ZCYZFR DSBGA YZF 16 3000 182.0 182.0 20.0
DAC60508ZCYZFT DSBGA YZF 16 250 182.0 182.0 20.0
DAC60508ZRTER WQFN RTE 16 3000 367.0 367.0 38.0
DAC60508ZRTET WQFN RTE 16 250 213.0 191.0 35.0
DAC60508ZYZFR DSBGA YZF 16 3000 182.0 182.0 20.0
DAC60508ZYZFT DSBGA YZF 16 250 182.0 182.0 20.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC80508MCRTER WQFN RTE 16 3000 367.0 367.0 38.0
DAC80508MCRTET WQFN RTE 16 250 213.0 191.0 35.0
DAC80508MCYZFR DSBGA YZF 16 3000 182.0 182.0 20.0
DAC80508MCYZFT DSBGA YZF 16 250 182.0 182.0 20.0
DAC80508ZCRTER WQFN RTE 16 3000 367.0 367.0 38.0
DAC80508ZCRTET WQFN RTE 16 250 213.0 191.0 35.0
DAC80508ZCYZFR DSBGA YZF 16 3000 182.0 182.0 20.0
DAC80508ZCYZFT DSBGA YZF 16 250 182.0 182.0 20.0
PACKAGE OUTLINE
YZF0016 SCALE 6.500
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
C
0.625 MAX
SEATING PLANE
0.35
BALL TYP 0.05 C
0.15
1.5 TYP
0.5 TYP
C 1.5
SYMM
TYP
D: Max = 2.42 mm, Min = 2.36 mm
B
0.5 E: Max = 2.42 mm, Min = 2.36 mm
TYP
A
0.35 1 2 3 4
16X
0.25 SYMM
0.015 C A B
4222182/A 08/2015
NOTES: NanoFree Is a trademark of Texas Instruments.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZF0016 DSBGA - 0.625 mm max height
(0.5) TYP
16X ( 0.245)
1 2 3 4
(0.5) TYP
B
SYMM
SYMM
LAND PATTERN EXAMPLE

SCALE:30X
( 0.245) 0.05 MAX METAL UNDER

0.05 MIN
METAL SOLDER MASK
SOLDER MASK ( 0.245)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED
SOLDER MASK DETAILS

NOT TO SCALE
4222182/A 08/2015
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZF0016 DSBGA - 0.625 mm max height
(0.5) TYP
16X ( 0.25) (R0.05) TYP
1 2 3 4
A
(0.5)
TYP
SYMM
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4222182/A 08/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
GENERIC PACKAGE VIEW
RTE 16 WQFN - 0.8 mm max height
3 x 3, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016D SCALE 4.000
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.15
B A
2.85
PIN 1 INDEX AREA
3.15
2.85
0.8 C
0.7
SEATING PLANE
0.05
0.08 C
0.00
2X 1.5
SYMM (0.2) TYP

5 8
EXPOSED
THERMAL PAD
4
9
SYMM 17
2X 1.5 0.8 0.1
12X 0.5
1
12
PIN 1 ID
0.30
16 13 16X
0.18
0.5 0.1 C A B
16X
0.3 0.05
4219118/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016D WQFN - 0.8 mm max height
( 0.8)
SYMM
16 13 SEE SOLDER MASK
DETAIL
16X (0.6)
12
16X (0.24) 1
17 SYMM
12X (0.5) (2.8)
(R0.05) TYP
4
9
( 0.2) TYP
VIA
5 8
(2.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK
EXPOSED METAL
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL OPENING
NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4219118/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016D WQFN - 0.8 mm max height
( 0.76)
16 13
16X (0.6)
16X (0.24) 1 12
17
12X (0.5) SYMM (2.8)
4 9
(R0.05) TYP
5 8
SYMM
(2.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219118/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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DAC80508, DAC70508, DAC60508

Simplified Block Diagram

DAC DAC DAC BUF OUT0

Changes from Revision C (April 2018) to Revision D Page

• Changed TUE in Features from ±0.14% to 0.1% .................................................................................................................. 1

Product Folder Links: DAC80508 DAC70508 DAC60508

Revision History (continued)

Changes from Revision B (January 2018) to Revision C Page

• Changed DAC80508Z, DAC70508Z, DAC60508Z, DAC80508M, DAC70508M, DAC60508M to DAC80508,

Changes from Revision A (December 2017) to Revision B Page

• Added 2.4 mm x 2.4 mm, 16-Pin DSBGA to Features .......................................................................................................... 1

Changes from Original (June 2017) to Revision A Page

• Changed from Advance Information to Mixed Status............................................................................................................. 1

Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Device Comparison Table

4 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

Product Folder Links: DAC80508 DAC70508 DAC60508

6 Pin Configuration and Functions

RTE Package YZF Package

REF 1 12 CS B OUT1 OUT2 OUT6 OUT5

D VIO SDO/ALARM SDI SCLK

Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 5

Pin Functions (continued)

7.2 ESD Ratings

7.3 Recommended Operating Conditions

6 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

Product Folder Links: DAC80508 DAC70508 DAC60508

7.4 Thermal Information

7.5 Electrical Characteristics

Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 7

Electrical Characteristics (continued)

8 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

Product Folder Links: DAC80508 DAC70508 DAC60508

Electrical Characteristics (continued)

Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 9

7.6 Typical Characteristics

DAC2 DAC6 0.6

0.07 DAC3 DAC7

10 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

Product Folder Links: DAC80508 DAC70508 DAC60508

Typical Characteristics (continued)

Zero Code Error (mV)

Figure 7. Offset Error vs Temperature Figure 8. Zero Code Error vs Temperature

0.105 Full Scale Error (%FSR) 0.105

Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 11

Typical Characteristics (continued)

Offset Error (mV)

Gain Error (%FSR)

12 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

Product Folder Links: DAC80508 DAC70508 DAC60508

Typical Characteristics (continued)

Total Unadjusted Error (%FSR)

Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 13

Typical Characteristics (continued)

4 2.4 4.5 2.25

14 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

Product Folder Links: DAC80508 DAC70508 DAC60508