SN65HVD233-HT 3.3-V CAN Transceiver: 1 Features 3 Description

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SN65HVD233-HT
SLLS933G – NOVEMBER 2008 – REVISED JANUARY 2015
SN65HVD233-HT 3.3-V CAN Transceiver

1 Features 3 Description
•
1 Bus-Pin Fault Protection Exceeds ±36 V The SN65HVD233 is used in applications employing
the controller area network (CAN) serial
• Bus-Pin ESD Protection Exceeds 16-kV Human communication physical layer in accordance with the
Body Model (HBM) ISO 11898 standard, with the exception that the
• Compatible With ISO 11898 thermal shutdown is removed. As a CAN transceiver,
• Signaling Rates(1) up to 1 Mbps the device provides transmit and receive capability
between the differential CAN bus and a CAN
• Extended –7-V to 12-V Common-Mode Range
controller, with signaling rates up to 1 Mbps.
• High-Input Impedance Allows for 120 Nodes
Designed for operation in especially harsh
• LVTTL I/Os Are 5-V Tolerant environments, the device features cross wire,
• Adjustable Driver Transition Times for Improved overvoltage, and loss-of-ground protection to ±36 V,
Signal Quality with common-mode transient protection of ±100 V.
• Unpowered Node Does Not Disturb the Bus This device operates over a –7-V to 12-V common-
mode range with a maximum of 60 nodes on a bus.
• Low-Current Standby Mode: 200 µA Typical
• Power-Up and Power-Down Glitch-Free Bus If the common-mode range is restricted to the ISO
Inputs and Outputs 11898 standard range of –2 V to 7 V, up to 120
nodes may be connected on a bus. This transceiver
– High-Input Impedance With Low VCC interfaces the single-ended CAN controller with the
– Monolithic Output During Power Cycling differential CAN bus found in industrial, building
• Loopback for Diagnostic Functions Available automation, and automotive applications.
• DeviceNet™ Vendor ID #806 Device Information(1)
(1)
The signaling rate of a line is the number of voltage PART NUMBER PACKAGE BODY SIZE (NOM)
transitions that are made per second expressed in the units
bps (bits per second). SOIC (8) 4.90 mm x 3.91 mm
CFP-HKJ (8) 6.90 mm x 5.65 mm
SN65HVD233-HT
2 Applications CFP-HKQ (8) 6.90 mm x 5.65 mm
• Down-Hole Drilling CDIP SB (8) 40.64 mm x 10.04 mm
• High-Temperature Environments (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• Industrial Automation
– DeviceNet Data Buses Functional Block Diagram
– Smart Distributed Systems (SDS™) 8
RS 7
• SAE J1939 Data Bus Interfaces CANH
1
• NMEA 2000 Data Bus Interfaces D 6
CANL
• ISO 11783 Data Bus Interfaces
• CAN Data Bus Interfaces 4
R
• Controlled Baseline
5
• One Assembly or Test Site LBK
• One Fabrication Site
• Available in Extreme (–55°C to 210°C)
Temperature Range (1)
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
• Texas Instruments high-temperature products use
highly optimized silicon (die) solutions with design
and process enhancements to maximize
performance over extended temperatures.
(1) Custom temperature ranges available
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD233-HT
SLLS933G – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 9 Detailed Description ............................................ 20
2 Applications ........................................................... 1 9.1 Overview ................................................................. 20
3 Description ............................................................. 1 9.2 Functional Block Diagram ....................................... 20
4 Revision History..................................................... 2 9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 22
5 Description (Continued) ........................................ 3
6 Pin Configuration and Functions ......................... 3 10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
7 Specifications......................................................... 6
10.2 Typical Application ................................................ 24
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings ............................................................ 6 11 Power Supply Recommendations ..................... 26
7.3 Recommended Operating Conditions....................... 6 12 Layout................................................................... 26
7.4 Thermal Information .................................................. 7 12.1 Layout Guidelines ................................................. 26
7.5 Driver Electrical Characteristics ................................ 8 12.2 Layout Example .................................................... 27
7.6 Receiver Electrical Characteristics ........................... 9 13 Device and Documentation Support ................. 28
7.7 Driver Switching Characteristics ............................. 10 13.1 Trademarks ........................................................... 28
7.8 Receiver Switching Characteristics......................... 11 13.2 Electrostatic Discharge Caution ............................ 28
7.9 Device Switching Characteristics............................ 11 13.3 Glossary ................................................................ 28
7.10 Typical Characteristics .......................................... 13 14 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information ................ 15 Information ........................................................... 28
4 Revision History
Changes from Revision F (August 2012) to Revision G Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 6
2 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVD233-HT

SN65HVD233-HT
www.ti.com SLLS933G – NOVEMBER 2008 – REVISED JANUARY 2015
5 Description (Continued)
RS (pin 8) provides for three modes of operation: high-speed, slope control, or low-power standby mode. The
high-speed mode of operation is selected by connecting RS directly to ground, thus allowing the driver output
transistors to switch on and off as fast as possible with no limitation on the rise and fall slope. The rise and fall
slope can be adjusted by connecting a resistor to ground at RS, because the slope is proportional to the output
current of the pin. Slope control is implemented with a resistor value of 10 kΩ to achieve a slew rate of
≉ 15 V/μs, and a value of 100 kΩ to achieve ≉ 2 V/μs slew rate. For more information about slope control, refer
to the Application and Implementation section.
The SN65HVD233 enters a low-current standby mode, during which the driver is switched off and the receiver
remains active if a high logic level is applied to RS. The local protocol controller reverses this low-current standby
mode when it needs to transmit to the bus.
A logic high on the loopback (LBK, pin 5) of the SN65HVD233 places the bus output and bus input in a high-
impedance state. The remaining circuit remains active and available for the driver to receiver loopback, self-
diagnostic node functions without disturbing the bus.
6 Pin Configuration and Functions
D, JDJ, and HKJ Packages HKQ Package

8-Pin SOIC, CDIP SB, and CFP 8-Pin CFP
Top View Top View
D 1 8 RS 8 1
GND 2 7 CANH
RS D
VCC 3 6 CANL CANH GND
R 4 5 LBK CANL VCC
LBK R
5 4
HKQ as formed or HKJ mounted dead bug.
Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
1 D I CAN Transmit Data input (Low for dominant and HIGH for recessive bus states)
2 GND Power Ground connection
3 VCC Power VCC
4 R O CAN Receive data output
5 LBK I LoopBack (Active high to enable controller loopback mode)
6 CFANL I/O Low level CAN bus line
7 CANH I/O High level CAN bus line
8 Rs I High Speed, Slope control, and standby enable mode input.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

SN65HVD233-HT
Bare Die Information

BACKSIDE BOND PAD
DIE THICKNESS BACKSIDE FINISH
POTENTIAL METALLIZATION COMPOSITION
15 mils. Silicon with backgrind GND Al-Si-Cu (0.5%)
Origin
a c
Bond Pad Coordinates In Microns - Rev A

DESCRIPTION PAD NUMBER A B C D
D 1 86.40 157.85 203.40 274.85
GND 2 1035.05 69.75 1150.05 184.75
GND 3 1168.15 69.75 1283.15 184.75
VCC 4 1572.05 51.85 1687.05 166.85
VCC 5 1711.95 51.85 1826.95 166.85
R 6 2758.85 237.65 2873.85 352.65
LBK 7 2774.25 1429.985 2889.25 1544.95
CANL 8 1549.90 1544.95 1664.90 1659.95
CANH 9 1351.45 1544.95 1466.45 1659.95
RS 10 83.50 1429.95 198.50 1544.95

SN65HVD233-HT
1711 um
Origin
D RS
62.5 um
PAD #1
62.5 um
GND
GND CANH
2963 um
VCC
VCC CANL
HVD233
R LBK

SN65HVD233-HT
7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.3 7 V
Voltage range at any bus terminal (CANH or CANL) –36 36 V
Voltage input range, transient pulse (CANH and CANL) through 100 Ω
–100 100 V
(see Figure 19)
VI Input voltage range (D, R, RS, LBK) –0.5 7 V
IO Receiver output current –10 10 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC CANH, CANL, and GND ±16000
Electrostatic JS-001, all pins (1)
V(ESD) All pins ±3000 V
discharge
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

TA = –55°C to 210°C
MIN MAX UNIT
VCC Supply voltage 3 3.6 V
Voltage at any bus terminal (separately or common mode) –7 12 V
VIH High-level input voltage D, LBK 2 5.5 V
VIL Low-level input voltage D, LBK 0 0.8 V
VID Differential input voltage –6 6 V
Resistance from RS to ground 0 100 kΩ
VI(Rs) Input voltage at RS for standby 0.75 VCC 5.5 V
Driver –50
IOH High-level output current mA
Receiver –10
Driver 50
IOL Low-level output current mA
Receiver 10
TJ Operating junction temperature 212 °C
TA Operating free-air temperature (1) –55 210 °C
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.

SN65HVD233-HT
7.4 Thermal Information

SN65HVD233-HT
THERMAL METRIC (1) D HJK/HKQ JDJ UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 106.4 146.1 72.7
RθJC(top) Junction-to-case (top) thermal resistance 55.8 23.7 3.1
RθJB Junction-to-board thermal resistance 46.5 152.0 38.3 °C/W
ψJT Junction-to-top characterization parameter 10.7 20.7 6.0
ψJB Junction-to-board characterization parameter 45.9 93.1 26.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

SN65HVD233-HT
7.5 Driver Electrical Characteristics

TA = –55°C to 125°C TA = 175°C (1) TA = 210°C (2)
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Bus output CANH D = 0 V, RS = 0 V, 2.45 VCC 2.45 VCC 2.45 VCC
VO(D) voltage See Figure 13 and V
(dominant) CANL Figure 14 0.5 1.25 0.5 1.25 0.5 1.25
Bus output CANH D = 3 V, RS = 0 V, 2.3 2.3 2.3
VO voltage See Figure 13 and V
(recessive) CANL Figure 14 2.3 2.3 2.3
D = 0 V, RS = 0 V,
See Figure 13 and 1.5 2 3 1.4 1.75 3 1.4 1.75 3
Differential output Figure 14
VOD(D) V
voltage (Dominant) D = 0 V, RS = 0 V,
See Figure 14 and 1.1 2 3 1.1 1.47 3 1.1 1.47 3
Figure 15
D = 3 V, RS = 0 V,
See Figure 13 and –120 12 –120 12 –120 12 mV
Differential output Figure 14
VOD
voltage (Recessive)
D = 3 V, RS = 0 V, No
–0.5 0.05 –0.5 0.8 –0.5 1.2 V
load
Peak-to-peak
VOC(pp) common-mode output See Figure 21 1 1 1 V
voltage
High-level
IIH D, LBK D=2V –30 30 –30 30 –30 30 μA
input current
Low-level
IIL D, LBK D = 0.8 V –30 30 –30 30 –30 30 μA
input current
VCANH = –7 V,
CANL open, –250 –250 –250
See Figure 24
VCANH = 12 V,
CANL open, 1 1 1
Short-circuit output See Figure 24
IOS mA
current VCANL = –7 V,
CANH open, –1 –1 –1
See Figure 24
VCANL = 12 V,
CANH open, 250 250 250
See Figure 24
See receiver input
CO Output capacitance
capacitance
RS input current for
IIRs(s) RS = 0.75 VCC –10 –10 –10 μA
standby
RS = VCC, D = VCC,
Standby 200 600 400 600 400 600 μA
LBK = 0 V
Supply D = 0 V, No load,
ICC Dominant 6 6 6
current LBK = 0 V, RS = 0 V
mA
D =t VCC, No load,
Recessive 6 6 6
LBK = 0 V, RS = 0 V
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C and production tested at TA = 125°C.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.

SN65HVD233-HT
7.6 Receiver Electrical Characteristics

TA = –55°C to 125°C TA = 175°C (1) TA = 210°C (2)
Positive-going input
VIT+ 620 900 600 900 600 900 mV
threshold voltage
Negative-going
VIT– input threshold LBK = 0 V, See Table 1 500 715 500 725 500 725 mV
voltage
Hysteresis voltage
Vhys 100 140 140 mV
(VIT+ – VIT–)
High-level output
VOH IO = –4 mA, See Figure 18 2.4 2.4 2.4 V
voltage
Low-level output
VOL IO = 4 mA, See Figure 18 0.4 0.4 0.4 V
voltage
CANH or
140 500 140 500 140 500
CANL = 12 V
CANH or
CANL = 12 V, Other bus 200 600 200 700 200 800
VCC = 0 V pin = 0 V,
II Bus input current D = 3 V, μA
CANH or LBK = 0 V, –610 –150 –610 –150 –610 –150
CANL = –7 V RS = 0 V,
CANH or
CANL = –7 V, –450 –130 –450 –130 –450 –130
VCC = 0 V
Pin to ground,
Input capacitance
CI VI = 0.4 sin (4E6πt) + 0.5 V, 45 55 55 pF
(CANH or CANL)
D = 3 V, LBK = 0 V
Pin to pin,
Differential input
CID VI = 0.4 sin (4E6πt) + 0.5 V, 15 15 15 pF
capacitance
D = 3 V, LBK = 0 V
Differential input
RID 40 110 40 110 40 110 kΩ
resistance
D = 3 V, LBK = 0 V
Input resistance
RIN 20 51 19 51 18 51 kΩ
(CANH or CANL)
Standby RS = VCC, D = VCC, LBK = 0 V 200 600 400 600 400 600 μA
D = 0 V, No load, RS = 0 V,
Supply Dominant 6 6 6
ICC LBK = 0 V
current mA
D = VCC, No load, RS = 0 V,
Recessive 6 6 6
LBK = 0 V
(1) Minimum and maximum parameters are characterized for operation at TA = 210°C and are not chacterized or production tested at
TA = 175°C.

SN65HVD233-HT
7.7 Driver Switching Characteristics

TA = –55°C to 125°C TA = 175°C (1) TA = 210°C (2)
RS = 0 V, See Figure 16 35 85 50 50
Propagation delay
RS with 10 kΩ to ground,
time, 70 125 75 75
tPLH See Figure 16 ns
low-to-high-level
output RS with 100 kΩ to ground,
500 870 500 500
See Figure 16
RS = 0 V,
70 120 70 70
See Figure 16
Propagation delay
time, RS with 10 kΩ to ground,
tPHL 130 180 130 130 ns
high-to-low-level See Figure 16
output
870 1200 870 870
See Figure 16
RS = 0 V,
35 9 9
See Figure 16
Pulse skew RS with 10 kΩ to ground,
tsk(p) 60 35 35 ns
(|tPHL – tPLH|) See Figure 16
370 475 475
See Figure 16
Differential output
tr 20 70 20 75 20 75
signal rise time
RS = 0 V, See Figure 16 ns
Differential output
tf 18 70 20 75 20 75
signal fall time
Differential output
tr 30 135 30 140 30 140
signal rise time RS with 10 kΩ to ground,
ns
Differential output See Figure 16
tf 30 135 30 140 30 140
signal fall time
Differential output
tr 250 1400 250 1400 250 1400
signal rise time RS with 100 kΩ to ground,
ns
Differential output See Figure 16
tf 350 1400 350 1400 350 1400
signal fall time
Enable time from
ten(s) standby to See Figure 20 0.6 1.5 0.6 1.5 0.6 1.5 μs
dominant
(1) Minimum and maximum parameters are characterized for operation at TA = 210°C but not production tested at TA = 175°C or 210°C.

SN65HVD233-HT
7.8 Receiver Switching Characteristics

TA = –55°C to 125°C TA = 175°C (1) TA = 210°C (2)
Propagation delay time, low-to-
tPLH 35 60 50 60 50 60 ns
high-level output
Propagation delay time, high-
tPHL 35 60 45 60 45 60 ns
to-low-level output
See Figure 18
tsk(p) Pulse skew (|tPHL – tPLH|) 7 5 5 ns
tr Output signal rise time 2 6.5 6.5 8 6.5 8 ns
tf Output signal fall time 2 6.5 6.5 9 6.5 9 ns
7.9 Device Switching Characteristics

TA = –55°C to 125°C TA = 175°C (1) TA = 210°C (2)
Loopback delay,
t(LBK) driver input to See Figure 23 7.5 15 12 15 12 15 ns
receiver output
RS = 0 V, See Figure 22 70 135 90 135 90 135
Total loop delay,
driver input to RS with 10 kΩ to ground,
105 190 115 190 115 190
t(loop1) receiver output, See Figure 22 ns
recessive to
dominant 535 1000 430 1000 430 1000
See Figure 22
RS = 0 V, See Figure 22 70 135 98 135 98 135
Total loop delay,
driver input to RS with 10 kΩ to ground,
105 190 150 190 150 190
t(loop2) receiver output, See Figure 22 ns
dominant to
recessive 535 1100 880 1200 880 1200
See Figure 22

SN65HVD233-HT
1000
100
Estimated Life (Years)
Electromigration Fail Mode

10
1
110 130 150 170 190 210 230
Continuous TJ (C)
A. See the Specifications for absolute maximum and minimum recommended operating conditions.
B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 1. Operating Life Derating Chart

SN65HVD233HD, SN65HVD233SJD, SN65HVD233SKGDA, SN65HVD233SHKJ, SN65HVD233SHKQ

SN65HVD233-HT
7.10 Typical Characteristics
Figure 2. Recessive-to-Dominant Loop Time vs Free-Air Figure 3. Dominant-to-Recessive Loop Time vs Free-Air
Temperature Temperature
20 160
VCC = 3.3 V, VCC = 3.3 V,
Rs, LBK = 0 V, Rs, LBK = 0 V,
140
TA = 25°C, TA = 25°C
19
I OL - Driver Output Current - mA

60- Load
I CC - Suppl y Current - mA
120
100
18
80
17 60
40
16
20
15 0
200 300 500 700 1000 0 1 2 3 4
f - Frequenc y - kbps VOL - Lo w-Level Output Voltage - V
Figure 4. Supply Current vs Frequency Figure 5. Driver Low-Level Output Current vs Low-Level
Output Voltage
0.12
VCC = 3.3 V,
I OH - Driver High-Le vel Output Current - mA
Rs, LBK = 0 V,
0.1 TA = 25°C
0.08
0.06
0.04
0.02
0
0 0.5 1 1.5 2 2.5 3 3.5
VOH - High-Le vel Output Voltage - V
Figure 6. Driver High-Level Output Current vs High-Level Figure 7. Differential Output Voltage vs Free-Air
Output Voltage Temperature

SN65HVD233-HT
Typical Characteristics (continued)
Figure 8. Receiver Low-to-High Propagation Delay vs Free- Figure 9. Receiver High-to-Low Propagation Delay vs Free-
Air Temperature Air Temperature
Figure 10. Driver Low-to-High Propagation Delay Figure 11. Driver High-to-Low Propagation Delay
vs Free-Air Temperature vs Free-Air Temperature
35
Rs, LBK = 0 V,
30 TA = 25°C,
RL = 60 Ω
I O - Driver Output Current - mA
25
20
15
10
-5
0 0.6 1.2 1.8 2.4 3 3.6
VCC - Supply Voltage - V
Figure 12. Driver Output Current vs Supply Voltage

SN65HVD233-HT
8 Parameter Measurement Information

IO(CANH)
II D
60 Ω ±1%
VOD
VO(CANH)
VO(CANH) + VO(CANL)
RS IIRs
VI 2
+ IO(CANL) VOC
VI(Rs) VO(CANL)
-
Figure 13. Driver Voltage, Current, and Test Definition
Dominant
≈3V VO(CANH)
Recessive
≈ 2.3 V
≈1V VO(CANL)
Figure 14. Bus Logic State Voltage Definitions
CANH 330 Ω ±1%
D
VI VOD 60 Ω ±1%
+
RS _ -7 V ≤ VTEST ≤ 12 V
CANL
330 Ω ±1%
Figure 15. Driver VOD
CANH
VCC
CL = 50 pF ±20% VI
VCC/2 VCC/2
D (see Note B) 0V
VO
RL = 60 Ω ±1% tPLH tPHL
VI RS + VO(D)
0.9 V 90%
VI(Rs) VO 0.5 V
(see Note A) CANL 10% VO(R)
-
tr tf
A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 16. Driver Test Circuit and Voltage Waveforms

SN65HVD233-HT
Parameter Measurement Information (continued)

CANH
R
IO
VI(CANH + VI(CANL) VI(CANH) VID
VIC =
2
CANL VO
VI(CANL)
Figure 17. Receiver Voltage and Current Definitions
2.9 V
CANH 2.2 V 2.2 V
VI
R IO 1.5 V
VI tPLH tPHL
CL = 15 pF ±20%
(see Note A) 1.5 V VO VOH
CANL (see Note B) 90% 90%
VO 50% 50%
10% 10%
VOL
tr tf
A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 18. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT MEASURED
VCANH VCANL R |VID|
–6.1 V –7 V L 900 mV
12 V 11.1 V L 900 mV
VOL
–1 V –7 V L 6V
12 V 6V L 6V
–6.5 V –7 V H 500 mV
12 V 11.5 V H 500 mV
–7 V –1 V H VOH 6V
6V 12 V H 6V
Open Open H X
CANH
100 Ω CANL
Pulse Generator D at 0 V or V CC
15 µs Duration
1% Duty Cycle
Rs, LBK, at 0 V or V CC
tr, tf ≤ 100 ns
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 19. Test Circuit, Transient Overvoltage Test

SN65HVD233-HT
RS VCC
VI CANH
VI 50%
D 60 Ω ±1% 0V
0V
LBK VOH
CANL 50%
VO
R VOL
t en(s)
VO
+
15 pF ±20%
-
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 20. Ten(s) Test Circuit and Voltage Waveforms
CANH 27 Ω ±1%
VOC(PP)
D
VI VOC
RS CANL VOC
27 Ω ±1% 50 pF ±20%
Figure 21. VOC(pp) Test Circuit and Voltage Waveforms
0Ω, 10 kΩ,
or 100 kΩ ±5% RS DUT
CANH VCC
D VI 50% 50%
VI 60 Ω ±1%
0V
LBK
t(loop2) t(loop1)
CANL VOH
VCC VO 50% 50%
VOL
+
VO 15 pF ±20%
-
Figure 22. T(loop) Test Circuit and Voltage Waveforms

SN65HVD233-HT
RS VCC
CANH
VI 50% 50%
D +
VI VOD 60 Ω ±1% 0V
- t(LBK1) t(LBK2)
LBK VOH
VCC CANL
VO 50% 50%
R VOL
t(LBK) = t(LBK1) = t(LBK2)
VOD ≈ 2.3 V
+
VO 15 pF ±20%
-
NOTE: All VI input pulses are supplied by agenerator having the following characteristics:
Figure 23. T(LBK) Test Circuit and Voltage Waveforms
 IOS 
IOS
15 s
D CANH
0V
0 V or VCC IOS +
_ VI 12 V
CANL
VI
0V
and 10 µs
0V
VI
-7 V
Figure 24. IOS Test Circuit and Waveforms

SN65HVD233-HT
3.3 V
TA = 25°C
VCC = 3.3 V
R2 ± 1% R1 ± 1%
R CANH +
VID
CANL - Vac
R2 ± 1% R1 ± 1% VI
The R Output State Does Not Change During

Application of the Input Waveform.
VID R1 R2
500 mV 50 Ω 280 Ω
900 mV 50 Ω 130 Ω
12 V
VI
-7 V
NOTE: All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 25. Common-Mode Voltage Rejection

SN65HVD233-HT
9 Detailed Description
9.1 Overview
Controller Area Network (CAN) is a robust multi master-master, differential signaling, serial communications bus
specified by the ISO 11898 family of standards. TI's SSN65HVD23x family of transceivers solve specialized
networking requirements for various applications.
Table 2. Available Options

ORDERABLE PART SLOPE DIAGNOSTIC AUTOBAUD
LOW-POWER MODE
NUMBER CONTROL LOOPBACK LOOPBACK
SN65HVD233HD
SN65HVD233SJD
SN65HVD233SKGDA 200-μA standby mode Adjustable Yes No
SN65HVD233SHKJ
SN65HVD233SHKQ
9.2 Functional Block Diagram
RS 8
7
CANH
1
D 6
CANL
4
R
5
LBK
9.3 Feature Description
9.3.1 ISO 11898 Compliance of SN65HVD23x Family of 3.3-V CAN Transceivers

Many users value the low power consumption of operating CAN transceivers from a 3.3-V supply. However,
some are concerned about the interoperability with 5-V supplied transceivers on the same bus. This section
analyzes this situation to address those concerns.
9.3.1.1 Differential Signal

CAN is a differential bus where complementary signals are sent over two wires, and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single-ended output signal.

SN65HVD233-HT
Feature Description (continued)
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW 75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
Figure 26. Typical SN65HVD23x Differential Output Voltage Waveform
The CAN driver creates the difference voltage between CANH and CANL in the dominant state. The dominant
differential output of the SN65HVD23x is greater than 1.5 V and less than 3 V across a 60-Ω load. The minimum
required by ISO 11898 is 1.5 V and the maximum is 3 V. These are the same limiting values for 5-V supplied
CAN transceivers. The bus termination resistors drive the recessive bus state and not the CAN driver.
A CAN receiver is required to output a recessive state with less than 500 mV and a dominant state with more
than 900-mV difference voltage on its bus inputs. The CAN receiver must do this with common-mode input
voltages from –2 V to 7 V. The SN65HVD23x family receivers meet these same input specifications as 5-V
supplied receivers.
9.3.1.1.1 Common-Mode Signal

A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. Obviously, the supply
voltage of the CAN transceiver has nothing to do with noise. The SN65HVD23x family driver lowers the common-
mode output in a dominant bit by a couple hundred millivolts from that of most 5-V drivers. While this does not
fully comply with ISO 11898, this small variation in the driver common-mode output is rejected by differential
receivers and does not affect data, signal noise margins, or error rates.
9.3.1.2 Interoperability Of 3.3-V CAN in 5-V CAN Systems

The 3.3-V–supplied SN65HVD23x family of CAN transceivers are electrically interchangeable with 5-V CAN
transceivers. The differential output is the same. The recessive common-mode output is the same. The dominant
common-mode output voltage is a couple hundred millivolts lower than 5-V–supplied drivers, while the receivers
exhibit identical specifications as 5-V devices.
Electrical interoperability does not assure interchangeability however. Most implementers of CAN buses
recognize that ISO 11898 does not sufficiently specify the electrical layer and that strict standard compliance
alone does not ensure interchangeability. This comes only with thorough equipment testing.

SN65HVD233-HT
9.4 Device Functional Modes
9.4.1 Function Tables
Table 3. Function Table (Driver) (1)

DRIVER
INPUTS OUTPUTS
D LBK Rs CANH CANL BUS STATE
X X >0.75 VCC Z Z Recessive
L L or open H L Dominant
≤0.33 VCC
H or open X Z Z Recessive
X H ≤0.33 VCC Z Z Recessive
(1) H = high level, L = low level, Z = high impedance, X = irrelevant, ? = indeterminate
Table 4. Function Table (Receiver)

RECEIVER
INPUTS OUTPUT
BUS STATE VID = V(CANH) – V(CANL) LBK D R
Dominant VID ≥ 0.9 V L or open X L
Recessive VID ≤ 0.5 V or open L or open H or open H
? 0.5 V < VID < 0.9 V L or open H or open
X X L L
H
X X H H
9.4.2 Equivalent Input and Output Schematic Diagrams

V CC V CC
100 kΩ
1 kΩ
INPUT
9V
+
_
INPUT
Figure 27. D Input Figure 28. RS Input

V CC V CC
110 kΩ 9 kΩ 110 kΩ 9 kΩ
45 kΩ 45 kΩ
INPUT INPUT
40 V 9 kΩ 40 V 9 kΩ
Figure 29. CANH Input Figure 30. CANL Input

SN65HVD233-HT
V CC V CC
5Ω
OUTPUT
OUTPUT
9V
40 V
Figure 31. CANH and CANL Outputs Figure 32. R Output

V CC
1 kΩ
INPUT
9V 100 kΩ
Figure 33. LBK Input

SN65HVD233-HT
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Diagnostic Loopback

The loopback (LBK) function of the SN65HVD233 is enabled with a high-level input to pin 5. This forces the
driver into a recessive state and redirects the data (D) input at pin 1 to the received-data (R) output at pin 4. This
allows the host controller to input and read back a bit sequence to perform diagnostic routines without disturbing
the CAN bus. A typical CAN bus application is displayed in Figure 34.
If the LBK pin is not used, it may be tied to ground (GND). However, it is pulled low internally (defaults to a low-
level input) and may be left open if not in use.
10.2 Typical Application
Bus Lines -- 40 m max CANH

120 Ω Stub Lines -- 0.3 m max 120 Ω
CANL
5V 3.3 V 3.3 V
Vref Vcc Rs Vcc Vref Vcc
SN65HVD251 0.1µ F SN65HVD233 0.1µ F SN65HVD230 0.1µ F
Rs Rs
GND GND GND
D R LBK D R D R
CANTX CANRX GPIO CANTX CANRX CANTX CANRX
TMS320LF243 TMS320F2812 TMS320LF2407A
Sensor, Actuator, or Control Sensor, Actuator, or Control Sensor, Actuator, or Control

Equipment Equipment Equipment
Figure 34. Typical SN65HVD233 Application
10.2.1 Design Requirements

The High-Speed ISO 11898 Standard specifications are given for a maximum signaling rate of 1 Mbps with a bus
length of 40 m and a maximum of 30 nodes. It also recommends a maximum un-terminated stub length of 0.3 m.
The cable is specified to be a shielded or unshielded twisted-pair with a 120-W characteristic impedance (ZO).
The Standard defines a single line of twisted-pair cable with the network topology as shown in Figure 34. It is
terminated at both ends with 120-W resistors, which match the characteristic impedance of the line to prevent
signal reflections. According to ISO 11898, placing RL on a node should be avoided because the bus lines lose
termination if the node is disconnected from the bus.

SN65HVD233-HT
Typical Application (continued)

10.2.2 Detailed Design Procedure
Table 5. Suggested Cable Length vs Signaling Rate

BUS LENGTH (m) SIGNALING RATE (Mbps)
40 1
100 0.5
200 0.25
500 0.10
1000 0.05
Basically, the maximum bus length is determined by, or rather is a trade-off with the selected signaling rate as
listed in Table 5.
A signaling rate decreases as transmission distance increases. While steady-state losses may become a factor
at the longest transmission distances, the major factors limiting signaling rate as distance is increased are time
varying. Cable bandwidth limitations, which degrade the signal transition time and introduce inter-symbol
interference (ISI), are primary factors reducing the achievable signaling rate when transmission distance is
increased.
For a CAN bus, the signaling rate is also determined from the total system delay – down and back between the
two most distant nodes of a system and the sum of the delays into and out of the nodes on a bus with the typical
5ns/m prop delay of a twisted-pair cable. Also, consideration must be given the signal amplitude loss due to
resistance of the cable and the input resistance of the transceivers. Under strict analysis, skin effects, proximity
to other circuitry, dielectric loss, and radiation loss effects all act to influence the primary line parameters and
degrade the signal.
A conservative rule of thumb for bus lengths over 100 m is derived from the product of the signaling rate in Mbps
and the bus length in meters, which should be less than or equal to 50.
Signaling Rate (Mbps) × Bus Length (m) <= 50. Operation at extreme temperatures should employ additional
conservatism.
10.2.2.1 Slope Control

The rise and fall slope of the SN65HVD233 driver output can be adjusted by connecting a resistor from Rs (pin 8)
to ground (GND), or to a low-level input voltage (see Figure 35).
The slope of the driver output signal is proportional to the output current of the pin. This slope control is
implemented with an external resistor value of 10 kΩ to achieve a ≉15-V/μs slew rate, and up to 100 kΩ to
achieve a ≉2.0- V/μs slew rate (see Figure 36). Typical driver output waveforms with slope control are displayed
in Figure 37.
Figure 35. Slope Control/Standby Connection to DSP
10.2.2.2 Standby
If a high-level input (>0.75 VCC) is applied to Rs, the circuit enters a low-current, listen-only standby mode, during
which the driver is switched off and the receiver remains active. The local controller can reverse this low-power
standby mode when the rising edge of a dominant state (bus differential voltage >900 mV typical) occurs on the
bus.

SN65HVD233-HT
10.2.3 Application Curves
25
Rs = 0 Ω
20
Slope (V/us)
15
Rs = 10 k Ω
10
5
Rs = 100 k Ω
0
0 4.7 6.8 10 15 22 33 47 68 100
Slope Control Resistance - kΩ
Figure 36. SN65HVD233 Driver Output Signal Slope vs Figure 37. Typical SN65HVD233 250-kbps Output Pulse
Slope Control Resistance Value Waveforms With Slope Control
11 Power Supply Recommendations

TI recommend to have localized capacitive decoupling near device VCC pin to GND. Values of 4.7 µF at VCC
pin and 10 µF, 1µF, and 0.1 µF at supply have tested well on evaluation modules.
12 Layout
12.1 Layout Guidelines

Minimize stub length from node insertion to bus.

SN65HVD233-HT
12.2 Layout Example
Figure 38. Layout Example

SN65HVD233-HT
13 Device and Documentation Support

13.1 Trademarks
SDS is a trademark of Texas Instruments.
DeviceNet is a trademark of Open DeviceNet Vendor Association.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 26-Jan-2019
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
SN65HVD233HD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 175 233S
& no Sb/Br)
SN65HVD233SHKJ ACTIVE CFP HKJ 8 1 TBD Call TI N / A for Pkg Type -55 to 210 SN65HVD233S
HKJ
SN65HVD233SHKQ ACTIVE CFP HKQ 8 25 TBD AU N / A for Pkg Type -55 to 210 HVD233S
HKQ
SN65HVD233SJD ACTIVE CDIP SB JDJ 8 1 TBD POST-PLATE N / A for Pkg Type -55 to 210 SN65HVD233SJD
SN65HVD233SKGDA ACTIVE XCEPT KGD 0 130 Green (RoHS Call TI N / A for Pkg Type -55 to 210
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jan-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD233-HT :
• Catalog: SN65HVD233
• Automotive: SN65HVD233-Q1
• Enhanced Product: SN65HVD233-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated

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Product Sample & Technical Tools & Support & Reference

Folder Buy Documents Software Community Design

SN65HVD233-HT 3.3-V CAN Transceiver

2 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated

Product Folder Links: SN65HVD233-HT

6 Pin Configuration and Functions

D, JDJ, and HKJ Packages HKQ Package

HKQ as formed or HKJ mounted dead bug.

Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

Bare Die Information

Bond Pad Coordinates In Microns - Rev A

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7.2 ESD Ratings

7.3 Recommended Operating Conditions

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7.4 Thermal Information

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7.5 Driver Electrical Characteristics

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7.6 Receiver Electrical Characteristics

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7.7 Driver Switching Characteristics

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Product Folder Links: SN65HVD233-HT

7.8 Receiver Switching Characteristics

7.9 Device Switching Characteristics

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Electromigration Fail Mode

Figure 1. Operating Life Derating Chart

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Product Folder Links: SN65HVD233-HT

7.10 Typical Characteristics

I OL - Driver Output Current - mA

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Typical Characteristics (continued)

Figure 12. Driver Output Current vs Supply Voltage

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8 Parameter Measurement Information

Figure 13. Driver Voltage, Current, and Test Definition

Figure 14. Bus Logic State Voltage Definitions

CANH 330 Ω ±1%

Figure 15. Driver VOD

Figure 16. Driver Test Circuit and Voltage Waveforms

Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Parameter Measurement Information (continued)

Figure 17. Receiver Voltage and Current Definitions

Figure 18. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test

Figure 19. Test Circuit, Transient Overvoltage Test

16 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated

Product Folder Links: SN65HVD233-HT

Figure 20. Ten(s) Test Circuit and Voltage Waveforms

Figure 21. VOC(pp) Test Circuit and Voltage Waveforms

Figure 22. T(loop) Test Circuit and Voltage Waveforms