PCA8575

PCA8575
Remote 16-bit I/O expander for I2C-bus with interrupt

Rev. 02 — 21 March 2007 Product data sheet
1. General description
The PCA8575 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional I2C-bus (serial clock (SCL), serial data (SDA)).
The device consists of a 16-bit quasi-bidirectional port and an I2C-bus interface. The
PCA8575 has a low current consumption and includes latched outputs with high current
drive capability for directly driving LEDs.
The PCA8575 also possesses an interrupt line (INT) which can be connected to the
interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote
I/O can inform the microcontroller if there is incoming data on its ports without having to
communicate via the I2C-bus. The internal Power-On Reset (POR) initializes the I/Os as
inputs.
2. Features
n 400 kHz I2C-bus interface
n 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
n 16-bit remote I/O pins that default to inputs at power-up
n Latched outputs with 25 mA sink capability for directly driving LEDs
n Total package sink capability of 400 mA
n Active LOW open-drain interrupt output
n 8 programmable slave addresses using 3 address pins
n Readable device ID (manufacturer, device type, and revision)
n Low standby current (10 µA max.)
n −40 °C to +85 °C operation
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
n Packages offered: SO24, SSOP24 (QSOP24), TSSOP24, HVQFN24, DHVQFN24
3. Applications
n LED signs and displays
n Servers
n Industrial control
n Medical equipment
n PLCs
n Cellular telephones
NXP Semiconductors PCA8575
n Gaming machines
n Instrumentation and test measurement
4. Ordering information
Table 1. Ordering information
Type number Topside Package
mark Name Description Version
PCA8575D PCA8575D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
PCA8575DB PCA8575DB SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
PCA8575DK PCA8575 SSOP24[1] plastic shrink small outline package; 24 leads; SOT556-1
body width 3.9 mm; lead pitch 0.635 mm
PCA8575PW PCA8575PW TSSOP24 plastic thin shrink small outline package; 24 leads; SOT355-1
body width 4.4 mm
PCA8575BQ 8575 DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad SOT815-1
flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm
PCA8575BS 8575 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; SOT616-1
24 terminals; body 4 × 4 × 0.85 mm
[1] Also known as QSOP24.
5. Block diagram
PCA8575
INTERRUPT
INT LP FILTER
LOGIC
AD0
AD1
AD2
P00 to P07
SCL INPUT I2C-BUS SHIFT I/O
REGISTER 16 BITS PORT
FILTER CONTROL
SDA P10 to P17
write pulse
read pulse
POWER-ON
VDD
RESET
VSS
002aac669
Fig 1. Block diagram of PCA8575
PCA8575_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 21 March 2007 2 of 30

VDD
write pulse IOH
100 µA
Itrt(pu)
data from Shift Register D Q

FF P00 to P07
CI IOL P10 to P17
S
power-on reset VSS
D Q
FF
read pulse CI
S
to interrupt logic
data to Shift Register
002aab631
Fig 2. Simplified schematic diagram of P00 to P17
6. Pinning information
6.1 Pinning
INT 1 24 VDD INT 1 24 VDD

AD1 2 23 SDA AD1 2 23 SDA
AD2 3 22 SCL AD2 3 22 SCL
P00 4 21 AD0 P00 4 21 AD0
P01 5 20 P17 P01 5 20 P17
P02 6 19 P16 P02 6 19 P16
PCA8575D PCA8575PW
P03 7 18 P15 P03 7 18 P15
P04 8 17 P14 P04 8 17 P14
P05 9 16 P13 P05 9 16 P13
P06 10 15 P12 P06 10 15 P12
P07 11 14 P11 P07 11 14 P11
VSS 12 13 P10 VSS 12 13 P10
002aac670 002aac671
Fig 3. Pin configuration for SO24 Fig 4. Pin configuration for TSSOP24

INT 1 24 VDD INT 1 24 VDD

AD1 2 23 SDA AD1 2 23 SDA
AD2 3 22 SCL AD2 3 22 SCL
P00 4 21 AD0 P00 4 21 AD0
P01 5 20 P17 P01 5 20 P17
P02 6 19 P16 P02 6 19 P16
PCA8575DK PCA8575DB
P03 7 18 P15 P03 7 18 P15
P04 8 17 P14 P04 8 17 P14
P05 9 16 P13 P05 9 16 P13
P06 10 15 P12 P06 10 15 P12
P07 11 14 P11 P07 11 14 P11
VSS 12 13 P10 VSS 12 13 P10
002aac672 002aac673
Fig 5. Pin configuration for SSOP24 Fig 6. Pin configuration for SSOP24
(QSOP24)
24 VDD
INT
terminal 1
index area
1
AD1 2 23 SDA
20 SDA
24 AD2
23 AD1
19 SCL
21 VDD
AD2 3 22 SCL
22 INT
terminal 1
index area P00 4 21 AD0
P01 5 20 P17
P00 1 18 AD0 P02 6 19 P16
PCA8575BQ
P01 2 17 P17 P03 7 18 P15
P02 3 16 P16 P04 8 17 P14
PCA8575BS
P03 4 15 P15 P05 9 16 P13
P04 5 14 P14 P06 10 15 P12
P05 6 13 P13 P07 11 14 P11
VSS 12
P10 13
P10 10
P11 11
P12 12
7
8
9
P06
P07
VSS
002aac675
002aac674
Transparent top view Transparent top view
Fig 7. Pin configuration for HVQFN24 Fig 8. Pin configuration for DHVQFN24

6.2 Pin description

Table 2. Pin description
Symbol Pin Description
SO24, SSOP24, HVQFN24
TSSOP24, DHVQFN24
INT 1 22 interrupt output (active LOW)
AD1 2 23 address input 1
P00 4 1 quasi-bidirectional I/O 00
VSS 12[1] 9[1] supply ground
SCL 22 19 serial clock line input
SDA 23 20 serial data line input/output
VDD 24 21 supply voltage
[1] HVQFN and DHVQFN package die supply ground is connected to both the VSS pin and the exposed center
pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.

7. Functional description
Refer to Figure 1 “Block diagram of PCA8575”.
7.1 Device address

Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA8575 is shown in Figure 9. Slave address pins AD2, AD1, and AD0 choose 1 of
8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 3 “PCA8575 address map”.
Remark: The General Call address (0000 0000b) and the Device ID address
(1111 100Xb) are reserved and cannot be used as device address. Failure to follow this
requirement will cause the PCA8575 not to acknowledge.
slave address
A6 A5 A4 A3 A2 A1 A0 R/W
programmable
002aab636
Fig 9. PCA8575 address
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8575 is
applied.
7.1.1 Address map

Table 3. PCA8575 address map
A6 A5 A4 A3 A2 A1 A0 Address (hex)
0 1 0 0 0 0 0 20h
0 1 0 0 0 0 1 21h
0 1 0 0 0 1 0 22h
0 1 0 0 0 1 1 23h
0 1 0 0 1 0 0 24h
0 1 0 0 1 0 1 25h
0 1 0 0 1 1 0 26h
0 1 0 0 1 1 1 27h

8. I/O programming
8.1 Quasi-bidirectional I/O architecture

The PCA8575’s 16 ports (see Figure 2) are entirely independent and can be used either
as input or output ports. Input data is transferred from the ports to the microcontroller in
the Read mode (see Figure 12). Output data is transmitted to the ports in the Write mode
(see Figure 11).
Every data transmission from the PCA8575 must consist of an even number of bytes, the
first byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third
will be referred to as P07 to P00, and so on.
This quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data directions. At power-on the I/Os are HIGH. In this mode only a current
source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising
edges into heavily loaded outputs. These devices turn on when an output is written HIGH,
and are switched off by the negative edge of SCL. The I/Os should be HIGH before being
used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as
inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the
Write mode.
Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large
current (IOL) will flow to VSS.
8.2 Writing to the port (Output mode)

To write, the master (microcontroller) first addresses the slave device. By setting the last
bit of the byte containing the slave address to logic 0 the Write mode is entered. The
PCA8575 acknowledges and the master sends the first data byte for P07 to P00. After the
first data byte is acknowledged by the PCA8575, the second data byte P17 to P10 is sent
by the master. Once again, the PCA8575 acknowledges the receipt of the data. Each 8-bit
data is presented on the port lines after it has been acknowledged by the PCA8575.
The number of data bytes that can be sent successively is not limited. After every two
bytes, the previous data is overwritten.
The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data
byte in every pair refers to Port 1 (P17 to P10). See Figure 10.
first byte second byte
07 06 05 04 03 02 01 00 A 17 16 15 14 13 12 11 10 A
P07 P06 P05 P04 P03 P02 P01 P00 P17 P16 P15 P14 P13 P12 P11 P10
002aab634
Fig 10. Correlation between bits and ports

SCL 1 2 3 4 5 6 7 8 9
slave address data to port 0 data to port 1
SDA S A6 A5 A4 A3 A2 A1 A0 0 P P 1 P P P P P A P 1 P P P P P P A
A 07 06 04 03 02 01 00 17 15 14 13 12 11 10
START condition R/W P05 P16 acknowledge

acknowledge acknowledge from slave
from slave from slave
write to port
tv(Q) tv(Q)
data output from port data A0 and B0 valid data A0 and B0 valid
P05 output voltage
Itrt(pu)
P05 pull-up output current
IOH
P16 output voltage
Itrt(pu)
P16 pull-up output current
IOH
INT
td(rst)
002aab632
Fig 11. Write mode (output)
8.3 Reading from a port (Input mode)

All ports programmed as input should be set to logic 1. To read, the master
(microcontroller) first addresses the slave device after it receives the interrupt. By setting
the last bit of the byte containing the slave address to logic 1 the Read mode is entered.
The data bytes that follow on the SDA are the values on the ports.
If the data on the input port changes faster than the master can read, this data may be
lost.

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Product data sheet
PCA8575_2
NXP Semiconductors
SCL 1 2 3 4 5 6 7 8 9
P0x P1x P0x P1x

SDA
S 0 1 0 0 A2 A1 A0 1 A DATA 00 A DATA 11 A DATA 00 A DATA 12 1 P
START condition R/W acknowledge acknowledge acknowledge no acknowledge

from master from master from master from master
acknowledge
from slave
read from port 0
data into port 0 DATA 00
read from port 1

Rev. 02 — 21 March 2007
data into port 1 DATA 10 DATA 11 DATA 12
INT

tv(D) td(rst) 002aab810
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
Fig 12. Read input port register, scenario 1
PCA8575
© NXP B.V. 2007. All rights reserved.
9 of 30
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Product data sheet
PCA8575_2
NXP Semiconductors
SCL 1 2 3 4 5 6 7 8 9
P0x P1x P0x P1x

SDA
S 0 1 0 0 A2 A1 A0 1 A DATA 00 A DATA 10 A DATA 03 A DATA 12 1 P
START condition R/W acknowledge acknowledge acknowledge no acknowledge

from master from master from master from master
acknowledge
from slave
read from port 0
th(D) tsu(D)
data into port 0 DATA 00 DATA 01 DATA 02 DATA 03
th(D)
read from port 1
tsu(D)
Rev. 02 — 21 March 2007
data into port 1 DATA 10 DATA 11 DATA 12
INT
002aab811

tv(D) td(rst)
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
Fig 13. Read input port register, scenario 2
PCA8575
10 of 30
8.4 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA8575 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA8575 registers and I2C-bus/SMBus state machine will initialize to their default
states. Thereafter VDD must be lowered below 0.2 V to reset the device.
8.5 Interrupt output (INT)

The PCA8575 provides an open-drain interrupt (INT) which can be fed to a corresponding
input of the microcontroller (see Figure 12, Figure 13, and Figure 14). This gives these
chips a kind of master function which can initiate an action elsewhere in the system.
An interrupt is generated by any rising or falling edge of the port inputs. After time tv(D) the
signal INT is valid.
The interrupt disappears when data on the port is changed to the original setting or data is
read from or written to the device which has generated the interrupt.
In the Write mode, the interrupt may become deactivated (HIGH) on the rising edge of the
write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely
deactivated (HIGH).
The interrupt is reset in the Read mode on the rising edge of the read from port pulse.
During the resetting of the interrupt itself, any changes on the I/Os may not generate an
interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as
an INT.
VDD device 1 device 2 device 8

PCA8575 PCA8575 PCA8575
MICROCOMPUTER
INT INT INT
INT
002aac676
Fig 14. Application of multiple PCA8575s with interrupt

9. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
SDA
SCL
data line change

stable; of data
data valid allowed mba607
Fig 15. Bit transfer
9.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16.)
SDA SDA
SCL SCL
S P
START condition STOP condition

mba608
Fig 16. Definition of START and STOP conditions
9.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 17).

SDA
SCL
MASTER SLAVE MASTER

SLAVE MASTER I2C-BUS
TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/
MULTIPLEXER
RECEIVER RECEIVER RECEIVER
SLAVE
002aaa966
Fig 17. System configuration
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master

1 2 8 9
S
clock pulse for
START acknowledgement
condition 002aaa987
Fig 18. Acknowledgement on the I2C-bus

10. Application design-in information
10.1 Bidirectional I/O expander applications

In the 8-bit I/O expander application shown in Figure 19, P00 and P01 are inputs, and P02
to P07 are outputs. When used in this configuration, during a write, the input (P00 and
P01) must be written as HIGH so the external devices fully control the input ports. The
desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to
P07). During a read, the logic levels of the external devices driving the input ports (P00
and P01) and the previous written logic level to the output ports (P02 to P07) will be read.
The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of
the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the
microprocessor that there is incoming data or a change of data on its ports without having
to communicate via the I2C-bus.
VDD
VDD
VDD
SDA P00 temperature sensor

CORE SCL P01 battery status
PROCESSOR INT P02 control for latch
P03 control for switch
P04 control for audio
AD0 P05 control for camera
AD1 P06 control for MP3
AD2 P07
002aab812
Fig 19. Bidirectional I/O expander application
10.2 High current-drive load applications

The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring
additional drive, two port pins in the same octal may be connected together to sink up to
50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one
octal) can be connected together to drive 200 mA.
VDD
VDD VDD
SDA P00
CORE SCL P01
PROCESSOR INT P02
P03 LOAD
P04
AD0 P05
AD1 P06
AD2 P07
002aab813
Fig 20. High current-drive load application

10.3 Differences between the PCA8575 and the PCF8575

The PCA8575 is a drop in replacement for the PCF8575 and can used without electrical
or software modifications, but there is a difference in interrupt output release timing during
the read operation.
Write operations are identical. At the completion of each 8-bit write sequence the data is
stored in its associated 8-bit write register at ACK or NACK. The first byte goes to P0n
while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n
then P1n again. Any write will update both read registers and clear interrupts.
Read operations are identical. Both devices update the byte register with the pin data as
each 8-bit read is initiated, the very first read after an address cycle corresponds to ports
P0n while the second (even byte) corresponds to P1n and subsequent reads without a
STOP wrap around to P0n then P1n again.
During read operations, the PCA8575 interrupt output will be cleared in a byte-wise
fashion as each byte is read. Reading the first byte will clear any interrupts associated
with the P0n pins. This first byte read operation will have no effect on interrupts associated
with changes of state on the P1n pins. Interrupts associated with the P1n pins will be
cleared when the second byte is read. Reading the second byte has no effect on
interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt
output will clear after reading both bytes of data regardless of whether data was changed
in the first byte or the second byte or both bytes.
11. Limiting values

Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 +6 V
IDD supply current - ±100 mA
ISS ground supply current - ±600 mA
VI input voltage VSS − 0.5 5.5 V
II input current - ±20 mA
IO output current - ±50[1] mA
Ptot total power dissipation - 600 mW
P/out power dissipation per output - 200 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C
[1] Total package (maximum) output current is 600 mA.

12. Static characteristics

Table 5. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current Operating mode; no load; - 100 200 µA
VI = VDD or VSS; fSCL = 400 kHz
Istb standby current Standby mode; no load; - 2.5 10 µA
VI = VDD or VSS
VPOR power-on reset voltage [1] - 1.8 2.0 V
Input SCL; input/output SDA
VIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL = 0.4 V 20 - - mA
IL leakage current VI = VDD or VSS −1 - +1 µA
Ci input capacitance VI = VSS - 5 10 pF
I/Os; P00 to P07 and P10 to P17
IOL LOW-level output current[2] VOL = 0.5 V; VDD = 2.3 V 12 28 - mA
VOL = 0.5 V; VDD = 3.0 V 17 35 - mA
VOL = 0.5 V; VDD = 4.5 V 25 42 - mA
IOL(tot) total LOW-level output current[2] VOL = 0.5 V; VDD = 4.5 V - - 400 mA
IOH HIGH-level output current VOH = VSS −30 −102 −300 µA
Itrt(pu) transient boosted pull-up current VOH = VSS; see Figure 11 −0.5 −1.0 - mA
Cio(off) off-state input/output [3] - 9 10 pF
capacitance
Interrupt INT
IOL LOW-level output current VOL = 0.4 V 6 - - mA
Co output capacitance - 3 5 pF
Inputs AD0, AD1, AD2
VIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
ILI input leakage current −1 - +1 µA
Ci input capacitance - 3.5 5 pF
[1] The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD).
[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.
[3] The value is not tested, but verified on sampling basis.

13. Dynamic characteristics

Table 6. Dynamic characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions Fast mode I2C-bus Unit
Min Typ Max
fSCL SCL clock frequency 0 - 400 kHz
tBUF bus free time between a STOP and START 1.3 - - µs
condition
tHD;STA hold time (repeated) START condition 0.6 - - µs
tSU;STA set-up time for a repeated START condition 0.6 - - µs
tSU;STO set-up time for STOP condition 0.6 - - µs
tHD;DAT data hold time 0 - - ns
tVD;ACK data valid acknowledge time [1] 0.1 - 0.9 µs
tVD;DAT data valid time [2] 50 - - ns
tSU;DAT data set-up time 100 - - ns
tLOW LOW period of the SCL clock 1.3 - - µs
tHIGH HIGH period of the SCL clock 0.6 - - µs
tf fall time of both SDA and SCL signals [3][4] 20 + 0.1Cb [5] - 300 ns
tr rise time of both SDA and SCL signals 20 + 0.1Cb [5] - 300 ns
tSP pulse width of spikes that must be suppressed [6] - - 50 ns
by the input filter
Port timing; CL ≤ 100 pF (see Figure 11 and Figure 12)
tv(Q) data output valid time - - 4 µs
tsu(D) data input set-up time 0 - - µs
th(D) data input hold time 4 - - µs
Interrupt timing; CL ≤ 100 pF (see Figure 11 and Figure 12)
tv(D) data input valid time - - 4 µs
td(rst) reset delay time - - 4 µs
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[4] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[5] Cb = total capacitance of one bus line in pF.
[6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

START bit 7 STOP

bit 6 bit 0 acknowledge
protocol condition MSB condition
(A6) (R/W) (A)
(S) (A7) (P)
tSU;STA tLOW tHIGH

1/f
SCL
SCL
tBUF tf
tr
SDA
tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO
002aab175
Rise and fall times refer to VIL and VIH.

Fig 21. I2C-bus timing diagram

14. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D E A
X
y HE v M A
24 13
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 12 detail X
e w M
bp
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
2.65 0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9
mm 0.25 1.27 1.4 0.25 0.25 0.1 o
0.1 2.25 0.36 0.23 15.2 7.4 10.00 0.4 1.0 0.4 8
o
0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0
inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT137-1 075E05 MS-013
03-02-19
Fig 22. Package outline SOT137-1 (SO24)


SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
D E A
X
c
y HE v M A
24 13
Q
A2 A
(A 3)
A1
pin 1 index
θ
Lp
L
1 12 detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
o
0.21 1.80 0.38 0.20 8.4 5.4 7.9 1.03 0.9 0.8 8
mm 2 0.25 0.65 1.25 0.2 0.13 0.1 o
0.05 1.65 0.25 0.09 8.0 5.2 7.6 0.63 0.7 0.4 0
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

ISSUE DATE
99-12-27
SOT340-1 MO-150
03-02-19
Fig 23. Package outline SOT340-1 (SSOP24)


SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 mm SOT556-1
D E A
X
y HE v M A
24 13
A2 A
A1 (A 3)
θ
Lp
L
1 12 detail X
e w M
bp
0 2.5 5 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
A
UNIT A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ
max.
o
0.25 1.55 0.31 0.25 8.8 4.0 6.2 0.89 1.05 8
mm 1.73 0.25 0.635 1 0.25 0.18 0.1 o
0.10 1.40 0.20 0.18 8.6 3.8 5.8 0.41 0.66 0
0.0098 0.061 0.012 0.0098 0.344 0.157 0.244 0.035 0.040 8o
inches 0.068 0.01 0.025 0.041 0.01 0.007 0.004 o
0.0040 0.055 0.008 0.0075 0.337 0.150 0.228 0.016 0.026 0
Note
1. Plastic or metal protrusions of 0.2 mm (0.008 inch) maximum per side are not included.

ISSUE DATE
99-12-27
SOT556-1 MO-137
03-02-18
Fig 24. Package outline SOT556-1 (SSOP24)


TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
D E A
X
y HE v M A
24 13
Q
A2 (A 3) A
A1
pin 1 index
θ
Lp
L
1 12
detail X
w M
e bp
0 2.5 5 mm
scale

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
mm
0.15 0.95 0.30 0.2 7.9 4.5 6.6 0.75 0.4 0.5 8o
1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 7.7 4.3 6.2 0.50 0.3 0.2 0o
Notes
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
99-12-27
SOT355-1 MO-153
03-02-19
Fig 25. Package outline SOT355-1 (TSSOP24)


DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm SOT815-1
D B A
A
E A1
c
detail X
terminal 1
index area
C
terminal 1 e1
index area v M C A B y1 C y
e b
w M C
2 11
L
12
1
Eh e2
24
13
23 14
Dh X
0 2.5 5 mm
scale
UNIT A(1) A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1

max.
0.05 0.30 5.6 4.25 3.6 2.25 0.5
mm 1 0.2 0.5 4.5 1.5 0.1 0.05 0.05 0.1
0.00 0.18 5.4 3.95 3.4 1.95 0.3
Note

ISSUE DATE
SOT815-1 --- --- --- 03-04-29
Fig 26. Package outline SOT815-1 (DHVQFN24)


HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm SOT616-1
D B A
terminal 1
index area
A
A1
E c
detail X
e1 C
1/2 e
y1 C y
e b v M C A B
7 12 w M C
L
13
6
e
Eh e2
1/2 e
1
18
terminal 1
index area 24 19
Dh X
0 2.5 5 mm
scale
A(1)
UNIT A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1
max.
mm 0.05 0.30 4.1 2.25 4.1 2.25 0.5

1 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1
0.00 0.18 3.9 1.95 3.9 1.95 0.3
Note

ISSUE DATE
01-08-08
SOT616-1 --- MO-220 ---
02-10-22
Fig 27. Package outline SOT616-1 (HVQFN24)


15. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220
Table 8. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 28.

maximum peak temperature

temperature = MSL limit, damage level
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level

Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.
17. Abbreviations
Table 9. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
GPIO General Purpose Input/Output
HBM Human Body Model
I/O Input/Output
I2C-bus Inter-Integrated Circuit bus
IC Integrated Circuit
ID Identification
LED Light Emitting Diode
LSB Least Significant Bit
MM Machine Model
MSB Most Significant Bit
PLC Programmable Logic Controller
RAID Redundant Array of Independent Disks
SMBus System Management Bus

18. Revision history

Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA8575_2 20070321 Product data sheet - PCA8575_1
Modifications: • Table 5 “Static characteristics”, sub-section “I/Os; P00 to P07 and P10 to P17”:
– IOL (Typ) for VDD = 2.3 V changed from <tbd> to 28 mA
– IOH (Typ) changed from <tbd> to −102 µA
– Symbol Ci, input capacitance changed to Cio(off), off-state input/output capacitance;
changed Typ value from <tbd> to 9 pF
– removed Symbol Co row
PCA8575_1 20061130 Objective data sheet - -

19. Legal information
19.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
Draft — The document is a draft version only. The content is still under
such inclusion and/or use is at the customer’s own risk.
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any Applications — Applications that are described herein for any of these
representations or warranties as to the accuracy or completeness of products are for illustrative purposes only. NXP Semiconductors makes no
information included herein and shall have no liability for the consequences of representation or warranty that such applications will be suitable for the
use of such information. specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet Limiting values — Stress above one or more limiting values (as defined in
with the same product type number(s) and title. A short data sheet is intended the Absolute Maximum Ratings System of IEC 60134) may cause permanent
for quick reference only and should not be relied upon to contain detailed and damage to the device. Limiting values are stress ratings only and operation of
full information. For detailed and full information see the relevant full data the device at these or any other conditions above those given in the
sheet, which is available on request via the local NXP Semiconductors sales Characteristics sections of this document is not implied. Exposure to limiting
office. In case of any inconsistency or conflict with the short data sheet, the values for extended periods may affect device reliability.
full data sheet shall prevail. Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
19.3 Disclaimers intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
General — Information in this document is believed to be accurate and any inconsistency or conflict between information in this document and such
reliable. However, NXP Semiconductors does not give any representations or terms and conditions, the latter will prevail.
warranties, expressed or implied, as to the accuracy or completeness of such
No offer to sell or license — Nothing in this document may be interpreted
information and shall have no liability for the consequences of use of such
or construed as an offer to sell products that is open for acceptance or the
information.
grant, conveyance or implication of any license under any copyrights, patents
Right to make changes — NXP Semiconductors reserves the right to make or other industrial or intellectual property rights.
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior 19.4 Trademarks
to the publication hereof.
Notice: All referenced brands, product names, service names and trademarks
Suitability for use — NXP Semiconductors products are not designed,
are the property of their respective owners.
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or I2C-bus — logo is a trademark of NXP B.V.
malfunction of a NXP Semiconductors product can reasonably be expected to
20. Contact information

For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com

21. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 20 Contact information . . . . . . . . . . . . . . . . . . . . 29
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.1 Address map. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7
8.1 Quasi-bidirectional I/O architecture . . . . . . . . . 7
8.2 Writing to the port (Output mode) . . . . . . . . . . . 7
8.3 Reading from a port (Input mode) . . . . . . . . . . 8
8.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11
8.5 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 11
9 Characteristics of the I2C-bus. . . . . . . . . . . . . 12
9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9.1.1 START and STOP conditions . . . . . . . . . . . . . 12
9.2 System configuration . . . . . . . . . . . . . . . . . . . 12
9.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13
10 Application design-in information . . . . . . . . . 14
10.1 Bidirectional I/O expander applications . . . . . 14
10.2 High current-drive load applications . . . . . . . . 14
10.3 Differences between the PCA8575 and the
PCF8575. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
12 Static characteristics. . . . . . . . . . . . . . . . . . . . 16
13 Dynamic characteristics . . . . . . . . . . . . . . . . . 17
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
15 Handling information. . . . . . . . . . . . . . . . . . . . 25
16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
16.1 Introduction to soldering . . . . . . . . . . . . . . . . . 25
16.2 Wave and reflow soldering . . . . . . . . . . . . . . . 25
16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25
16.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26
17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27
18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28
19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 29
19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29
19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 March 2007
Document identifier: PCA8575_2

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PCA8575

Remote 16-bit I/O expander for I2C-bus with interrupt

[1] Also known as QSOP24.

Fig 1. Block diagram of PCA8575

PCA8575_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 21 March 2007 2 of 30

data from Shift Register D Q

Fig 2. Simplified schematic diagram of P00 to P17

INT 1 24 VDD INT 1 24 VDD

PCA8575_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 21 March 2007 3 of 30

INT 1 24 VDD INT 1 24 VDD

Transparent top view Transparent top view

PCA8575_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 21 March 2007 4 of 30

6.2 Pin description

PCA8575_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 21 March 2007 5 of 30

7.1 Device address

Fig 9. PCA8575 address

7.1.1 Address map

PCA8575_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 21 March 2007 6 of 30

8.1 Quasi-bidirectional I/O architecture

8.2 Writing to the port (Output mode)

first byte second byte

Fig 10. Correlation between bits and ports

PCA8575_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 21 March 2007 7 of 30

slave address data to port 0 data to port 1

START condition R/W P05 P16 acknowledge

P05 output voltage

P16 output voltage

Fig 11. Write mode (output)

8.3 Reading from a port (Input mode)

PCA8575_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 21 March 2007 8 of 30

P0x P1x P0x P1x

START condition R/W acknowledge acknowledge acknowledge no acknowledge

read from port 0

data into port 0 DATA 00

read from port 1

data into port 1 DATA 10 DATA 11 DATA 12

Remote 16-bit I/O expander for I2C-bus with interrupt

P0x P1x P0x P1x

START condition R/W acknowledge acknowledge acknowledge no acknowledge

read from port 0

data into port 0 DATA 00 DATA 01 DATA 02 DATA 03

data into port 1 DATA 10 DATA 11 DATA 12

Remote 16-bit I/O expander for I2C-bus with interrupt

8.4 Power-on reset

8.5 Interrupt output (INT)

VDD device 1 device 2 device 8

Fig 14. Application of multiple PCA8575s with interrupt

PCA8575_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 21 March 2007 11 of 30

9. Characteristics of the I2C-bus

9.1 Bit transfer

data line change

Fig 15. Bit transfer