A6261

Protected LED Array Driver

FEATURES AND BENEFITS DESCRIPTION

• AEC-Q100 qualified The A6261 is a linear, programmable current regulator providing
• Total LED drive current up to 400 mA (LP, LJ, and LY up to 100 mA from each of four outputs (LP and LY) to drive
packages) or 300 mA (LJ) arrays of high brightness LEDs. The regulated LED current
• Current shared equally up to 100 mA by up to 4 strings from each output, accurate to 5%, is set by a single reference
(LP and LY) resistor. Current matching in each string is better than 10%
• 6 to 50 V supply without the use of ballast resistors. Driving LEDs with constant
• Low dropout voltage current ensures safe operation with maximum possible light
• LED output short-to-ground and thermal protection output. The A6261 in the LJ package offers two pins with
• Disable on open LED detection option 200 mA each channel (A6261LJ-1) and with 100 mA and
• Enable input for PWM control 200 mA maximum output current (A6261LJ).
• Current slew rate limit during PWM
Output control is provided by an enable input, giving direct
• Current set by reference resistor
control for PWM applications. Outputs can be connected in
• Automotive temperature range (K, –40°C to 150°C)
parallel or left unused as required.
PACKAGES Short detection is provided to protect the LEDs and the A6261
8-pin SOICN with
during a short-to-ground at any LED output pin. An open LED
exposed thermal in any of the strings disables all outputs, but can be overridden.
pad (suffix LJ) Shorted LED output pins or open LEDs are indicated by a
fault flag.
10-pin MSOP with A temperature monitor is included to reduce the LED drive
exposed thermal current if the chip temperature exceeds a thermal threshold.
pad (suffix LY)
The device packages are an 8-pin SOICN (suffix LJ), a 10-pin
MSOP (LY), and a 16-pin TSSOP (LP), all with exposed pad
for enhanced thermal dissipation. They are lead (Pb) free, with
16-pin TSSOP with 100% matte-tin leadframe plating.
exposed thermal
pad (suffix LP)

Not to scale

+ +
Power input Power input
VIN VIN

A6261 A6261
(LJ Package) (LP, LY Packages)
PWM dimming input LA1 PWM dimming input LA1
EN EN
FF LA2 FF LA2
IREF IREF LA3
THTH THTH LA4

GND GND

– –

Typical Application Diagrams

A6261A-DS, Rev. 14 January 21, 2018

MCO-0000361
A6261 Protected LED Array Driver

SELECTION GUIDE
Ambient Operating
Part Number Packing Current Package
Temperature, TA (°C)
LA1 = 200 mA
A6261KLJTR-T –40 to 125 3000 pieces per 13-in. reel 8-pin SOIC with exposed thermal pad
LA2 = 100 mA

A6261KLJTR-T-1 –40 to 125 3000 pieces per 13-in. reel LA1 = LA2 = 200 mA 8-pin SOIC with exposed thermal pad

A6261ELPTR-T –40 to 85 4000 pieces per 13-in. reel

16-pin TSSOP with exposed thermal pad
A6261KLPTR-T –40 to 125 4000 pieces per 13-in. reel LA1-LA4 = 100 mA

A6261KLYTR-T –40 to 125 4000 pieces per 13-in. reel 10-pin MSOP with exposed thermal pad

ABSOLUTE MAXIMUM RATINGS [1]

Characteristic Symbol Notes Rating Unit
Load Supply Voltage VIN –0.3 to 50 V
Pin EN –0.3 to 50 V
All LAx pins –0.3 to 50 V
Pin FF –0.3 to 50 V
Pins IREF, THTH –0.3 to 6.5 V
Ambient Operating Temperature E temperature range –40 to 85 °C
TA
Range [2] K temperature range –40 to 125 °C
Maximum Continuous Junction
TJ(max) 150 °C
Temperature
Overtemperature event not exceeding 10 seconds, lifetime duration
Transient Junction Temperature TtJ 175 °C
not exceeding 10 hours, ensured by design characterization
Storage Temperature Range Tstg –55 to 150 °C

[1] With respect to GND.

[2] Limited by power dissipation.

THERMAL CHARACTERISTICS [3]: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions* Value Unit
On 4-layer PCB based on JEDEC standard 35 °C/W
LJ package
On 2-layer PCB with 0.8 in.2 of copper area each side 62 °C/W

Package Thermal Resistance On 4-layer PCB based on JEDEC standard 34 °C/W

RθJA LP package
(Junction to Ambient) On 2-layer PCB with 3.8 in.2 of copper area each side 43 °C/W

On 4-layer PCB based on JEDEC standard 48 °C/W

LY package
On 2-layer PCB with 2.5 in.2 of copper area each side 48 °C/W
Package Thermal Resistance
RθJP 2 °C/W
(Junction to Pad)

[3] To be verified by characterization for LP and LY. Additional thermal information available on the Allegro™ website.

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A6261 Protected LED Array Driver

+V
VIN

EN Control Current
Logic Regulators
LA1
THTH Temp Temp Slew
LA2
Comp Monitor Limit
LA3
IREF Current
Reference LA4
FF
Fault
RTH Control
RREF
PAD
GND

LP and LY
packages only

Functional Block Diagram

PINOUT DIAGRAMS AND TERMINAL LIST TABLE

Terminal List Table

THTH 1 8 FF
IREF 2 7 EN Number
PAD
GND 3 6 VIN Name LJ LP LY Function
LA1 4 5 LA2
EN 7 13 9 Enable
LJ Package FF 8 14 10 Fault output
GND 3 5 3 Ground reference
NC 1 16 NC
15 NC
IREF 2 4 2 Current reference
NC 2
THTH 3 14 FF LA1 4 6 4 LED anode (+) connection 1
IREF 4 13 EN LA2 5 7 5 LED anode (+) connection 2
PAD
GND 5 12 VIN
LA3 – 10 6 LED anode (+) connection 3
LA1 6 11 LA4
LA2 7 10 LA3 LA4 – 11 7 LED anode (+) connection 4
NC 8 9 NC 1,2,8,
NC – – No connection; connect to GND
9,15,16
LP Package
PAD – – – Exposed thermal pad
THTH 1 10 FF THTH 1 3 1 Thermal threshold
IREF 2 9 EN VIN 6 12 8 Supply
GND 3 PAD 8 VIN
LA1 4 7 LA4
LA2 5 6 LA3

LY Package

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A6261 Protected LED Array Driver

ELECTRICAL CHARACTERISTICS [1]: Valid at TJ = –40°C to 150°C, VIN = 7 to 40 V, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
SUPPLY AND REFERENCE
VIN Functional Operating Range [2] VIN 6 – 50 V
VIN Quiescent Current IINQ All LAx pins connected to VIN – – 10 mA
VIN Sleep Current IINS EN = GND, VIN = 16 V – – 10 µA
VIN > 7 V to ILA2 < –5 mA, RREF = 125 Ω (except
LJ-1 version);
Startup Time tON 5 20 30 µs
VIN > 7 V to ILA2 < –10 mA, RREF = 125 Ω (LJ-1
version)
CURRENT REGULATION
Reference Voltage VIREF 0.7 mA < IREF < 8.8 mA 1.15 1.2 1.25 V
GH0 LP and LY packages, ILAx / IREF – 12.5 – –
LJ package only ILA1 / IREF, LJ-1 package,
Reference Current Ratio GH1 – 25 – –
ILAx/IREF
GH2 LJ package only ILA2 / IREF – 12.5 – –
10% ILANx > ILAx > 100% ILANx –5 ±4 5 %
Current Accuracy [3] EILAx
ILAx = 10 mA, LJ-1 (200 mA × 2 channel) option [5] – 10 – %
LP and LY packages only –20 mA > ILAx >
Current Matching [4] EIMLAx –100 mA, LJ-1 package only –40 mA > ILAx > – 5 10 %
–200 mA, VLAx match to within 1 V
GHx ×
ILAx EN = high – – –
IREF
IREF = 8 mA, EN = high, LP, LY and LA2 pin of
Output Current ILAN0 –105 –100 –95 mA
LJ package
IREF = 8 mA, EN = high, LJ-1 and LA1 pin of LJ
ILAN1 –210 –200 –190 mA
package
IREF = 9.2 mA, EN = high, LP, LY and LA2 pin of
ILAxmax – – –110 mA
LJ package
Maximum Output Current
IREF = 9.2 mA, EN = high, LJ-1 and LA1 pin of
ILA1max – – –220 mA
LJ package
VIN – VLAx , ILAx = –100 mA, LP, LY and LA2 pin
– – 800 mV
of LJ package
VIN – VLAx , ILAx = –200 mA, LJ-1 and LA1
– – 800 mV
pin of LJ package
Minimum Drop-Out Voltage VDO
VIN – VLAx , ILAx = –40 mA , LP, LY and LA2 pin
– – 660 mV
of LJ package
VIN – VLAx , ILAx = –80 mA, LJ-1 and LA1
– – 660 mV
pin of LJ package
Output Disable Threshold VODIS VIN – VLAx 65 – 160 mV
Current Slew Time tSL Current rising or falling between 10% and 90% 50 80 110 µs

Continued on the next page…

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A6261 Protected LED Array Driver

ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TJ = –40°C to 150°C, VIN = 7 to 40 V, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
LOGIC INPUTS FF AND EN
Input Low Voltage VIL – – 0.8 V
Input High Voltage VIH 2 – – V
Input Hysteresis (EN pin) VIhys 150 350 – mV
Pull-Down Resistor (EN pin) RPD – 50 – kΩ
Output Low Voltage (FF pin) VOL IOL = 1 mA – – 0.4 V
PROTECTION
Short Detect Voltage VSCD Measured at LAx 1.2 – 1.8 V
Short present LAx to GND: LP, LY and LA2 pin
ISCS0 –2 –0.8 –0.5 mA
of LJ package
Short-Circuit Source Current
Short present LAx to GND: LJ-1 and LA1 pin of
ISCS1 –4 –1.6 –1 mA
LJ package
Short Release Voltage VSCR Measured at LAx – – 1.9 V
Short Release Voltage Hysteresis VSChys VSCR – VSCD 200 – 500 mV
Open-Load Detect Voltage VOCD VIN – VLAx 170 – 450 mV
Open-Load Detect Delay tOCD – 2 – ms
Thermal Monitor Activation Temperature TJM TJ with ISEN = 90%, THTH pin is open 95 115 130 °C
Thermal Monitor Slope dISEN/dTJ ISEN = 50% –3.5 –2.5 –1.5 %/°C
Thermal Monitor Low Current
TJL TJ at ISEN = 25%, THTH pin is open 120 135 150 °C
Temperature
Overtemperature Shutdown TJF Temperature increasing – 170 – °C
Overtemperature Hysteresis TJhys Recovery = TJF – TJhys – 15 – °C

[1] For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
[2] Function is correct but parameters are not guaranteed outside the general limits (7 to 40 V).
[3] When EN = high, E
ILAx = 100 × [( | ILAx | × RREF / 15 ) –1], with ILAx in mA and RREF in kΩ, for LP, LY and LA2 pin of LJ package.
[4] E
IMLA = 100 × max ( | ILAx– ILA(AV) | ) / ILA(AV) , where ILA(AV) is the average current of all active outputs.
[5] Guaranteed by design and characterization, not production tested.

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A6261 Protected LED Array Driver

FUNCTIONAL DESCRIPTION

The A6261 is a linear current regulator that is designed to provide LA[1:4]. Current source connected to the anode of the first
drive current and protection for parallel strings of series-con- LED in each string. Connect directly to VIN to disable the
nected high brightness LEDs. The LP and LY options provide up respective output. In this document, “LAx” indicates any one
to four matched programmable current outputs at up to 100 mA, output of the ICs.
and LJ-1 option provides two outputs with 200mA per channel, FF. Open drain fault flag, used with an external pull-up resistor,
whereas the LJ option provides two outputs, LA1 = 200 mA and to indicate open, short, or overtemperature conditions. FF is inac-
LA2 = 100 mA. All the outputs have low minimum dropout volt- tive when a fault is present. During an open-load condition, FF
ages below the main supply voltage. For 12 V power net applica- can be pulled low to force the remaining outputs on.
tions, optimum performance is achieved when driving all strings LED Current Level
of 1 to 3 series connected LEDs, at rated current per string.
The LED current is controlled by four matching linear current
The A6261 is specifically designed for use in applications where regulators between the VIN pin and each of the LAx outputs. The
the LED current is controlled by a single logic input or a high- basic equation that determines the nominal output current at each
side switched supply. In addition, the A6261 disables all LEDs on LAx pin is:
detecting a single open LED. Given EN = high,
Current regulation is maintained and the LEDs protected during a
1.2 (1)
short-to-ground at any point in the LED string. A short-to-ground IREF =
on any regulator output terminal will disable that output and set RREF
the fault flag. An open load on any output will set the fault flag and
and disable all outputs. Remaining outputs can be re-enabled
by pulling the fault flag output low. Individual outputs can be ILAx = GHx × IREF (2)
disabled by connecting the output to VIN.
Integrated thermal management reduces the regulated current where ILAx is in mA and RREF is in kΩ.
level at high internal junction temperatures to limit power dis- The output current may be reduced from the set level by the ther-
sipation. mal monitor circuit.

Pin Functions Conversely, the reference resistors may be calculated from:

VIN Supply to the control circuit and current regulators. A small

1.2 × GHx
value ceramic bypass capacitor, typically 100 nF, should be con- RREF = (3)
ILAx
nected from close to this pin to the GND pin.
GND. Ground reference connection. Should be connected where ILAx is in mA and RREF is in kΩ.
directly to the negative supply. For example, where the required current is 90 mA per channel in
LP or LY package the resistor value will be :
EN. Logic input to enable LED current output. This provides a
direct on/off action and can be used for direct PWM control.
RREF = 15 = 167 Ω
IREF. 1.2 V reference to set current reference. Connect resistor, 90
RREF, to GND to set reference current.
These equations completely define the output currents with
THTH. Sets the thermal monitor threshold, TJM , where the output respect to the setting resistors. However, for further reference, a
current starts to reduce with increasing temperature. Connecting more detailed description of the internal reference current calcu-
THTH directly to GND will disable the thermal monitor function. lations is included below.

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A6261 Protected LED Array Driver

It is important to note that because the A6261 is a linear regu- rents, or by connecting the output directly to VIN to disable the
lator, the maximum regulated current is limited by the power regulator for that output. When a regulator is disabled, it will
dissipation and the thermal management in the application. All not indicate an open load and will not affect the fault flag or the
current calculations assume adequate heatsinking for the dissi- operation of the remaining regulator outputs.
pated power. Thermal management is at least as important as the
electrical design in all applications. In high-current, high-ambient Sleep Mode
temperature applications, the thermal management is the most When EN is held low, the A6261 will be in shutdown mode and
important aspect of the systems design. The application section all sections will be in a low-power sleep mode. The input current
below provides further detail on thermal management and the will be typically less than 10 µA. This means that the complete
associated limitations. circuit, including LEDs, may remain connected to the power sup-
ply under all conditions.
Operation with Fewer LED Strings or Higher Currents
The A6261 may be configured to use fewer than four LED
strings, either by connecting outputs together for higher cur-

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A6261 Protected LED Array Driver

Safety Features
VIN
The circuit includes several features to ensure safe operation and A6261
to protect the LEDs and the A6261: LA1
A. Any LED cathode short-to-ground.
LA2
• The current regulators between VIN and each LAx output Current remains regulated in
LA3
provide a natural current limit due to the regulation. LA4
non-shorted LEDs. Matching may
be affected. FF is low.
• Each LAx output includes a short-to-ground detector that will
disable the output to limit the dissipation. GND
• An open circuit on any output will disable all outputs.
• The thermal monitor reduces the regulated current as the
temperature rises.
• Thermal shutdown completely disables the outputs under VIN
extreme overtemperature conditions. A6261
LA1
SHORT CIRCUIT DETECTION LA2 B. Any LAx output short-to-ground.
A short-to-ground on any LED cathode (Figure 1A) will not LA3 Shorted output is disabled. Other
LA4 outputs remain active. FF is high.
result in a short fault condition. The current through the remain-
ing LEDs will remain in regulation and the LEDs will be pro-
tected. Due to the difference in the voltage drop across the LEDs GND
as a result of the short, the current matching in the A6261 may
exceed the specified limits.
Any LAx output that is pulled below the short detect voltage
(Figure 1B) will disable the regulator on that output and allow VIN
the fault flag, FF, to go high. A small current will be sourced A6261
from the disabled output to monitor the short and detect when LA1 C. Shorted LEDs.
it is removed. When the voltage at LAx rises above the short LA2 Current remains regulated.
detect voltage, the fault flag will be removed and the regulator LA3 Matching may be affected.
re-enabled. LA4 Only the shorted LED is inactive.
FF is low.
A shorted LED (Figure 1C) will not result in a short fault condi-
GND
tion. The current through the remaining LEDs will remain in
regulation and the LEDs will be protected. Due to the difference
in the voltage drop across the LEDs as a result of the short, the
current matching in the A6261 may exceed the specified limits.
A short between LEDs in different strings (Figure 1D) will not VIN
result in a short fault condition. The current through the remain- A6261
ing LEDs will remain in regulation, and the LEDs will be D. Short between LEDs in different
LA1
strings. Current remains regulated.
protected. The current will be summed and shared by the affected LA2
Current is summed and shared by
strings. Current matching in the strings will then depend on the LA3
affected strings. Intensity match
LED forward voltage differences. LA4
dependent on voltage binning.
FF is low.
GND

Figure 1: Short-Circuit Conditions

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A6261 Protected LED Array Driver

OPEN-LOAD DETECTION TEMPERATURE MONITOR

An open-load condition is detected when the voltage across the A temperature monitor function, included in the A6261, reduces
regulator, VIN – VLAx , is less than the open-load detect voltage, the LED current as the silicon junction temperature of the A6261
VOCD , but greater than the output disable threshold voltage, increases (see Figure 2). By mounting the A6261 on the same
VODIS . When this condition is present for more than the open- thermal substrate as the LEDs, this feature can also be used to
load detect time, tOCD , then all regulators will be disabled and the limit the dissipation of the LEDs. As the junction temperature of
fault flag allowed to go high. the A6261 increases, the regulated current level is reduced, reduc-
ing the dissipated power in the A6261 and in the LEDs. The cur-
The regulators will remain disabled until either the power is
rent is reduced from the 100% level at typically 2.5% per degree
cycled off and on, the EN input is taken low then high, or the
Celsius until the point at which the current drops to 25% of the
fault flag, FF, is pulled low. If the power is cycled or EN is pulsed
full value, defined at TJL . Above this temperature, the current will
low, the regulators will start in the enabled state, unless disabled
continue to reduce at a lower rate until the temperature reaches
by tying the output to VIN, and the open-load detection timer will
the overtemperature shutdown threshold temperature, TJF.
be reset. If the open load is still present the regulators will again
be disabled after the open-load detect time. The temperature at which the current reduction begins can be
adjusted by changing the voltage on the THTH pin. When THTH
Pulling the fault flag low will override the open-load fault action
is left open, the temperature at which the current reduction begins
and all enabled regulators will be switched on. This state will
is defined as the thermal monitor activation temperature, TJM, and
be maintained while the fault flag is held low. If the fault flag is
is specified in the characteristics table at the 90% current level.
allowed to go high the A6261 will return to the open-load fault
condition and will disable all regulators.
110

Each of the four regulators includes a limiter to ensure that 100

the output voltage will not rise higher than the output disable
threshold voltage below VIN when driven by the regulator. This 90

means that the voltage across the regulator will not be less than 80
Relative Sense Current (%)

the output disable voltage, unless it is forced by connecting the 70

LAx pin to VIN. However if a load becomes disconnected, the
60
regulator will pull the LAx pin up to the limit, which will ensure
that the voltage across the regulator, VIN – VLAx , is less than the 50

open-load detect voltage, VOCD . 40

Note that an open load may also be detected if the sum of the for- 30

ward voltages of the LEDs in a string is close to or greater than 20

the supply voltage on VIN.
10 TJM
TJL
0
70 80 90 100 110 120 130 140 150 160 170 180

Junction Temperature, TJ (°C)

Figure 2: Temperature Monitor Current Reduction

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A6261 Protected LED Array Driver

Thermal monitor activation temperature can be set to a desired to estimate THTH pin resistor (RTH). If the pull-up voltage is 5 V,
level by setting the voltage on the THTH pin (VTHTH). There then a 211 kΩ resistor should be used. If the pull-up voltage is
is an internal 1 V source connected with a series resistor to the 3 V, use a 100 kΩ resistor.
THTH pin inside the IC. A resistor connected between THTH and
In extreme cases, if the chip temperature exceeds the overtem-
GND will reduce VTHTH and increase TJM. A resistor connected
perature limit, TJF , all regulators will be disabled. The tempera-
between THTH and a reference supply greater than 1 V will
ture will continue to be monitored and the regulators re-activated
increase VTHTH and reduce TJM.
when the temperature drops below the threshold provided by the
Figure 3a shows the relationship between TJM and VTHTH while specified hysteresis.
Figure 3b shows typical resistor values, either pull up or pull
Note that it is possible for the A6261 to transition rapidly
down, to set the voltage on THTH pin.
between thermal shutdown and normal operation. This can hap-
Now, based on the TJM requirement, estimate the required VTHTH pen if the thermal mass attached to the exposed thermal pad is
voltage from Figure 3a, and then, depending on the VTHTH value, small and TJM is increased to close to the shutdown temperature.
decide the THTH pin resistor from Figure 3b. THTH pin resistor
The period of oscillation will depend on TJM, the dissipated
may either pull up or pull down depending on VTHTH.
power, the thermal mass of any heatsink present, and the ambient
As an example, if TJM of 90°C is required, then from Figure 3a, temperature.
VTHTH should be 1.115 V. To achieve this voltage, use Figure 3b

1.25
1.25

1.20
1.2
RTH Pull up to 5 V
1.15
1.15

1.10 RTH Pull up to 3 V

1.1

1.05
VTHTH (V)

1.05
VTHTH (V)

1.00 RTH Pull down to GND

1

0.95
0.95

0.90
0.9

0.85
0.85

0.80
0.8 0 50 100 150 200 250
70 80 90 100 110 120 130 140 150
RTH (kΩ)
Thermal Monitor Activation Temperature, T JM (°C )

Figure 3a: Relationship Between TJM and VTHTH Figure 3b: Typical Resistor Values to Set Voltage on
THTH Pin

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A6261 Protected LED Array Driver

APPLICATION INFORMATION

Power Dissipation Note that the voltage drop across the regulator, VREG , is always
greater than the specified minimum dropout voltage, VDO . The
The most critical design considerations when using a linear regu- output current is regulated by making this voltage large enough
lator such as the A6261 are the power produced internally as heat to provide the voltage drop from the supply voltage to the total
and the rate at which that heat can be dissipated. forward voltage of all LEDs in series, VLED .
There are three sources of power dissipation in the A6261: The total power dissipated in the A6261 is the sum of the qui-
• The quiescent power to run the control circuits escent power, the reference power, and the power in each of the
four regulators:
• The power in the reference circuit
• The power due to the regulator voltage drop
PDIS = PQ + PREF (7)
The elements relating to these dissipation sources are illustrated + PREGA + PREGB + PREGC + PREGD
in Figure 4.
The power that is dissipated in each string of LEDs is:
QUIESCENT POWER
The quiescent power is the product of the quiescent current, IINQ , PLEDx = VLEDx × ILEDx
(8)
and the supply voltage, VIN , and is not related to the regulated
current. The quiescent power, PQ, is therefore defined as:
where x is A, B, C, or D, and VLEDx is the voltage across all
PQ = VIN × IINQ (4) LEDs in the string.
REFERENCE POWER From these equations (and as illustrated in Figure 5) it can be
seen that, if the power in the A6261 is not limited, then it will
The reference circuit draws the reference current from the supply
increase as the supply voltage increases but the power in the
and passes it through the reference resistor to ground. The refer-
LEDs will remain constant.
ence current is 8% of the output current on any one active output.
The reference circuit power is the product of the reference current
and the difference between the supply voltage and the reference
voltage, typically 1.2 V. The reference power, PREF , is therefore
defined as:

VIN
(VIN – VREF) × VREF
PREF = (5) A6261
RREF VREG
ILAx
REGULATOR POWER LAx
In most application circuits, the largest dissipation will be pro-
duced by the output current regulators. The power dissipated in
VIN IREF IINQ
each current regulator is simply the product of the output current
and the voltage drop across the regulator.
VLED
The total current regulator dissipation is the sum of the dissipa- IREF
tion in each output regulator. The regulator power for each output
is defined as:
VREF RREF

PREGx = (VIN – VLEDx ) × ILEDx

(6) GND

where x is 1, 2, 3, or 4. Figure 4: Internal Power Dissipation Sources

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A6261 Protected LED Array Driver

3.0 the graph shows the current as the supply voltage increases from
14 to 17 V. As the supply voltage increases, without the thermal
2.5 foldback feature, the current would remain at 50 mA, as shown by
Power Dissipation, PD (W)

the dashed line. The solid line shows the resulting current decrease
2.0
as the thermal foldback feature acts.
1.5 If the thermal foldback feature did not affect LED current, the
LED Power current would increase the power dissipation and therefore the
1.0 silicon temperature. The thermal foldback feature reduces power
A6261 Power in the A6261 in order to limit the temperature increase, as shown
0.5 in Figure 7. The figure shows the operation of the A6261 under
the same conditions as Figure 6. That is, 4 strings of 3 red LEDs,
0
8 9 10 11 12 13 14 15 16 each string running at 50 mA with each LED forward voltage at
Supply Voltage, VIN (V) 2.3 V. The graph shows the temperature as the supply voltage
Figure 5: Power Dissipation versus Supply Voltage
54
Dissipation Limits
52
There are two features limiting the power that can be dissipated
Without thermal monitor
by the A6261: thermal shutdown and thermal foldback. 50
ILED (mA)

THERMAL SHUTDOWN 48
With thermal monitor
If the thermal foldback feature is disabled by connecting the 46 4 Strings
THTH pin to GND, or if the thermal resistance from the A6261 VLED = 6.9 V
44 ILED = 50 mA
to the ambient environment is high, then the silicon temperature TA = 50°C
will rise to the thermal shutdown threshold and the current will be 42
disabled. After the current is disabled, the power dissipated will
drop and the temperature will fall. When the temperature falls by 40
14.0 14.5 15.0 15.5 16.0 16.5 17.0
the hysteresis of the thermal shutdown circuit, then the current Supply Voltage, VIN (V)
will be re-enabled and the temperature will start to rise again.
Figure 6: LED current versus Supply Voltage
This cycle will repeat continuously until the ambient temperature
drops or the A6261 is switched off. The period of this thermal
shutdown cycle will depend on several electrical, mechanical, 130
and thermal parameters and could be from a few milliseconds to
4 Strings
a few seconds. 125
VLED = 6.9 V Without thermal monitor
ILED = 50 mA
THERMAL FOLDBACK 120 TA = 50°C
TJ (°C)

If there is a good thermal connection to the A6261, then the 115

thermal foldback feature will have time to act. This will limit the With thermal monitor

silicon temperature by reducing the regulated current and there- 110

fore the dissipation.
105
The thermal monitor will reduce the LED current as the tempera-
ture of the A6261 increases above the thermal monitor activation
100
temperature, TJM , as shown in Figure 6. The figure shows the 14.0 14.5 15.0 15.5 16.0 16.5 17.0
operation of the A6261 with 4 strings of 3 red LEDs, each string Supply Voltage, VIN (V)
running at 50 mA. The forward voltage of each LED is 2.3 V and
Figure 7: Junction Temperature versus Supply Voltage

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A6261 Protected LED Array Driver

increases from 14 to 17 V. Without the thermal foldback feature,

the temperature would continue to increase up to the thermal
shutdown temperature as shown by the dashed line. The solid line
shows the effect of the thermal foldback function in limiting the
temperature rise.
Figures 6 and 7 show the thermal effects where the thermal
resistance from the silicon to the ambient temperature is 40°C/W.
Thermal performance can be enhanced further by using a signifi-
cant amount of thermal vias as described below. LJ Package

Thermal Dissipation
The amount of heat that can pass from the silicon of the A6261
to the ambient environment depends on the thermal resistance of
the structures connected to the A6261. The thermal resistance,
RθJA , is a measure of the temperature rise created by the power
dissipated and is usually measured in degrees Celsius per watt
(°C/W).
The temperature rise, ΔT, is calculated from the power dissipated,
PD , and the thermal resistance, RθJA , as:
LP Package
ΔT = PD × RθJA (9)
A thermal resistance from silicon to ambient, RθJA , of approxi-
mately 30°C/W (LP package) or 34°C/W (LY package), can be
achieved by mounting the A6261 on a standard FR4 double-sided
printed circuit board (PCB) with a copper area of a few square
inches on each side of the board under the A6261. Multiple
thermal vias, as shown in Figure 8, help to conduct the heat from
the exposed pad of the A6261 to the copper on each side of the
board. The thermal resistance can be reduced by using a metal
substrate or by adding a heatsink.

Supply Voltage Limits

In some applications, the available supply voltage can vary over LY Package
a two-to-one range— for example, emergency lighting systems
using battery backup. In such systems is it necessary to design
the application circuit such that the system meets the required
performance targets over a specified voltage range.
To determine this range when using the A6261, there are two
limiting conditions: Figure 8: Board Via Layout for Thermal Dissipation

• For maximum supply voltage, the limiting factor is the power

that can be dissipated from the regulator without exceeding the
temperature at which the thermal foldback starts to reduce the
output current below an acceptable level.

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A6261 Protected LED Array Driver

• For minimum supply voltage, the limiting factor is the defined as the voltage above which the LED current drops below
maximum dropout voltage of the regulator, where the the acceptable minimum.
difference between the load voltage and the supply is
This can be estimated by determining the maximum power that
insufficient for the regulator to maintain control over the
can be dissipated before the internal (junction) temperature of the
output current.
A6261 reaches TJM.
MINIMUM SUPPLY LIMIT: REGULATOR SATURATION Note that, if the thermal monitor circuit is disabled (by connect-
VOLTAGE ing the THTH pin to GND), then the maximum supply limit will
The supply voltage, VIN , is always the sum of the voltage drop be determined by the specified maximum continuous operating
across the high-side regulator, VREG , and the forward voltage of temperature, 150°C.
the LEDs in the string, VLED, as shown in Figure 4. The maximum power dissipation is therefore defined as:
VLED is constant for a given current and does not vary with sup-
ply voltage. Therefore, VREG provides the variable difference ∆T
between VLED and VIN . VREG has a minimum value below which PD(max) = (11)
RθJA
the regulator can no longer be guaranteed to maintain the output
current within the specified accuracy. This level is defined as the where ΔT is difference between the thermal monitor activa-
regulator dropout voltage, VDO. tion temperature, TJM , of the A6261 and the maximum ambient
The minimum supply voltage, below which the LED current temperature, TA(max), and RθJA is the thermal resistance from the
does not meet the specified accuracy, is therefore determined by internal junctions in the silicon to the ambient environment.
the sum of the minimum dropout voltage, VDO , and the forward If minimum LED current is not a critical factor, then the maxi-
voltage of the LEDs in the string, VLED . The supply voltage must mum voltage is simply the absolute maximum specified in the
always be greater than this value and the minimum specified sup- parameter tables above.
ply voltage, that is:
Application Examples
VIN > VDO + VLED,
In some filament bulb replacement applications, the supply may
and be provided by a PWM-driven, high-side switch. The A6261 can
be used in this application by simply connecting EN to VIN.
VIN > VIN (min) (10)
If neither fault action nor fault reporting is required, then FF
As an example, consider the configuration used in Figures 6
should be tied to ground.
and 7 above, namely 4 strings of 3 red LEDs, each string running
at 50 mA, with each LED forward voltage at 2.3 V. The minimum When power is applied, there will be a short startup delay, tON ,
supply voltage will be approximately: before the current starts to rise. The current rise time will be lim-
ited by the internal current slew rate control.
VIN(min) = 0.55 + (3 × 2.3) = 7.45 V
The application circuit options in Figure 9 show operation with
MAXIMUM SUPPLY LIMIT: THERMAL LIMITATION a higher voltage supply and with combinations of outputs tied
As described above, when the thermal monitor reaches the activa- together and disabled.
tion temperature, TJM (due to increased power dissipation as the
supply voltage rises), the thermal foldback feature causes the out-
put current to decrease. The maximum supply voltage is therefore

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A6261 Protected LED Array Driver

+ +
12 V PWM 24 V
high-side drive
VIN VIN
A6261 A6261
(LP, LY Packages) (LP, LY Packages)
PWM dimming LA1
input LA2
EN LA1 EN LA3
FF LA2 FF LA4
Fault output
IREF LA3 IREF
THTH LA4 THTH

GND GND

– –

A. High brightness (HB) LED incandescent lamp replacement B. Higher voltage operation

+ +
12 V 14 V

VIN VIN
A6261 A6261
(LP, LY Packages) (LJ Package)
PWM dimming PWM dimming
input input LA1
EN LA1 EN
FF LA2 FF LA2
IREF LA3 IREF

THTH LA4 THTH

GND GND

– –

C. Mix of output combinations D. A6261LJ: Single output with 100mA. For 200 mA
single output, connect LA2 to VIN and LEDs to LA1.

Figure 9: Typical Applications with Various Supply and Output Options.

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A6261 Protected LED Array Driver

Binning Resistor Arrangement

An external binning resistor can be connected in series with the
IREF pin to set appropriate current through various LED batches.
A filter capacitor of 100 nF should be placed after RREF1 as
shown in Figure 10.

ILAx(min) = (1.2 × GHX) ÷ (RREF1 + RREF2) (12)

ILAx(max) = (1.2 × GHX) ÷ RREF1 (13)

LED Driver Board LED Board

VIN

A6261 LED1 LED2

(LJ Package)

FF LA1
EN LA2
THTH LED3 LED4
RREF1
IREF

GND

CREF RREF2

Figure 10: Application Circuit for Binning –

Current-setting resistor (RREF2) can be placed
on LED board for different bins of LEDs.

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A6261 Protected LED Array Driver

PACKAGE OUTLINE DRAWINGS

For Reference Only – Not for Tooling Use

(Reference MS-012BA)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

4.90 ±0.10 8° 0.65 1.27

0°
8
8
0.25 1.75
0.17

B
2.41 NOM 3.90 ±0.10 6.00 ±0.20 2.41 5.60
A

1.04 REF
1 2
1.27 1 2
3.30 NOM
0.40
3.30

0.25 BSC C PCB Layout Reference View

Branded Face
SEATING PLANE
GAUGE PLANE
8X C
1.70 MAX A Terminal #1 mark area
0.10 C
SEATING
PLANE B Exposed thermal pad (bottom surface)
0.51
0.31 C Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM);
0.15 all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
0.00 to meet application process requirements and PCB layout tolerances; when
1.27 BSC mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

Figure 11: Package LJ, 8-Pin SOICN with Exposed Thermal Pad

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A6261 Protected LED Array Driver

For Reference Only – Not for Tooling Use

(Reference MO-153 ABT)
Dimensions in millimeters. NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

0.45 0.65
8º
0º
5.00 ±0.10 16

16
0.20 1.70
0.09

3 NOM 4.40 ±0.10 6.40 ±0.20 3.00 6.10

A
0.60 ±0.15
1.00 REF

1 2
3 NOM
0.25 BSC 1 2
Branded Face
SEATING PLANE 3.00
16X C
SEATING GAUGE PLANE
0.10 C PLANE C PCB Layout Reference View

0.30
0.19 1.20 MAX
0.65 BSC
0.15 NNNNNNN
0.00 YYWW
LLLL
A Terminal #1 mark area

B Exposed thermal pad (bottom surface); dimensions may vary with device
1
C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); D Standard Branding Reference View
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary N = Device part number
to meet application process requirements and PCB layout tolerances; when = Supplier emblem
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land Y = Last two digits of year of manufacture
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) W = Week of manufacture
L = Characters 5-8 of lot number
D Branding scale and appearance at supplier discretion

Figure 12: Package LP, 16-Pin TSSOP with Exposed Thermal Pad

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A6261 Protected LED Array Driver

For Reference Only – Not for Tooling Use

(Reference JEDEC MO-187)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

0° to 6°
3.00 ±0.10

10
0.15 ±0.05

3.00 ±0.10 4.88 ±0.20

0.53 ±0.10
1 2
1.98 0.25

1 2 Seating Plane
Gauge Plane

A Terminal #1 mark area

B B Exposed thermal pad (bottom surface)

1.73

10

0.86 ±0.05

SEATING
PLANE
0.27 0.50 0.05
0.18 REF 0.15

Figure 13: Package LY, 10-Pin MSOP with Exposed Thermal Pad

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A6261 Protected LED Array Driver

Revision History
Number Date Description
8 September 10, 2013 Add LJ package
9 December 6, 2014 Add LJ-1 package; revised Selection Guide
10 June 25, 2015 Temperature Monitor text on page 9 updated to match EC table: derating slope is –2.5% per °C
11 September 30, 2015 Removed Contact Factory status from A6261KLJTR-T-1; THTH pin resistor (RTHTH) selection
description modified; Binning resistor application note added; figure 2 updated.
12 July 28, 2016 Updated Figure 10
13 January 8, 2018 Updated Current Accuracy characteristic in EC table (page 4)
14 January 21, 2019 Minor editorial updates

Copyright ©2019, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

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