SGM41513/SGM41513A/SGM41513D

High Input Voltage, 3A Single-Cell Battery Charger

with NVDC Power Path Management
FEATURES ● Fully Integrated All MOSFETs, Current Sense and
Compensation
● 3.9V to 13.5V Operating Input Voltage Range
● 2.5μA Ship Mode Low Battery Leakage Current
● Up to 22V Sustainable Voltage
● High Accuracy
● High Efficiency, 1.5MHz, Synchronous Buck Charger
 ±0.6% Charge Voltage Regulation (8mV/Step)
 93.8% Charge Efficiency at 1.02A from 5V Input
 ±5% Charge Current Regulation at 1.38A
 89.8% Charge Efficiency at 2A from 9V Input
 ±33% Charge Current Regulation at 60mA
 Optimized for 9V/12V Input
 ±10% Input Current Regulation at 0.9A
 Selectable PFM Mode for Light Load Efficiency
● Safety
● USB On-The-Go (OTG) Support (Boost Mode)
 Battery Temperature Sensing (Charge/Boost Modes)
 Boost Converter with up to 1.2A Output
 Thermal Regulation and Thermal Shutdown
 Boost Efficiency of 93.5% at 0.5A and 92.2% at 1A
 Input Under-Voltage Lockout (UVLO)
 Accurate Hiccup Mode Over-Current Protection
 Input Over-Voltage (ACOV) Protection
 Soft-Start Capable with up to 500μF Capacitive Load
 Output Short Circuit Protection
 Selectable PFM Mode for Light Load Operations APPLICATIONS
● Programmable Input Current Limit (IINDPM) and
Smart Phones, EPOS
Dynamic Power Management to Support USB Portable Internet Devices and Accessory
Standard Adapters
● Maximum Power Tracking by Programmable Input
Voltage Limit (VINDPM) with Selectable Offset
SIMPLIFIED SCHEMATIC
● VINDPM Tracking of Battery Voltage Input
3.9V to 13.5V
SW
● Auto Detect USB BC1.2, SDP, CDP, DCP and OTG
VBUS
SYS
USB 5V at 1.2A 3.5V to 4.6V
Non-Standard Adaptors BTST

SYS
● High Battery Discharge Efficiency with 26mΩ Switch ICHG = 3A
BAT
● Narrow Voltage DC (NVDC) Power Path Management
nQON
I2C Bus
 Instant-On with No or Highly Depleted Battery
SGM41513
 Ideal Diode Operation in Battery Supplement Mode Host SGM41513A REGN Optional
SGM41513D
● Ship Mode, Wake-Up and Full System Reset Capability Host Control

by Battery FET Control TS

2
● Flexible Autonomous and I C Operation Modes for
Optimal System Performance

SG Micro Corp SEPTEMBER 2022 – REV. B

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This datasheet has been downloaded from http://www.digchip.com at this page

SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

GENERAL DESCRIPTION
The SGM41513/SGM41513A/SGM41513D are battery management (DPM) feature is also included that
chargers and system power path management devices with automatically reduces the charge current if the input current
integrated converter and power switches for using with or voltage limit is reached. If the system load continues to
single-cell Li-Ion or Li-polymer batteries. This highly increase after reduction of charge current down to zero, the
integrated 3A device is capable of fast charging and supports power path management provides the deficit from battery by
a wide input voltage range suitable for smart phones, tablets discharging battery to the system until the system power
2
and portable systems. I C programming makes it a very demand is fulfilled. This is called supplement mode, which
flexible powering and charger design solution. prevents the input source from overloading.

The devices include four main power switches: input reverse Starting and termination of a charging cycle can be
blocking FET (RBFET, Q1), high-side switching FET for Buck accomplished without software control. The sensed battery
or Boost mode (HSFET, Q2), low-side switching FET for Buck voltage is used to decide for starting phase of charging in one
or Boost mode switching (LSFET, Q3) and battery FET that of the three phases of charging cycle: pre-conditioning,
controls the interconnection of the system and battery constant current or constant voltage. When the charge
(BATFET, Q4). The bootstrap diode for the high-side gate current falls below a preset limit and the battery voltage is
driving is also integrated. The internal power path has a very above recharge threshold, the charger function will
low impedance that reduces the charging time and maximizes automatically terminate and end the charging cycle. If the
the battery discharge efficiency. Moreover, the input voltage voltage of a charged battery falls below the recharge
and current regulations provide maximum charging power threshold, the charger begins another charging cycle.
delivery to the battery with various types of input sources.
Several safety features are provided in the SGM41513/
A wide range of input sources are supported, including SGM41513A/SGM41513D such as over-voltage and
standard USB hosts, charging ports and USB compliant high over-current protections, battery temperature monitoring,
voltage adapters. The default input current limit is charging safety timing, thermal shutdown and input UVLO.
automatically selected based on the built-in USB interface. TS pin is connected to an NTC thermistor for battery
This limit is determined by the detection circuit in the system temperature monitoring and protection in both charge and
(e.g. USB PHY). The SGM41513/SGM41513A/SGM41513D Boost modes according to JEITA profile. This device also
are USB 2.0 and USB 3.0 power specifications compliant with features thermal regulation in which the charge current is
input current and voltage regulation. It also meets USB reduced, if the junction temperature exceeds 80℃ or 120℃
On-The-Go (OTG) power rating specification and is capable (selectable).
to boost the battery voltage to supply 5.15V on VBUS with
Charging status is reported by the STAT output and
1.2A (or 0.5A) current limit.
fault/status bits. A negative pulse is sent to the nINT output
The system voltage is regulated slightly above the battery pin as soon as a fault occurs to notify the host. BATFET reset
voltage by the power path management circuit and is kept control is provided by nQON pin to exit ship mode or for a full
above the programmable minimum system voltage (3.5V by system reset.
default). Therefore, system power is maintained even if the
The SGM41513/SGM41513A/SGM41513D are available in a
battery is completely depleted or removed. Dynamic power
Green TQFN-4×4-24L package.

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2
SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE ORDERING PACKAGE PACKING
MODEL TEMPERATURE
DESCRIPTION NUMBER MARKING OPTION
RANGE
SGM41513
SGM41513 TQFN-4×4-24L -40℃ to +85℃ SGM41513YTQF24G/TR YTQF24 Tape and Reel, 3000
XXXXX
SGMGKA
SGM41513A TQFN-4×4-24L -40℃ to +85℃ SGM41513AYTQF24G/TR YTQF24 Tape and Reel, 3000
XXXXX
SGMGKB
SGM41513D TQFN-4×4-24L -40℃ to +85℃ SGM41513DYTQF24G/TR YTQF24 Tape and Reel, 3000
XXXXX

MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
XXXXX
Vendor Code
Trace Code
Date Code - Year

Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.

ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS

Voltage Range (with Respect to GND) Input Voltage Range, VVBUS .............................. 3.9V to 13.5V
(1)
VAC, VBUS (Converter Not Switching) ............-2V to 22V Input Current (VBUS), IIN ..................................... 3.2A (MAX)
BTST, PMID (Converter Not Switching) ........... -0.3V to 22V Output DC Current (SW), ISWOP .............................. 4A (MAX)
SW ...................................................................... -2V to 16V Battery Voltage, VBATOP ................................... 4.624V (MAX)
SW (Peak for 10ns Duration) .............................. -3V to 16V Fast Charging Current, ICHGOP ................................ 3A (MAX)
BTST to SW ....................................................... -0.3V to 6V Discharging Current (Continuous), IBATOP ............... 6A (MAX)
PSEL, nPG, D+, D- ............................................ -0.3V to 6V Ambient Temperature Range ......................... -40℃ to +85℃
REGN, TS, nCE, BAT, SYS (Converter Not Switching)
........................................................................... -0.3V to 6V OVERSTRESS CAUTION
SDA, SCL, nINT, nQON, STAT.......................... -0.3V to 6V Stresses beyond those listed in Absolute Maximum Ratings
Output Sink Current may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
STAT ............................................................................. 6mA
may affect reliability. Functional operation of the device at any
nINT .............................................................................. 6mA
conditions beyond those indicated in the Recommended
Package Thermal Resistance
Operating Conditions section is not implied.
TQFN-4×4-24L, θJA .................................................. 36℃/W
TQFN-4×4-24L, θJB .................................................. 12℃/W ESD SENSITIVITY CAUTION
TQFN-4×4-24L, θJC .................................................. 28℃/W This integrated circuit can be damaged if ESD protections are
Junction Temperature .................................................+150℃ not considered carefully. SGMICRO recommends that all
Storage Temperature Range ........................ -65℃ to +150℃ integrated circuits be handled with appropriate precautions.
Lead Temperature (Soldering, 10s) ............................+260℃ Failure to observe proper handling and installation procedures
ESD Susceptibility can cause damage. ESD damage can range from subtle
HBM ............................................................................. 3000V performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
CDM ............................................................................ 1000V
because even small parametric changes could cause the
device not to meet the published specifications.
NOTE: 1. Maximum 28V for 10 seconds.
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.

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3
SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

PIN CONFIGURATION
SGM41513 (TOP VIEW) SGM41513A (TOP VIEW)

REGN

REGN
VBUS

VBUS
BTST

BTST
PMID

PMID
SW

SW

SW

SW
24 23 22 21 20 19 24 23 22 21 20 19

VAC 1 18 GND VAC 1 18 GND

PSEL 2 17 GND D+ 2 17 GND

nPG 3 16 SYS D- 3 16 SYS

SGM41513 SGM41513A
STAT 4 15 SYS STAT 4 15 SYS

SCL 5 14 BAT SCL 5 14 BAT

SDA 6 13 BAT SDA 6 13 BAT

7 8 9 10 11 12 7 8 9 10 11 12
nINT

NC

nCE

NC

TS

nQON

nINT

NC

nCE

NC

TS

nQON
TQFN-4×4-24L TQFN-4×4-24L

SGM41513D (TOP VIEW)

REGN

BTST
PMID

SW

SW
NC

24 23 22 21 20 19

VBUS 1 18 GND

D+ 2 17 GND

D- 3 16 SYS
SGM41513D
STAT 4 15 SYS

SCL 5 14 BAT

SDA 6 13 BAT

7 8 9 10 11 12
nINT

NC

nCE

NC

TS

nQON

TQFN-4×4-24L

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

PIN DESCRIPTION
PIN
SGM SGM SGM NAME TYPE (1) FUNCTION
41513 41513A 41513D
Sense Input for DC Input Voltage (Typically from an AC/DC Adaptor). Must be
1 1 — VAC AI
connected to VBUS pin.
Power Source Selection Input. If PSEL is pulled high, the input current limit is set to
500mA (USB 2.0) and if it is pulled low, the limit is set to 2.4A (adaptor). When the
2 — — PSEL DI
I2C link to the host is established, the host can program a different input current limit
value by writing to the IINDPM[4:0] register.
Positive USB Data Line. D+/D- based USB device protocol detection and voltage of
— 2 2 D+ AIO
this pin can be set by DP_VSET[1:0].
Open-Drain Active Low Input Power Good Indicator. Use a 10kΩ pull-up to the logic
3 — — nPG DO high rail. A low state indicates a good input (UVLO < VVBUS < ACOV, and above
sleep mode threshold, ILIM > 30mA).
Negative USB Data Line. D+/D- based USB device protocol detection and voltage
— 3 3 D- AIO
of this pin can be set by DM_VSET[1:0].
Open-Drain Charge Status Output. Use a 10kΩ pull-up to the logic high rail (or an
LED + a resistor). The STAT pin acts as follows:
During charge: low (LED ON).
4 4 4 STAT DO Charge completed or charger in sleep mode: high (LED OFF).
Charge suspended (in response to a fault): 1Hz, 50% duty cycle pulses (LED
BLINKS).
The function can be disabled via EN_ICHG_MON[1:0] register.
5 5 5 SCL DI I2C Clock Signal. Use a 10kΩ pull-up to the logic high rail.
6 6 6 SDA DIO I2C Data Signal. Use a 10kΩ pull-up to the logic high rail.
Open-Drain Interrupt Output Pin. Use a 10kΩ pull-up to the logic high rail. The nINT
7 7 7 nINT DO pin is active low and sends a negative 256µs pulse to inform host about a new
charger status update or a fault.
8, 10 8, 10 8, 10, 24 NC — Internal No Connection.
Charge Enable Input Pin (Active Low). Battery charging is enabled when
9 9 9 nCE DIO
CHG_CONFIG bit is 1 and nCE pin is pulled low.
Temperature Sense Input Pin. Connect to the battery NTC thermistor that is
grounded on the other side. To program operating temperature window, it can be
biased by a resistor divider between REGN and GND. Charge suspends if TS
11 11 11 TS AI voltage goes out of the programmed range. It is recommended to use a 103AT-2
type thermistor.
If NTC or TS pin function is not needed, use a 10kΩ/10kΩ pair for the resistor
divider.
BATFET On/Off Control Pin. Use an internal pull-up to a small voltage for
maintaining the default high logic (whenever a source or battery is available). In the
ship mode, the BATFET is off. To exit ship mode and turn BATFET on, a logic low
12 12 12 nQON DI pulse with a duration of tSHIPMODE (1s TYP) can be applied to nQON. When VBUS
source is not connected, a logic low pulse with a duration of tQON_RST (10s TYP)
resets the system power (SYS) by turning BATFET off for tBATFET_RST (320ms TYP)
and then back on to provide a full power reset for system.
Battery Positive Terminal Pin. Use a 10µF capacitor between BAT and GND pins
13, 14 13, 14 13, 14 BAT P close to the device. SYS and BAT pins are internally connected by BATFET with
current sensing capability.
Connection Point to Converter Output. SYS is connected to the converter LC filter
output that powers the system. BAT to SYS internal current (power from battery to
15, 16 15, 16 15, 16 SYS P
system) is sensed. Connect a 20μF capacitor between SYS pin and GND close to
the device (in addition to COUT).
17, 18 17, 18 17, 18 GND — Ground Pin of the Device.

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

PIN DESCRIPTION (continued)

PIN
SGM SGM SGM NAME TYPE (1) FUNCTION
41513 41513A 41513D
Switching Node Output. Connect SW pin to the output inductor. Connect a 47nF
19, 20 19, 20 19, 20 SW P
bootstrap capacitor from SW pin to BTST pin.
High-side Driver Positive Supply. It is internally connected to the boost-strap diode
21 21 21 BTST P
cathode. Use a 47nF ceramic capacitor from SW pin to BTST pin.
LDO Output that Powers LSFET Driver and Internal Circuits. Internally, the REGN
pin is connected to the anode of the bootstrap diode. Place a 4.7μF (10V rating)
22 22 22 REGN P
ceramic capacitor between REGN pin and GND. It is recommended to place the
capacitor close to the REGN pin. The output is typically 4.5V to 5V.
PMID Pin. PMID is the actual higher voltage port of converter (Buck or Boost) and
is connected to the drain of the reverse blocking MOSFET (RBFET) and the drain
23 23 23 PMID P
of HSFET. Connect a 10μF ceramic capacitor from PMID pin to GND. It is the
proper point for decoupling of high frequency switching currents.
Charger Input (VIN). The internal N-channel reverse blocking MOSFET (RBFET) is
connected between VBUS and PMID pins. Connect a 1μF ceramic capacitor from
24 24 1 VBUS P
VBUS pin to GND close to the device. For SGM41513D, this pin senses the input
voltage (VAC).
Thermal Pad and Ground Reference. It is the ground reference for the device and
Exposed Exposed Exposed also the thermal pad to conduct heat from the device (not suitable for high current
— P
Pad Pad Pad return). Tie externally to the PCB ground plane (GND). Thermal vias under the pad
are needed to conduct the heat to the PCB ground planes.

NOTE:
1. AI = Analog Input, AO = Analog Output, AIO = Analog Input and Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input and Output,
P = Power.

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS
(VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise
noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Quiescent Currents
Battery Discharge Current VBAT = 4.5V, VVBUS < VVAC_UVLOZ,
IBQ_VBUS 0.1 1 µA
(BAT, SW, SYS) in Buck Mode leakage between BAT and VBUS, BATFET off
Battery Discharge Current VBAT = 4.5V, HIZ mode and BATFET_DIS = 1 or
IBQ_HIZ_BOFF 2.5 5 µA
(BAT) in Buck Mode no VBUS, I2C disabled, BATFET disabled
Battery Discharge Current VBAT = 4.5V, HIZ mode and BATFET_DIS = 0 or
IBQ_HIZ_BON 8.5 15 µA
(BAT, SW, SYS) no VBUS, I2C disabled, BATFET enabled
VVBUS = 5V, HIZ mode and BATFET_DIS = 1,
12 20
no battery
IVBUS_HIZ µA
VVBUS = 12V, HIZ mode and BATFET_DIS = 1,
Input Supply Current 38 55
no battery
(VBUS) in Buck Mode
VVBUS = 12V, VVBUS > VBAT, converter not switching 2.5 3.5
IVBUS VBAT = 3.8V, ISYS = 0A, VVBUS > VBAT, mA
2.3
VVBUS > VVAC_UVLOZ, converter switching, BATFET off
Battery Discharge Current
IBOOST VBAT = 4.2V, IVBUS = 0A, converter switching 3.3 mA
in Boost Mode
BAT Pin, VAC Pin and VBUS Pin Power-Up
VBUS Operating Range VVBUS_OP VVBUS rising 3.9 13.5 V
VBUS UVLO to Have Active I2C
(with No Battery) Seen by Sense VVAC_UVLOZ VVAC rising, TJ = +25℃ 3.2 3.4 V
VAC Pin
I2C Active Hysteresis VVAC_UVLOZ_HYS VVAC falling from above VVAC_UVLOZ 400 mV
VVAC Minimum (as One of the
VVAC_PRESENT VVAC rising, TJ = +25℃ 3.5 3.75 V
Conditions) to Turn on REGN
VVAC Hysteresis (as One of the
VVAC_PRESENT_HYS VVAC falling 400 mV
Conditions) to Turn on REGN
VVAC - VBAT, VVBUSMIN_FALL ≤ VBAT ≤ VREG, VVAC falling,
Sleep Mode Falling Threshold VSLEEP 20 60 100 mV
VBAT = 4V, TJ = +25℃
VVAC - VBAT, VVBUSMIN_FALL ≤ VBAT ≤ VREG, VVAC rising,
Sleep Mode Rising Threshold VSLEEPZ 170 225 280 mV
VBAT = 4V, TJ = +25℃
6.5V Setting OVP[1:0] = 01 6.3 6.5 6.7
VAC
Over-Voltage 10.5V Setting VVAC_OV_RISE VVAC rising OVP[1:0] = 10 10.25 10.5 10.75 V
Rising Threshold
14V Setting OVP[1:0] = 11 13.7 14 14.3
6.5V Setting OVP[1:0] = 01 100
VAC
Over-Voltage 10.5V Setting VVAC_OV_HYS VVAC falling OVP[1:0] = 10 250 mV
Hysteresis
14V Setting OVP[1:0] = 11 300
BAT Voltage to Have Active I2C
VBAT_UVLOZ VBAT rising 2.65 V
(No Source on VBUS)
VBAT_DPL_FALL VBAT falling 2.2 2.38 2.56
BAT Depletion Threshold V
VBAT_DPL_RISE VBAT rising 2.4 2.6 2.8
BAT Depletion Rising Hysteresis VBAT_DPL_HYS VBAT rising 220 mV
Bad Adapter Detection Current
IBAD_SRC VVBUS = 5V, sink current from VBUS to GND 30 mA
(Internal Current Sink)
Bad Adapter Detection (VBUS
VVBUSMIN_FALL VVBUS falling 3.7 3.8 3.9 V
Voltage Drop) Falling Threshold
Bad Adapter Detection (VBUS
VVBUSMIN_HYS 170 mV
Voltage Drop) Hysteresis

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise
noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power Path Management
VBAT +
System Regulation Voltage VSYS VBAT = 4.4V, VBAT > VSYS_MIN, BATFET_DIS = 1 V
50mV
Minimum DC System Voltage VBAT < SYS_MIN[2:0] = 101 (3.5V),
VSYS_MIN 3.6 3.7 V
Output BATFET_DIS = 1
Maximum DC System Voltage VBAT ≤ 4.4V, VBAT > VSYS_MIN = 3.5V,
VSYS_MAX 4.4 4.46 4.51 V
Output BATFET_DIS = 1
Top Reverse Blocking MOSFET
On-Resistance between VBUS RON_RBFET 30 mΩ
and PMID - Q1
Top Switching MOSFET
On-Resistance between PMID RON_HSFET VREGN = 5V 33 mΩ
and SW - Q2
Bottom Switching MOSFET
On-Resistance between SW and RON_LSFET VREGN = 5V 33 mΩ
GND - Q3
BATFET forward Voltage in
VFWD 28 mV
Supplement Mode
Battery Charger
Charge Voltage Program Range VBAT_REG_RANGE 3.856 4.624 V
Charge Voltage Step VBAT_REG_STEP Combined with VREG_FT bits 8 mV

VREG[4:0] = 01011 TJ = +25℃ 4.192 4.208 4.224

(4.208V) TJ = -40℃ to +85℃ 4.186 4.23

VREG[4:0] = 01111 TJ = +25℃ 4.333 4.35 4.367

Charge Voltage Setting VBAT_REG V
(4.350V) TJ = -40℃ to +85℃ 4.327 4.373

VREG[4:0] = 10001 TJ = +25℃ 4.383 4.4 4.417

(4.400V) TJ = -40℃ to +85℃ 4.375 4.425
VBAT_REG = 4.208V or TJ = +25℃ -0.4 0.4
Charge Voltage Setting Accuracy VBAT_REG_ACC VBAT_REG = 4.350V or %
VBAT_REG = 4.400V TJ = -40℃ to +85℃ -0.6 0.6
Charge Current Regulation
ICHG_REG_RANGE 0 3000 mA
Range
ICHG = 10mA 0.01
ICHG = 60mA 0.03 0.065 0.105

VBAT = 3.1V, ICHG = 230mA 0.155 0.24 0.335

TJ = +25℃ ICHG = 720mA 0.62 0.73 0.86
ICHG = 1.38A 1.28 1.38 1.5

Charge Current Regulation ICHG = 1.98A 1.92 1.98 2.04

ICHG_REG A
Setting ICHG = 10mA 0.01
ICHG = 60mA 0.035 0.065 0.1

VBAT = 3.8V, ICHG = 230mA 0.175 0.24 0.3

TJ = +25℃ ICHG = 720mA 0.66 0.73 0.8
ICHG = 1.38A 1.31 1.38 1.45
ICHG = 1.98A 1.92 1.98 2.04
IPRECHG[3:0] = 0001
10
(10mA)
Pre-Charge Current Regulation IPRECHG[3:0] = 0111
IPRECHG TJ = +25℃ 25 65 110 mA
Setting (60mA)
IPRECHG[3:0] = 1101
110 190 270
(180mA)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise
noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Battery LOW Falling Threshold VBATLOW_FALL ICHG = 480mA 2.83 2.95 3.07 V
Battery LOW Rising Threshold VBATLOW_RISE Change from pre-charge to fast charging 3.07 3.15 3.23 V
ICHG[5:0] > 011000 ITERM[3:0] = 0001 (10mA) 10
(300mA),
ITERM[3:0] = 0111 (60mA) 25 70 115
VBAT_REG = 4.208V,
Termination Current Regulation TJ = +25℃ ITERM[3:0] = 1101 (180mA) 130 190 255
ITERM mA
Setting ICHG[5:0] ≤ 011000 ITERM[3:0] = 0001 (10mA) 10
(300mA),
ITERM[3:0] = 0111 (60mA) 30 60 100
VBAT_REG = 4.208V,
TJ = +25℃ ITERM[3:0] = 1101 (180mA) 125 185 245
VSHORT VBAT falling 1.9 2 2.11
Battery Short Voltage V
VSHORTZ VBAT rising 2.13 2.2 2.27
Battery Short Current ISHORT VBAT < VSHORTZ, ISHORT_SET = 0 (90mA) 95 mA

Recharge Threshold below VRECHG = 0 (100mV) 85 115 145

VRECHG VBAT falling mV
VBAT_REG VRECHG = 1 (200mV) 195 225 255
System Discharge Load Current ISYS_LOAD VSYS = 4.2V 25 mA
BATFET MOSFET VBAT = 4.2V, measured from BAT pin to SYS pin,
RON_BATFET 26 31 mΩ
On-Resistance TJ = +25℃
Input Voltage and Current Regulation (DPM: Dynamic Power Management)
VINDPM_OS = 00 (4.4V) 4.36 4.4 4.44

VINDPM[3:0] = 0101, VINDPM_OS = 01 (6.4V) 6.33 6.4 6.47

Input Voltage Regulation Limit VINDPM V
TJ = +25℃ VINDPM_OS = 10 (8V) 7.91 8 8.09
VINDPM_OS = 11 (11V) 10.87 11 11.13
Input Voltage Regulation
VINDPM_ACC TJ = +25℃ -1.2 1.2 %
Accuracy
Input Voltage Regulation Limit VBAT = 4V, VINDPM = 3.9V, TJ = +25℃,
VDPM_VBAT 4.19 4.3 4.41 V
Tracking VBAT VDPM_BAT_TRACK[1:0] = 11 (300mV)
Input Voltage Regulation
VDPM_VBAT_ACC TJ = +25℃ -2.6 2.6 %
Accuracy Tracking VBAT
IINDPM[4:0] = 00100
395 590
(500mA)
IINDPM[4:0] = 01000
VVBUS = 5V, current 785 950
USB Input Current Regulation (900mA)
IINDPM pulled from SW, mA
Limit IINDPM[4:0] = 01110
TJ = +25℃ 1365 1495
(1.5A)
IINDPM[4:0] = 10011
1840 1960
(2A)
Input Current Limit during System
IIN_START 200 mA
Start-Up Sequence
BAT Pin Over-Voltage Protection
VBATOVP_RISE As percentage of VBAT rising 102.9 103.9 104.9
Battery Over-Voltage Threshold %
VBATOVP_FALL VBAT_REG, TJ = +25℃ VBAT falling 100.9 101.9 102.9
Thermal Regulation and Thermal Shutdown

Junction Temperature Regulation Temperature TREG = 1 (120℃) 120

TJUNCTION_REG ℃
Threshold increasing TREG = 0 (80℃) 80
Thermal Shutdown Rising
TSHUT Temperature increasing 150 ℃
Temperature
Thermal Shutdown Hysteresis TSHUT_HYS 30 ℃

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise
noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JEITA Thermistor Comparator (Buck Mode)
T1 (0℃) Threshold Voltage on TS Charge suspends if temperature T is below T1
72.7 73.2 73.7
Pin VT1 (T < T1), as percentage of VREGN %
T1 Falling As percentage of VREGN 71.1 71.6 72.1
Charge sets to ICHG/2 and the lower of 4.1V and VREG
T2 (10℃) Threshold 67.5 68 68.5
VT2 if T1 < T < T2, as percentage of VREGN %
T2 Falling As percentage of VREGN 66.2 66.7 67.2
T3 Rising As percentage of VREGN 45.4 45.9 46.4
VT3 Charge sets to the lower of 4.1V and VREG %
T3 (45℃) Threshold 44 44.5 45
if T3 < T < T4, as percentage of VREGN
T4 Rising As percentage of VREGN 34.9 35.4 35.9
VT4 %
T4 (60℃) Threshold Charge suspends if T > T4, as percentage of VREGN 33.6 34.1 34.6
Cold or Hot Thermistor Comparator (Boost Mode)
Cold Temperature Threshold
As percentage of VREGN (approx. -20℃ w/ 103AT) 79.5 80 80.5
(TS Pin Voltage Rising Threshold)
VBCOLD %
TS Voltage Falling
As percentage of VREGN 78.5 79 79.5
(Exit from Cold Range to Cool)
Hot Temperature Threshold
As percentage of VREGN (approx. 60℃ w/ 103AT) 30.5 31.2 31.9
(TS Pin Voltage Falling Threshold)
VBHOT %
TS Voltage Rising
As percentage of VREGN 33.7 34.4 35.1
(Exit Hot Range to Warm)
Charge Over-Current Comparator (Cycle-by-Cycle)
HSFET Cycle-by-Cycle
IHSFET_OCP TJ = +25℃ 5.5 7.2 A
Over-Current Threshold
System Overload Threshold IBATFET_OCP TJ = +25℃ 6.4 A
Charge Under-Current Comparator (Cycle-by-Cycle)
LSFET Under-Current Falling Change rectifier from synchronous mode to
ILSFET_UCP 170 mA
Threshold non-synchronous mode
PWM
Buck mode 1380 1500 1620
PWM Switching Frequency fSW Oscillator frequency, TJ = +25℃ kHz
Boost mode 1380 1500 1620
Maximum PWM Duty Cycle (1) DMAX 99 %
Boost Mode Operation
Boost Mode Regulation Voltage VOTG_REG VBAT = 3.8V, IPMID = 0A, BOOSTV[1:0] = 10 (5.15V) 5.02 5.15 5.28 V
Boost Mode Regulation Voltage
VOTG_REG_ACC VBAT = 3.8V, IPMID = 0A, BOOSTV[1:0] = 10 (5.15V) -2.6 2.6 %
Accuracy
VBAT falling, MIN_BAT_SEL = 0 2.9 3 3.07

Exit Boost Mode Due to Low VBAT rising, MIN_BAT_SEL = 0 3.1 3.2 3.3
VBATLOW_OTG V
Battery Voltage VBAT falling, MIN_BAT_SEL = 1 2.5 2.6 2.7
VBAT rising, MIN_BAT_SEL = 1 2.7 2.8 2.9
OTG Mode Maximum Output
IOTG BOOST_LIM = 1 (1.2A), TJ = +25℃ 1.13 1.43 1.73 A
Current
OTG Over-Voltage Threshold VOTG_OVP Rising threshold 5.8 6 6.2 V
HSFET Under-Current Falling Change rectifier from synchronous mode to
IOTG_HSZCP 270 mA
Threshold non-synchronous mode

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise
noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REGN LDO
VVBUS = 9V, IREGN = 40mA 4.45 4.9 5.4
REGN LDO Output Voltage VREGN V
VVBUS = 5V, IREGN = 20mA 4.7 4.85 5
Logic I/O Pin Characteristics (nCE, PSEL, SCL, SDA and nINT)
Input Low Threshold VIL 0.35 V
nCE
Input High Threshold VIH 0.9 V
Input Low Threshold PSEL, SCL, VIL 0.35 V
Input High Threshold SDA, nINT VIH 0.9 V
High-Level Leakage Current IBIAS Pull up rail 1.8V 0.1 1 µA
Logic I/O Pin Characteristics (nPG, STAT) – Open-Drain
Low-Level Output Voltage VOL Sink 5mA 0.2 V

NOTE:
1. Guaranteed by design. Not production tested.

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

TIMING REQUIREMENTS
(VVAC_UVLOZ < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise
noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VVBUS/VBAT Power-Up
VBUS OVP Reaction Time tACOV VVBUS rising above ACOV threshold to turn off Q2 0.1 µs
Wait Window for Bad Adapter Detection tBAD_SRC 30 ms
Battery Charger
Deglitch Time for Charge Termination tTERM_DGL 230 ms
Deglitch Time for Recharge tRECHG_DGL 230 ms
System Over-Current Deglitch Time to Turn
tSYSOVLD_DGL 112 µs
off Q4
Battery Over-Voltage Deglitch Time to
tBATOVP 1 µs
Disable Charge
Typical Charge Safety Timer Range tSAFETY CHG_TIMER = 1 14 16 18 h
Typical Top-Off Timer Range tTOP_OFF TOPOFF_TIMER[1:0] = 10 (30min) 30 35 40 min
nQON Timing and Ship Mode Timing
nQON Negative Pulse Low Pulse Width to
tSHIPMODE 0.9 1 1.5 s
Turn on BATFET and Exit Ship Mode
nQON Low Time to Reset BATFET tQON_RST 8 10 15 s
BATFET off Time during Full System Reset tBATFET_RST 285 320 355 ms
Wait Delay for Entering Ship Mode tSM_DLY 10 12 17 s
Digital Clock and Watchdog Timer
Watchdog Reset Time tWDT WATCHDOG[1:0] = 01, REGN LDO disabled 40 s
Digital Clock Frequency in Low Power fLPDIG REGN LDO disabled 31.25 kHz
Digital Clock Frequency fDIG REGN LDO enabled 500 kHz
2
I C Interface
SCL Clock Frequency fSCL 400 kHz

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS

Charge Efficiency vs. Charge Current OTG Efficiency vs. OTG Current
100 100
VBAT = 3.8V, L = 1μH (WURTH 74439344010), VOTG = 5.15V, L = 1μH (WURTH 74439344010),
DCR = 5.5mΩ 95 DCR = 5.5mΩ
95
Charge Efficiency (%)

OTG Efficiency (%)

90
90
85
85
80
80
75
VVBUS = 5V VBAT = 3.3V
75 70
VVBUS = 9V VBAT = 3.8V
VVBUS = 12V VBAT = 4V
70 65
0.1 0.6 1.1 1.6 2.1 2.6 3.1 0 0.2 0.4 0.6 0.8 1 1.2
Charge Current (A) OTG Current (A)

OTG Output Voltage vs. Output Current Charge Current Accuracy vs. Charge Current
6 5
4
5
Charge Current Accuracy (%)

3
OTG Output Voltage (V)

2
4
1
3 0
-1
2
-2
-3
1
-4
VBAT = 3.8V, VOTG = 5.15V VVBUS = 5V, VBAT = 4V
0 -5
0 0.2 0.4 0.6 0.8 1 1.2 0.5 1 1.5 2 2.5 3

Output Current (A) Charge Current (A)

SYS_MIN Voltage vs. Junction Temperature BAT_REG Charge Voltage vs. Junction Temperature
3.85 4.50
4.45
3.80
BAT_REG Charge Voltage (V)

4.40
SYS_MIN Voltage (V)

3.75 4.35

3.70 4.30
4.25
3.65 4.20
3.60 4.15
4.10
3.55 VBAT_REG = 4.208V
4.05
VBAT_REG = 4.350V
3.50 4.00
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (℃) Junction Temperature (℃)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Input Current Limit vs. Junction Temperature Charge Current vs. Junction Temperature
2500 2000
IINDPM = 500mA ICHG = 230mA
1800 ICHG = 720mA
IINDPM = 900mA
2000 IINDPM = 1500mA 1600 ICHG = 1380mA
Input Current Limit (mA)

Charge Current (mA)

1400
1500 1200
1000
1000 800
600
500 400
200
0 0
-40 -25 -10 5 20 35 50 65 80 95 -40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature (℃) Junction Temperature (℃)

VBUS Power-Up with Charge Disable (VBAT = 3.2V) VBUS Power-Up with Charge Enable (VBAT = 3.2V)
5V/div 5V/div

5V/div 5V/div
VBUS VBUS

REGN REGN
2V/div

2V/div
VSYS VSYS
5V/div

2A/div
PMID
IBAT
VVBUS = 5V, VBAT = 3.2V VVBUS = 5V, VBAT = 3.2V, ICHG = 2A

Time (40ms/div) Time (40ms/div)

Charge Enable Charge Disable

5V/div
5V/div

STAT
STAT
nCE
5V/div
5V/div

nCE
5V/div

SW SW
5V/div
2A/div

2A/div

IBAT
IBAT
VVBUS = 5V, VBAT = 3.2V, ICHG = 2A VVBUS = 5V, VBAT = 3.2V, ICHG = 2A

Time (10ms/div) Time (10ms/div)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

PFM Switching in Buck Mode, Charge Disabled OTG Switching (Boost Mode)

200mV/div
VSYS

5V/div
5V/div
SW SW

500mA/div
500mA/div
IL IL
VVBUS = 5V, ISYS = 50mA VBAT = 4V, ILOAD = 50mA, PFM Enable

Time (5μs/div) Time (2μs/div)

PFM Switching in Buck Mode, Charge Disabled OTG Switching (Boost Mode)
200mV/div

VSYS
5V/div

5V/div
SW
SW

1A/div
500mA/div

IL IL
VVBUS = 9V, ISYS = 50mA VBAT = 4V, ILOAD = 1A, PWM

Time (3μs/div) Time (400ns/div)

PFM Switching in Buck Mode, Charge Disabled OTG Start-Up

200mV/div

VSYS
2V/div

VPMID
5V/div

2V/div

SW

VBUS
500mA/div

5V/div

SW
IL
VVBUS = 12V, ISYS = 50mA

Time (3μs/div) Time (20ms/div)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

System Load Transient System Load Transient

5V/div

5V/div 2A/div
VSYS VSYS

IBAT IBAT

2A/div

2A/div
2A/div 2A/div
ISYS ISYS

IIN

2A/div
VVBUS = 5V, IINDPM = 1A, ICHG = 1A IIN VVBUS = 5V, IINDPM = 2A, ICHG = 1A,
VBAT = 3.7V, ISYS = 0A to 2A
VBAT = 3.7V, ISYS = 0A to 4A

Time (2ms/div) Time (2ms/div)

System Load Transient System Load Transient

VSYS VSYS
5V/div

5V/div
IBAT
IBAT
2A/div

2A/div
2A/div

2A/div
ISYS ISYS
2A/div

2A/div
IIN VVBUS = 5V, IINDPM = 1A, ICHG = 2A IIN VVBUS = 5V, IINDPM = 1A, ICHG = 2A
VBAT = 3.7V, ISYS = 0A to 2A VBAT = 3.7V, ISYS = 0A to 4A

Time (2ms/div) Time (2ms/div)

System Load Transient System Load Transient

VSYS VSYS
5V/div

5V/div

IBAT IBAT
2A/div

2A/div
2A/div

2A/div

ISYS ISYS

IIN IIN
2A/div

2A/div

VVBUS = 5V, IINDPM = 2A, ICHG = 2A VVBUS = 5V, IINDPM = 2A, ICHG = 2A
VBAT = 3.7V, ISYS = 0A to 2A VBAT = 3.7V, ISYS = 0A to 4A

Time (2ms/div) Time (2ms/div)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

PWM Switching in Buck Mode (L = 1µH) PWM Switching in Buck Mode (L = 1μH)

5V/div
5V/div
SW SW

2A/div

2A/div
IL IL

VVBUS = 5V, ICHG = 1980mA, Charge Enable VVBUS = 12V, ICHG = 1980mA, Charge Enable

Time (1μs/div) Time (1μs/div)

VINDPM Tracking Battery Voltage

2V/div

VBUS
2V/div

VBAT
1A/div

IIN

Time (1s/div)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

TYPICAL APPLICATION CIRCUITS

Input OTG VAC PMID
3.9V to 13.5V 5V at 1.2A
VBUS 10µF

1µF
1µH
VSYS
SW
47nF 10µF × 2
BTST
PHY PSEL REGN
SYS SYS
4.7µF

GND
2.2kΩ 2.2kΩ
SYS
nPG ICHG = 3A
VREF
BAT
STAT
10µF

10kΩ 10kΩ 10kΩ

SGM41513
Host
51pF
REGN
SDA
47Ω
SCL
5.23kΩ
nINT
nCE TS
nQON
Optional 30.1kΩ 10kΩ

Figure 1. SGM41513 Typical Application Circuit

Input OTG VAC (1) PMID

3.9V to 13.5V 5V at 1.2A
10µF
VBUS
1µF 1µH
VSYS
SW
47nF 10µF × 2
BTST
D+
USB REGN
D- 4.7µF

SYS
GND

SYS
ICHG = 3A
VREF 2.2kΩ BAT

STAT 10µF

SGM41513A
Host 10kΩ 10kΩ 10kΩ SGM41513D
51pF
REGN
SDA
47Ω SCL
5.23kΩ
nINT
nCE TS

nQON 30.1kΩ 10kΩ

Optional

NOTE:
1. Only for SGM41513A.

Figure 2. SGM41513A/SGM41513D Typical Application Circuit

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

FUNCTIONAL BLOCK DIAGRAM

VBUS PMID
RBFET (Q1)

REGN REGN
VAC Q1 LDO
(SGM41513A/ Control
SGM41513D Only)

BTST

Protections:
Voltage & Current
OVP
Sensing
UVP
&
OCP
DAC Reference
UCP
OTP HSFET (Q2)
D+
(SGM41513A/ SW
SGM41513D Only) Input Converter
D- Source Control REGN
Detection

PSEL
LSFET (Q3)
(SGM41513 Only)
GND

nPG Digital SYS

Control
(SGM41513 Only) ICHG

nINT Q4 Gate
BATFET (Q4)
Control

BAT

STAT

VPULL-UP

nQON

nCE

SDA Battery
I2C JEITA Temperature TS
Interface Control Sensing
SCL

SGM41513
SGM41513A
SGM41513D

Figure 3. Block Diagram

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION
The SGM41513/SGM41513A/SGM41513D are power Power-Up from Battery Only (No Input
management and charger devices for applications such as Source)
cell phones, tablets and wearables that use high capacity When only the battery is presented as a source and its
single-cell Li-Ion or Li-polymer batteries. The SGM41513/ voltage is above depletion threshold (VBAT_DPL_RISE), the
SGM41513A/SGM41513D can accommodate a wide range BATFET turns on and connects the battery to the system.
of input sources including USB, wall adapter and car chargers. The quiescent current is minimum because the REGN LDO
It is optimized for 5V input (USB voltage) but is capable to remains off. Conduction losses are also low due to small
operate with input voltages from 3.9V up to 13.5V. It also RDSON of BATFET. Low losses help to extend the battery run
supports JEITA profile for battery charging safety at high or time.
low temperatures. Automatic power path selection to power
The discharge current through BATFET is continuously
the system (SYS) from the input source (VBUS), battery
monitored. In the supplement mode, if a system overload (or
(BAT), or both, is another feature of the device. Battery
short) occurs (IBAT > IBATFET_OCP), the BATFET is turned off
charge current is programmable and can reach to a maximum
immediately and BATFET_DIS bit is set to 1. The BATFET
of 3A (charge). In the Boost mode, the battery voltage is
will not enable until the input source is applied or one of the
boosted to power the VBUS pin (1.2A MAX) when it is a
BATFET Enable Mode (Exit Ship Mode) methods (explained
power receiving node (USB OTG) that is typically regulated to
later) is used to activate the BATFET.
5.15V.

The device may operate in several different modes: Power-Up Process from the Input Power
In HIZ mode, the reverse blocking FET (Q1), internal REGN Source
LDO, converter switches and some other parts of the internal Upon connection of an input source (VBUS), its voltage
circuit remain off to save the battery while it is supplying DC sensed from VAC pin is checked to turn on the internal REGN
power to the system through BATFET. LDO regulator and the bias circuits (no matter whether the
battery is present or not). The input current limit is determined
In the sleep mode, the switching is stopped. The charger and set before the Buck converter is started. The sequences
goes to the sleep mode when the input source voltage (VVAC) of actions when VBUS as input source is powered up are:
is not high enough for charging the battery. In other words,
VVAC is smaller than VBAT + VSLEEP (where VSLEEP is a small 1. REGN LDO power-up.
threshold) and Buck converter is not able to charge, even at 2. Poor power source detection (qualification).
its maximum duty cycle. The Boost may also go to the sleep 3. Input power source type detection. (Based on D+/D- or
mode if similar issue happens in the reverse direction (when PSEL input. It is used to set the default input current limit
VVAC is almost equal to or smaller than VBAT). (IINDPM[4:0]).)
4. Setting of the input voltage limit threshold (VINDPM
In supplement mode, the input source power is not enough to threshold).
supply system demanded power and the battery assists by 5. DC/DC converter power-up.
discharging to the system in parallel, and providing the deficit.
Details of the power-up steps are explained in the following
Power-On Reset (POR) sections.
The internal circuit of the device is powered from the greater
voltage between VVBUS and VBAT. When the voltage of the
selected source goes above its UVLO level (VVBUS >
VVBUS_UVLOZ or VBAT > VBAT_UVLOZ), a POR happens and
activates the sleep comparator, battery depletion comparator
2
and BATFET driver. Upon activation, the I C interface will
also be ready for communication and all registers reset to
their default values.

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

REGN LDO Power-Up completed. Some registers and pins are also updated as
The REGN low dropout regulator powers the internal bias detailed below:
circuits, HSFET and LSFET gate drivers and TS rail
1. Input current limit register (the value in the IINDPM[4:0]) is
(thermistor pin). The STAT pin can also be pulled up to REGN.
changed to set current limit.
The REGN enables when the following 2 conditions are
2. PG_STAT (power good) bit is set.
satisfied and remain valid for a 220ms delay time, otherwise
3. VBUS_STAT[2:0] register is updated to indicate USB or
the device stays in high impedance mode (HIZ) with REGN
adaptor input source types.
LDO off.
The input current is always limited by the IINDPM[4:0] register
1. VVAC > VVAC_PRESENT.
and the limit can be updated by the host if needed.
2. VVAC > VBAT + VSLEEPZ (in Buck mode) or VVBUS < VBAT +
VSLEEP (in Boost mode).
Input Current Limit by PSEL (SGM41513)
In HIZ state, the quiescent current drawn from VBUS is very PSEL pin interfaces with USB physical layer (PHY) for input
small (less than IVBUS_HIZ). System is only powered by the current limit setting. The USB PHY device output is used to
battery in HIZ mode. detect if the input is a USB host or a charging port. In the
host-control mode, the host must enable IINDET_EN bit for
Poor Power Source Detection (Qualification) reading the PSEL value and updating the IINDPM[4:0]. In the
When REGN LDO is powered, the input source (adaptor) is default mode, IINDPM[4:0] is updated automatically by PSEL
checked for its type and current capacity. To start the Buck value in real-time as given in Table 1.
converter, the input (VBUS) must meet the following
conditions: Table 1. Input Current Limit Setting and Status
Input Current
1. VVBUS < VVAC_OV. Input Detection PSEL Pin VBUS_STAT[2:0]
Limit (ILIM)
2. VVBUS > VVBUSMIN_RISE during tBAD_SRC test period (30ms TYP) USB Host SDP High 500mA 001
in which the IBAD_SRC (30mA TYP) current is pulled from Adapter Low 2400mA 010
VBUS.

If the test is failed, the conditions are repeatedly checked Input Current Limit by D+/D- Detection
every two seconds. As soon as the input source passes (SGM41513A/SGM41513D)
qualification, the VBUS_GD bit in status register is set to 1 The SGM41513A/SGM41513D integrate a D+/D- based input
and a pulse is sent to the nINT pin to inform the host. Type source detection to set the input current limit when VBUS is
detection will start as next step. plug-in. When input source is plugged in, the SGM41513A/
SGM41513D start USB BC1.2 detection and sets the
Input Power Source Type Detection SDP/DCP related input current limit. And if the data contact
The input source detection will run through the D+/D- lines or detection timer expires, the non-standard adapter detection
the PSEL pin while REGN LDO is powered and after the starts and then sets the input current limit. Please refer to
VBUS_GD bit is set. The SGM41513D can detect the input Table 2 and Table 3.
source types which include SDP/DCP and non-standard
adapter through D+/D- pins following USB BC1.2 Force Detection of Input Current Limit
specification. The input current limit of the SGM41513 is set The host can set IINDET_EN bit to 1 in host mode to force the
based on the state of PSEL pin. A pulse is sent to nINT pin to device to run. And the IINDET_EN bit returns to 0 by itself and
inform the host when the input source type detection is input result is updated after the detection is completed.

Table 2. Non-Standard Adapter Detection

Non-Standard Adapter D+ Threshold D- Threshold Input Current Limit (A)
Divider 1 VD+ within V2P7 VD- within V2P0 2.1
Divider 2 VD+ within V1P2 VD- within V1P2 2
Divider 3 VD+ within V2P0 VD- within V2P7 1
Divider 4 VD+ within V2P7 VD- within V2P7 2.4

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Table 3. Input Current Limit Setting from D+/D- Detection The BATFET remains on to charge the battery if the battery
D+/D- Detection Input Current Limit (IINLIM) charging function is enabled, otherwise BATFET turns off.
USB SDP (USB500) 500mA When converter operates for battery charging, it acts as an
USB CDP 1.5A efficient, fixed frequency synchronous Buck converter
USB DCP 2.4A regardless of the input/output voltages and currents. However,
Divider 1 2.1A it is capable to switch to PFM mode at light load when
Divider 2 2A
charging is disabled or when the detected battery voltage is
less than minimum system voltage setting. PFM operation
Divider 3 1A
can be enabled or prevented in either Buck or Boost mode
Divider 4 2.4A
using the PFM_DIS bit.
Unknown 5V Adapter 500mA
Boost Mode
D+/D- Output Voltage Setting (SGM41513A/SGM41513D) The SGM41513/SGM41513A/SGM41513D support USB
The host can set D+/D- output voltages by DP_VSET[1:0] On-The-Go. When a load device is connected to the USB port,
and DM_VSET[1:0] to HIZ, 0V, 0.6V or 3.3V. When BC1.2 the converter can operate as a step-up synchronous
detection runs, these bits are ignored. converter (Boost mode) with 1.5MHz switching frequency to
supply power from the battery to that load. The 500mA USB
Setting of the Input Voltage Limit Threshold OTG output current limit requirement is achieved by
(VINDPM Threshold) programming, however the Boost converter can deliver 1.2A
A wide voltage range (3.9V to 5.4V, 5.9V to 9V, 10.5V to 12V) to the output (default limit). Converter will be set to Boost
is supported for the input voltage limit setting in VINDPM[3:0] mode if at least 30ms is passed from enabling this mode
and VINDPM_OS[1:0]. 4.5V is the default for USB. (OTG_CONFIG bit = 1) and the following conditions are
satisfied:
The device supports dynamic tracking of the battery voltage
(VINDPM). VDPM_BAT_TRACK[1:0] bits can be used to 1. VBAT > VBATLOW_OTG.
enable tracking (00 to disable tracking) and set the tracking 2. VVBUS < VBAT + VSLEEP (in sleep mode).
offset value. When the tracking is enabled, the input voltage 3. Acceptable voltage range at TS pin (VBHOT < VTS < VBCOLD).
limit will be set to the larger value between the VINDPM[3:0] and
The output voltage is set to VVBUS = 5.15V and is maintained
VBAT + VDPM_BAT_TRACK[1:0]. The VDPM_BAT_TRACK[1:0]
as long as VBAT is above VBATLOW_OTG. The output current can
tracking offset can be set to 200mV, 250mV or 300mV. And
reach up to the programmed value by BOOST_LIM bit (0.5A
this function only takes effect when VINDPM_OS[1:0] = 00.
or 1.2A). The VBUS_STAT[2:0] status register bits are set to
111 in Boost mode (OTG).
DC/DC Converter Power-Up
The 1.5MHz switching converter composed of LSFET and To minimize the output overshoot in Boost mode, the device
HSFET is enabled, which can start switching when the input starts with PFM first and then switches to PWM. As stated
current limit is set. Converter is initiated with a soft-start when before, PFM can be avoided by using PFM_DIS bit in Buck
the system voltage is ramped up. The input current is limited and Boost modes.
to 200mA or IINDPM[4:0], whichever is smaller, if SYS
voltage is less than 2.2V, otherwise the limit is set to
IINDPM[4:0].

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Host Mode and Default Mode Operation Battery Charging Management
with Watchdog Timer The SGM41513/SGM41513A/SGM41513D are designed for
After a power-on reset (POR), the device starts in default charging single-cell Li-Ion or Li-poly batteries with a charge
mode (standalone) with all registers reset as if the watchdog current up to 3A (MAX). The battery connection switch
timer is expired. When the host is in sleep mode or there is no (BATFET) is in the charge or discharge current path features
host, the device stays in the default mode in which the low on-resistance (26mΩ) to allow high efficiency and low
SGM41513/SGM41513A/SGM41513D operate like an voltage drop.
autonomous charger. The battery is charged for 16 hours
(default value for the fast charging safety timer). Then the Charging Cycle in Autonomous Mode
charge stops while Buck converter continues to operate to Charging is enabled if CHG_CONFIG = 1 and nCE pin is
power the system load. In this mode, WATCHDOG_FAULT pulled low. In default mode, the SGM41513/SGM41513A/
bit is high. SGM41513D run a charge cycle with the default parameters
itemized in Table 4. At any moment, the host can be
Most of the flexibility features of the SGM41513/SGM41513A/
controlled by changing to host mode.
SGM41513D become available in the host mode when the
2
device is controlled by a host with I C. By setting the Table 4. Charging Parameter Default Setting
WD_RST bit to 1, the charger mode changes from default
SGM41513/SGM41513A/
mode to host mode. In this mode the WATCHDOG_FAULT Default Mode
SGM41513D
bit is low and all device parameters can be programmed by
Charging Voltage (VREG) 4.208V
the host. To prevent device watchdog from reset that results
Charging Current (ICHG) 1980mA
in going back to default mode, the host must disable the
Pre-Charge Current (IPRECHG) 120mA
watchdog timer by setting WATCHDOG[1:0] = 00, or it must
consistently reset the watchdog timer before expiry by writing 1 Termination Current (ITERM) 120mA
to WD_RST to prevent WATCHDOG_FAULT bit from being set. Temperature Profile JEITA
Every time a 1 is written to the WD_RST, the watchdog timer Safety Timer 16h
will restart counting. Therefore, it should be reset again before
overflow (expiry) to keep the device in the host mode. If the
watchdog timer expires (WATCHDOG_FAULT bit = 1), the
device returns to default mode and all registers are reset to
their default values except for IINDPM[4:0], VINDPM[3:0],
VINDPM_OS[1:0], BATFET_DLY and BATFET_DIS bits that
keep their values unchanged.

POR
Watchdog Timer Expired
Reset Registers Start
I2C Interface Enabled Watchdog Timer

Y
I2C Write?
Host Mode
Host Programs Registers
N

Default Mode
Reset Watchdog Timer
Reset Selective Registers Y
WD_RST Bit = 1?

N Y N
I2C Write?

Y N
Watchdog Timer
Expired?

Figure 4. Watchdog Timer Flow Chart

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Start a New Charging Cycle The CHRG_STAT[1:0] status register reports the present
If the converter can start switching and all the following charging phase and status by two bits: 00 = charging disabled,
conditions are satisfied, a new charge cycle starts: 01 = in pre-charge, 10 = in fast charging (constant current mode
or constant voltage mode) and 11 = charging completed.
• NTC temperature fault is not asserted (TS pin).
• Safety timer fault is not asserted. A negative pulse is sent on nINT pin to inform the host when a
• BATFET is not forced off. (BATFET_DIS bit = 0). charging cycle is completed.
• Charging enabled (3 conditions: CHG_CONFIG bit = 1,
In addition, the output status of STAT pin can be set by
ICHG[5:0] register is not 0mA and nCE pin is low).
STAT_SET[1:0] bits, 00 = LED off (HIZ), 01 = LED on (low),
• Battery voltage is below the programmed full charge level
10 = LED blinking at 1s on 1s off, 11 = LED blinking at 1s on
(VREG).
3s off. This tow bits only take effect when
A new charge cycle starts automatically if battery voltage falls EN_ICHG_MON[1:0] = 01.
below the recharge threshold level (VREG - 100mV or VREG -
200mV configured by VRECHG bit). Also, if the charge cycle Battery Charging Profile
is completed, a new charging cycle can be initiated by The SGM41513/SGM41513A/SGM41513D feature full
toggling of the nCE pin or CHG_CONFIG bit. battery charging profile with five phases. In the beginning of
the cycle, the battery voltage (VBAT) is tested and appropriate
Normally a charge cycle terminates when the charge voltage
current and voltage regulation levels are selected as shown in
is above the recharge threshold level and the charging
Table 5. Depending on the detected status of the battery, the
current falls below the termination threshold if the device is
proper phase is selected to start or for continuation of the
not in thermal regulation or Dynamic Power Management
charging cycle. The phases are trickle charge (VBAT < 2.2V),
(DPM) mode.
pre-charge, fast-charge (constant current and constant
voltage) and optional top-off trickle charge.
Charge Status Report
STAT is an open-drain output pin that reports the status of Note that in the DPM or thermal regulation modes, normal
charge and can drive an LED for indication: a low indicates charging functions are temporarily modified: The charge
charging is in progress, a high shows charging is completed current will be less than the value in the register; termination
or disabled and alternating low/high (blinking) show a is disabled, and the charging safety timer is slowed down by
charging fault. The STAT may be disabled (keep the open counting at half clock rate.
drain switch off) by setting EN_ICHG_MON[1:0] = 11.
Table 5. Charging Current Setting Based on VBAT
VBAT Voltage Selected Charging Current Default Value in the Register CHRG_STAT[1:0]
< 2.2V ISHORT 90mA 01
2.2V to 3V IPRECHG 120mA 01
> 3V ICHG 1980mA 10

Regulation Voltage
VREG[4:0]
Battery Voltage
Charge Current
ICHG[5:0]

Charge Current

VBATLOW (3V)

VSHORTZ (2.2V)

IPRECHG[3:0]

ITERM[3:0]
ISHORT
Trickle Charge Pre-charge Fast Charge and Voltage Regulation
Top-Off Timer Safety Timer
(Optional) Expiration

Figure 5. Battery Charging Profile

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Charge Termination can protect the battery based on JEITA guidelines. There is
A charge cycle is terminated when the battery voltage is no battery temperature protection when battery is discharging
higher than the recharge threshold and the charge current to the system (either boosting or not charging).
falls below the programmed termination current. Unless there
is a high power demand for system and it needs to operate in Compliance with JEITA Guideline
supplement mode, the BATFET turns off at the end of the JEITA guideline (April 20, 2007 release) is implemented in the
charge cycle. Even after termination, the Buck converter device for safe charging of the Li-Ion battery. JEITA highlights
operates continuously to supply the system. the considerations and limits that should to be considered for
charging at cold or hot battery temperatures. High charge
CHRG_STAT[1:0] bits are set to 11 and a negative pulse is
current and voltage must be avoided outside normal
sent to nINT pint after termination.
operating temperatures (typically 0 ℃ and 60 ℃ ). This
If the charger is regulating input current, input voltage or functionality can be disabled if not needed. Four
junction temperature instead of charge current, termination temperatures levels are defined by JEITA from T1 (minimum)
will be temporarily prevented. EN_TERM bit is termination to T4 (maximum). Outside this range, charging should be
control bit and can be set to 0 to disable termination before it stopped. The corresponding voltages sensed by NTC are
happens. named VT1 to VT4. Due to the sensor negative resistance, a
higher temperature results in a lower voltage on TS pin. The
At low termination currents (60mA TYP), the offset in the
battery cool range is between T1 - T2 and the warm range is
internal comparator may give rise to a higher (+10mA to
between T3 - T4. Charge must be limited in the cool and
+20mA) actual termination current. A delay in termination can
warm ranges.
be added (optional) as a compensation for comparator offset
using a programmable top-off timer. During the delay, One of the conditions for starting a charge cycle is having the
constant voltage charge phase continues and gives the falling TS voltage within VT1 to VT4 window limits. If during the
charge current a chance to drop closer to the programmed charge, battery gets too cold or too hot and TS voltage
value. The top-off delay timer has the same restrictions of the exceeds the T1 - T4 limits, charging is suspended (zero
safety timer. As an example, if under some conditions the charge current) and the controller waits for the battery
safety timer is suspended, the top-off timer will also be temperature to come back within the T1 to T4 window.
suspended or if the safety timer is slowed down, the
JEITA recommends reducing charge current to 1/2 of fast
termination timer will also be slowed down. The
charging current or lower at cool temperatures (T1 - T2). For
TOPOFF_ACTIVE bit reports the active/not active status of
warmer temperature (within T3 - T4 range), charge voltage is
the top-off timer. The CHRG_STAT[1:0] and
recommended to be kept below 4.1V.
TOPOFF_ACTIVE bits can be read to find status of the
termination. The SGM41513/SGM41513A/SGM41513D exceed the
JEITA requirement by its flexible charge parameter settings.
Any of the following events resets the top-off timer:
At warm temperature range (T3 - T4), the charge voltage is
1. Disable to enable transition of nCE (charge enable). set to VREG and 4.1V when JEITA_VSET_H = 0, the charge
2. A low to high change in the status of termination. voltage is set to VREG when JEITA_VSET_H = 1, and the
3. Set REG_RST bit to 1. charge current can be reduced down to 0%, 20% or 50% of
fast charging current by the JEITA_ISET_H[1:0] bits. At cool
The setting of the top-off timer is applied at the time of
temperatures (T1 - T2), the current setting can be reduced
termination detection and unless a new charge cycle is
down to 50% or 20% of fast charging current selectable by
started, modifying the top-off timer parameters after
the JEITA_ISET_L bit when JEITA_ISET_L_EN = 1, and the
termination has no effect. A negative pulse is sent to nINT
charge voltage is set to VREG when JEITA_VSET_L = 0, the
when top-off timer is started or ended.
charge voltage is set to the lower of VREG and 4.1V when
JEITA_VSET_L = 1. Additional, the cool threshold T2 and
Temperature Qualification
warm threshold T3 can be changed through JEITA_VT2 [1:0]
The charging current and voltage of the battery must be
and JEITA_VT3 [1:0], and the charge current can be disabled
limited when battery is cold or hot. A thermistor input for
by setting JEITA_ISET_L_EN = 0.
battery temperature monitoring is included in the device that

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

SGM41513
SGM41513A VREGN
SGM41513D Boost Disabled

Temperature Increasing
BAT VBCOLD
10µF (-20℃)
REGN
4.7µF

VTS
Boost Enabled

RT1
VBHOT
TS Li-Ion (60℃)
Cell
NTC
RT2 Boost Disabled
10kΩ@25℃

AGND

Figure 6. Battery Thermistor Connection and Bias Figure 7. TS Pin Thermistor Temperature Window
Network Settings in Boost Mode

A 103AT-2 type thermistor is recommended to use for the

Safety Timer
SGM41513/SGM41513A/SGM41513D. Other thermistors
Abnormal battery conditions may result in prolonged charge
may be used and bias network (see Figure 6) can be
cycles. An internal safety timer is considered to stop charging
calculated based on the following equations:
in such conditions. If the safety time is expired,
 1 1  CHRG_FAULT[1:0] bits are set to 11 and a negative pulse is
VREGN × RTHCOLD × RTHHOT ×  −  (1)
 VT1 VT 4  sent to nINT pin. By default, the charge time limit is 2 hours if
RT2 =
V  V  the battery voltage does not rise above VBATLOW threshold.
RTHHOT ×  REGN − 1 − RTHCOLD ×  REGN − 1
V
 T4  V
 T1  And it is 16 hours if it goes above VBATLOW. This feature is
optional and can be disabled by clearing EN_TIMER bit. The
  V REGN  
16 hours limit can also be reduced to 7 hours by clearing
  V  − 1 (2)
 T1  
RT1 =  CHG_TIMER bit.
 1   1 
 +  The safety timer counts at half clock rate when charger is
 RT2   RTHCOLD 
running under input voltage regulation, input current
where VT1, VT4 and VREGN are characteristics of the device regulation, JEITA cool or thermal regulation, because in these
and RTHCOLD and RTHHOT are thermistor resistances (RTH) at conditions, the actual charge current is likely to be less than
desired T1 (Cold) and T4 (Hot) temperatures. Select TCOLD = the register setting. As an example, if the safety timer is set to
0℃ and THOT = 60℃ for Li-Ion or Li-polymer batteries. For a 7 hours and the charger is regulating the input current
103AT-2 type thermistor RTHCOLD = 27.28kΩ and RTHHOT = (IINDPM_STAT bit = 1) in the whole charging cycle, the
3.02kΩ, the calculation results are: RT1 = 5.23kΩ and RT2 = actual safety time will be 16 hours. Clearing the TMR2X_EN
30.1kΩ. bit will disable the half clock rate feature.

The safety timer is paused if a fault occurs and charging is

Boost Mode Temperature Monitoring (Battery
suspended. It will resume once the fault condition is removed.
Discharge)
If charging cycle is stopped by a restart or by toggling nCE pin
The device is capable to monitor the battery temperature for
or CHG_CONFIG bit, the timer resets and restarts a new
safety during the Boost mode. The temperature must remain
timing.
within the VBCOLD to VBHOT thresholds, otherwise the Boost
mode will be suspended and VBUS_STAT[2:0] bits are set to
000. Moreover, NTC_FAULT[2:0] bits are updated to report
Boost mode cold or hot condition. Once the temperature
returns within the right window, the Boost mode is resumed
and NTC_FAULT[2:0] bits are cleared to 000 (normal).

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Narrow Voltage DC (NVDC) Design in SGM41513/SGM41513A/SGM41513D Dynamic
SGM41513/SGM41513A/SGM41513D Power Management (DPM)
The SGM41513/SGM41513A/SGM41513D feature an NVDC The SGM41513/SGM41513A/SGM41513D feature a
design using the BATFET that connects the system and dynamic power management (DPM). To implement DPM, the
battery. By using the linear region of the BATFET, the charger device always monitors the input current and voltage to
regulates the system bus voltage (SYS pin) above the regulate power demand from the source and avoid input
minimum setting using Buck converter even if the battery adapter overloading or to meet the maximum current limits
voltage is very low. MOSFET linear mode allows for the large specified in the USB specs. Overloading an input power
voltage difference between SYS and BAT pins to appear as source may result in either the voltage tending to fall below
VDS across the switch while conducting and charging battery. the input voltage limit (VINDPM) or the current trying to exceed
SYS_MIN[2:0] register sets the minimum system voltage the input current limit (IINDPM). With DPM, the device keeps the
(default 3.5V). If the system is in minimum system voltage VSYS regulated to its minimum setting by reducing the
regulation, VSYS_STAT bit is set. battery charge current adequately such that the input
parameter (voltage or current) does not exceed the limit. In
The BATFET operates in linear region when the battery
other words, charge current is reduces to satisfy IIN ≤ IINDPM or
voltage is lower than the minimum system voltage. The
VIN ≥ VINDPM whichever occurs first. DPM can be either an IIN
system voltage is regulated to 180mV (TYP) above the
type (IINDPM) or VIN type (VINDPM) depending on which limit
minimum system voltage setting. The battery gradually gets
is reached.
charged and its voltage rises above the minimum system
voltage and lets BATFET to change from linear mode to fully Changing to the supplement mode may be required if the
turned-on switch such that the voltage difference between the charge current is decreased and reached to zero while the
system and battery is the small VDS of fully on BATFET. input is still overloaded. In this case, the charger reduces the
system voltage below the battery voltage to allow operation in
The system voltage is always regulated to 50mV (TYP) above
the supplement mode and provide a portion of system power
the battery voltage if:
demand from the battery through the BATFET.
1. The charging is terminated.
The IINDPM_STAT or VINDPM_STAT status bits are set
2. Charging is disabled and the battery voltage is above the
during an IINDPM or VINDPM respectively. Figure 9
minimum system voltage setting.
summarizes the DPM behavior (IINDPM type) for a design
4.5 example with a 9V/1.2A adapter, 3.2V battery, 2.8A charge
current setting and 3.4V minimum system voltage setting.
4.3
Voltage
4.1
System Voltage (V)

9V VBUS
3.9
VSYS
3.7 3.6V
3.4V
3.2V VBAT
3.5 3.18V
Charge Enabled
3.3 Charge Disabled
Minimum System Voltage Current
3.1
4A
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
3.2A ICHG
Battery Voltage (V)
2.8A ISYS
Figure 8. System Voltage vs. Battery Voltage
1.2A IIN
1.0A
0.5A

-0.6A
DPM DPM
Supplement

Figure 9. DPM Behavior Plot

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Battery Supplement Mode Exit Ship Mode (BATFET Enable)
If the system voltage drops below the battery voltage, the To exit the ship mode and enable the BATFET one of the
BATFET gradually starts to turn on. The threshold margin is following can be applied:
180mV if VSYS_MIN setting is less than VBAT and 45mV if
With no input power (no operating VBUS):
VSYS_MIN setting is larger than VBAT. At low discharge currents,
the BATFET gate voltage is regulated (RDS modulation) such 1. Connect the adapter to the input with a valid voltage to the
that the BATFET VDS stays at 30mV. At higher currents, the VBUS input.
BATFET will turn fully on (reaching its lowest RDSON). From 2. Pull nQON pin from logic high to low to enable BATFET, for
this point, increasing the discharge current will linearly example, by shorting nQON to GND. The negative pulse
increase the BATFET VDS (determined by RDSON × ID). Using width should be at least a tSHIPMODE (1s TYP) for deglitching.
the MOSFET linear mode at lower currents prevents swinging
With the chip already powered by VBUS:
oscillation of entering and exiting the supplement mode. 2
3. Clear BATFET_DIS bit using host and I C.
BATFET gate regulation V-I characteristics is shown in Figure 4. Set REG_RST bit to 1 to reset all registers.
10. If the battery voltage falls below its minimum depletion, 5. Apply a negative pulse to nQON (same as 2).
the BATFET turns off and exits supplement mode.
4.5 Full System Reset with BATFET Using nQON
When the input source is not present, the BATFET can act as
4.0
a load on/off switch between the system and battery. This
3.5 feature can be used to apply a power-on reset to the system.
3.0 Host can toggle BATFET_DIS bit to cycle power off/on and
Current (A)

2.5 reset the system. A push-button connected to nQON pin or a

negative pulse can also be used to manually force a system
2.0
power cycle when BATFET is ON (BATFET_DIS bit = 0). For
1.5 this function, a negative logic pulse with a minimum width of
1.0 tQON_RST (10s TYP) must be applied to the nQON pin that
0.5 results in a temporary BATFET turn off for tBATFET_RST (320ms
TYP) that automatically turns on afterward. This functionality
0.0
20 40 60 80 100 120 140 can be disabled by setting BATFET_RST_EN bit to 0.
VBAT-SYS (mV)
In summary the nQON pin controls BATFET and system reset
Figure 10. BATFET Gate Regulation V-I Curve
in two different ways:

1. Enable BATFET: Applying an nQON logic high to low

BATFET Control for System Power Reset transition with longer than tSHIPMODE deglitch time (negative
and Ship Mode pulse) turns on BATFET to exit ship mode (Figure 11 left). HIZ
Ship Mode (BATFET Disable) is also enabled (EN_HIZ = 1) when exiting shipping mode.
Ship mode is usually used when the system is stored or in After exiting shipping mode, the host can disable HIZ (EN_HIZ
idle state for a long time or is in shipping. In such conditions, it = 0). OTG cannot be enabled until HIZ is disabled
is better to completely disconnect battery and make system (OTG_CONFIG = 1).
voltage zero to minimize the leakage and extend the battery
life. To enter ship mode, the BATFET has to be forced off by 2. Reset BATFET: By applying a logic low for a duration of at
setting BATFET_DIS bit. The BATFET turns off immediately if least tQON_RST to nQON pin while VBUS is not powered and
BATFET_DLY bit is 0, or turns off after a tSM_DLY delay (12 BATFET is allowed to turn on (BATFET_DIS bit = 0), the
seconds) if BATFET_DLY is set. BATFET turns off for tBATFET_RST and then it is re-enabled
resulting in a system power-on reset. This function can be
disabled by clearing BATFET_RST_EN bit (Figure 11 right).

A typical push button circuit for nQON is given in Figure 12.

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Press Push Button Press Push Button

nQON

tSHIPMODE tQON_RST
tBATFET_RST

BATFET
Status

BATFET off due to I2C BATFET on BATFET on

or system overload BATFET off
Turn on BATFET Reset BATFET
When BATFET_DIS = 1 or SLEEPZ = 1 When BATFET_DIS = 0 and SLEEPZ = 0

Figure 11. nQON Enable and Reset BATFET Timing

SYS

BATFET (Q4)
Control BAT

VPULL-UP

nQON

Figure 12. nQON Push Button Circuit

Status Outputs Pins (nPG, STAT and nINT) Charge Status (STAT Pin)
Charging state is indicated with the open-drain STAT pin as
Power Good Indication (nPG Pin and PG_STAT Bit)
explained in Table 6. This pin is able to drive an LED (see
When a good input source is connected to VBUS and input
Figure 1). The functionality of the STAT pin is disabled if the
type is detected, the PG_STAT status bit goes high and the
EN_ICHG_MON[1:0] bits are set to 11.
nPG pin goes low. A good input source is detected if all
Table 6. STAT Pin Function
following conditions on VVBUS are satisfied and input type
detection is completed: Charging State STAT Indicator
Charging battery (or recharge) Low (LED ON)
• VVBUS is in the operating range: VVBUS_UVLOZ < VVBUS < VVAC_OV.
• Device is not in sleep mode: VVBUS > VBAT + VSLEEP. Charging completed High (LED OFF)
• Input source is not poor: VVBUS > VVBUSMIN (3.8V TYP) when Charging is disabled or in sleep mode High (LED OFF)
IBAD_SRC (30mA TYP) loading is applied. (Poor source Charge is suspended due to input over-voltage,
detection.) TS fault, timer faults or system over-voltage or 1Hz Blinking
Boost mode is suspended (TS fault)
• Completed input source type detection.
EN_ICHG_MON[1:0] = 01, controlled by register
STAT_SET[1:0]
only, no matter with charging state

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

nINT Interrupt Output Pin sequence is in progress and the device pulses the input
When a new update occurs in the charger states, a 256μs current limit between current limit set forth by IINDPM[4:0]
negative pulse is sent through the nINT pin to interrupt the register and the 100mA current limit. When the pulse
host. The host may not continuously monitor the charger sequence is completed, the input current limit is returned to
device and by receiving the interrupt, it can react and check value set by IINDPM[4:0] register and the PUMPX_UP or
the charger situation on time. PUMPX_DN bit is cleared. In addition, the EN_PUMPX can
be cleared during the current pulse sequence to terminate the
The following events can generate an interrupt pulse:
sequence and force charger to return to input current limit as
1. Faults reflected in REG09 register (watchdog, Boost set forth by the IINDPM[4:0] register immediately. When
overload, charge faults and battery over-voltage). EN_PUMPX bit is low, write to PUMPX_UP and PUMPX_DN
2. Charging completed. bits would be ignored and have no effect on VBUS current
3. PSEL or D+/D- detection identified a connected source limit.
(USB or adapter).
4. Input source voltage entered the "input good" range: SGM41513/SGM41513A/SGM41513D
a) VVBUS exceeded VBAT (not in sleep mode). Protection Features
b) VVBUS came below VVAC_OV. Monitoring of Voltage and Current
c) VVBUS remained above VVBUSMIN (3.8V TYP) when During the converter operation, the input and system voltages
IBAD_SRC (30mA TYP) load current is applied. (VBUS and VSYS) and switch currents are constantly
5. Input removed or out of the "input good" range. monitored to assure safe operation of the device in both Buck
6. A DPM event (VINDPM or IINDPM) occurred (a maskable and Boost modes, as will be explained below.
interrupt).

Once a fault/flag happens, the INT pulse is asserted Buck Mode Voltage and Current Monitoring
immediately and the fault/flag bits are updated in REG09 and 1. Input Over-Voltage (ACOV)
REG0E. Fault/flag status is not reset in the register until the Converter switching will stop as soon as VBUS voltage
host reads it. A new fault/flag will not assert a new INT pulse exceeds VVAC_OV over-voltage limit that is programmable by
until the host reads REG09 and REG0E and all the previous OVP[1:0] in REG06. It is selectable between 5.5V, 6.5V
faults/flags are cleared. Therefore, in order to read the current (default), 10.5V and 14V for USB or 5V, 9V or 12V adaptors
time faults, the host must read REG09 two times respectively.
consecutively. The first read returns the history of the fault Each time VBUS exceeds the OVP limit, an INT pulse is
register status (from the time of the last read or reset) and the asserted. As long as the over-voltage persists, the
second one checks the current active faults. As an exception, CHRG_FAULT[1:0] bits are set to 01 in REG09. Fault will be
the NTC_FAULT bit reports the actual real-time status of TS cleared to 00 if the voltage comes back below limit (and a
pin. hysteresis threshold) and host reads the fault register.
Charger resumes its normal operation when the voltage
Current Pulse Control Protocol comes back below OVP limit.
The device provides the control to generate the VBUS current
2. System Over-Voltage (SYSOVP)
pulse protocol to communicate with adjustable high voltage
During a system load transient, the device clamps the system
adapter in order to signal adapter to increase or decrease
voltage to protect the system components from over-voltage.
output voltage. To enable the interface, the EN_PUMPX bit
The SYSOVP over-voltage limit threshold is 350mV +
must be set. Then the host can select the increase/decrease
VSYS_REG (system regulation voltage + 350mV). Once a
voltage pulse by setting one of the PUMPX_UP or
SYSOVP occurs, switching stops to clamp any overshoot and
PUMPX_DN bit (but not both) to start the VBUS current pulse
a 30mA sink current is applied to SYS to pull the voltage
sequence. During the current pulse sequence, the
down.
PUMPX_UP and PUMPX_DN bits are set to indicate pulse

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Boost Mode Voltage and Current Monitoring If the junction temperature exceeds TSHUT (+150℃), thermal
In Boost mode, the RBFET (reverse blocking) and LSFET shutdown protection arise in which the converter is turned off,
(low-side switch) FET currents and VBUS voltage are CHRG_FAULT[1:0] bits are set to 10 in the fault register and
monitored for protection. an INT pulse is sent.

1. Soft-Start on VBUS When the device recovers and TJ falls below the hysteresis
Boost mode begins with a soft-start to prevent large inrush band of TSHUT_HYS (30℃ under TSHUT), the converter resumes
currents when it is enabled. automatically.

2. Output Short Protection for VBUS

Boost Mode Thermal Protections
Short circuit protection is provided for VBUS output in Boost
Similar to Buck mode, TJ is monitored in Boost mode for
mode. To accept different types of load connected to VBUS
thermal shutdown protection. If junction temperature exceeds
and OTG adaptation, an accurate constant current regulation
TSHUT (+150℃), BATFET will turn off and the Boost mode will
control is implemented for Boost mode. In case of a short
be disabled (OTG_CONFIG bit clears). BATFET will resume If
circuit on VBUS pin, the Q1 turns off and retries 7 times
TJ falls below the hysteresis band of TSHUT_HYS (30℃ under
(Hiccup). If short is not removed after retries, the OTG will be
TSHUT). Boost can recover again by re-enabling OTG_CONFIG
disabled by clearing OTG_CONFIG bit. Also, an INT pulse is
bit by host.
sent and the BOOST_FAULT bit is set to 1 in REG09. When
the host activates the Boost mode again, the BOOST_FAULT
Battery Protections
bit will be cleared.
Battery Over-Voltage Protection (BATOVP)
3. Output Over-Voltage Protection for VBUS The over-voltage limit for the battery is 4% above the battery
In Boost mode, converter stops switching and exits Boost regulation voltage setting. In case of a BATOVP, charging or
mode (by clearing OTG_CONFIG bit) if VBUS voltage rises external direct charging stops right away, the BAT_FAULT bit
above regulation and exceeds the VOTG_OVP over-voltage limit is set to 1 and an INT pulse is sent.
(6V TYP). An INT pulse is sent and the BOOST_FAULT bit is
set 1. Battery Over-Discharge Protection
If battery discharges too much and VBAT falls below the
SGM41513/SGM41513A/SGM41513D Thermal depletion level (VBAT_DPL_FALL), the device turns off BATFET to
Regulation and Shutdown protect battery. This protection is latched and is not recovered
Buck Mode Thermal Protections until an input source is connected to the VBUS pin. In such
Internal junction temperature (TJ) is always monitored to condition, the battery will start charging with the small ISHORT
avoid overheating. A limit of +120 ℃ is considered for current (95mA TYP) first as long as VBAT < VSHORTZ. When
maximum IC surface temperature in Buck mode and if TJ battery voltage is increased and VSHORTZ < VBAT < VBATLOW,
intends to exceed this level, the device reduces the charge the charge current will increase to the pre-charge current
current to keep maximum temperature limited to 120 ℃ level programmed in the IPRECHG[3:0] register.
(thermal regulation mode) and sets the THERM_STAT bit to 1.
As expected, the actual charging current is usually lower than Battery Over-Current Protection for System
programmed value during thermal regulation. Therefore, the The BATFET will latch off, if its current limit is exceeded due to
safety timer runs at half clock rate and charge termination is a short or large overload on the system (IBAT > IBATOP). To reset
disabled during thermal regulation. this latch off and enable BATFET, the "Exit Ship Mode"
procedure must be followed.

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

I2C Serial Interface and Data Communication
2
Standard I C interface is used to program SGM41513/
SGM41513A/SGM41513D parameters and get status reports. SDA
2
I C is well known 2-wire serial communication interface that
can connect one (or more) master device(s) to some slave SCL
devices for two-way communication. The bus lines are named S P

serial data (SDA) and serial clock (SCL). The device that START STOP
initiates a data transfer is a master. A master generates the
2
SCL signal. Slave devices have unique addresses to identify. Figure 13. I C Bus in START and STOP Conditions
A master is typically a micro controller or a digital signal
Data Bit Transmission and Validity
processor.
Data bit (high or low) must remain stable during clock HIGH
The SGM41513/SGM41513A/SGM41513D operate as a period. The state of SDA can only change when SCL is LOW.
slave device that address is 0x1A (1AH). It has twelve 8-bit For each data bit transmission, one clock pulse is generated
registers, numbered from REG00 to REG0F. A register read 2
by the master. Bit transfer in I C is shown in Figure 14.
beyond REG0F (0x0F) returns 0xFF.

SDA
Physical Layer
2
The standard I C interface of SGM41513/SGM41513A/
SGM41513D support standard mode and fast mode SCL
communication speeds. The frequency of stand mode is up to
100kbits/s, while the fast mode is up to 400kbits/s. Bus lines Data Line Stable Change of Data
and Data Valid Allowed
are pulled high by weak current source or pull-up resistors
and in logic high state with no clocking when the bus is free. 2
Figure 14. I C Bus Bit Transfer
The SDA and SCL pins are open-drain.
Byte Format
I2C Data Communication Data is transmitted in 8-bit packets (one byte at a time). The
START and STOP Conditions number of bytes in one transaction is not limited. In each
A transaction is started by taking control of the bus by master packet, the 8 bits are sent successively with the Most
if the bus is free. The transaction is terminated by releasing Significant Bit (MSB) first. An acknowledge (or not-acknowledge)
the bus when the data transfer job is done as shown in Figure bit must come after the 8 data bits. This bit informs the
13. All transactions begin by the master who applies a transmitter whether the receiver is ready to proceed for the
START condition on the bus lines to take over the bus and next byte or not. If the slave is busy and cannot transfer
exchange data. At the end, the master terminates the another byte of data, it can hold the SCL line low and keep
transaction by applying one (or more) STOP condition. the master in a wait state (called clock stretching). When the
START condition is defined when SCL is high and a high to slave is ready for another byte of data, it releases the clock
low transition on the SDA is generated by master. Similarly, a line and data transfer can continue with clocks generated by
STOP is defined when SCL is high and SDA goes from low to master. Figure 15 shows the byte transfer process with I C
2

high. START and STOP are always generated by a master. interface.

After a START and before a STOP the bus is considered
busy.

1 9 1 9

SCL

SDA MSB

Acknowledgement Acknowledgement
S/Sr P/Sr
signal from receiver signal from receiver
START ACK ACK STOP
or Repeated or Repeated
START START
Figure 15. Byte Transfer Process

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Acknowledge (ACK) and Not Acknowledge (NCK) (when master is asking for data). Data direction is the same
After transmission of each byte by transmitter, an for all next bytes of the transaction. To reverse it, a new
acknowledge bit is replied by the receiver as ninth bit. With START or repeated START condition must be sent by master
the acknowledge bit, the receiver informs the transmitter that (STOP will end the transaction). Usually the second byte is a
the byte has been received, and another byte is expected or WRITE sending the register address that is supposed to be
can be sent (ACK) or it is not expected (NCK = not ACK). accesses in the next byte(s). The data transfer transaction is
Clock (SCL) is always generated by the master, including for shown in Figure 16.
the acknowledge clock pulse, no matter who is acting as
WRITE: If the master wants to write in the register, the third
transmitter or receiver. SDA line is released for receiver
byte can be written directly as shown in Figure 17 for a single
control during the acknowledge clock pulse, and the receiver
write data transfer. After receiving the ACK, master may issue
can pull the SDA line low as ACK (reply a 0 bit) or let it be
a STOP condition to end the transaction or send the next
high as NCK during the SCL high pulse. After that, the master
register data, which will be written to the next address in a
can either STOP (P) to end the transaction or send a new
slave as multi-write. A STOP is needed after sending the last
START (S) condition to start a new transfer (called repeated
data.
start). For example, when master wants to read a register in
slave, one start is needed to send the slave address and READ: If the master wants to read a single register (Figure
register address, and then, without a stop condition, another 18), it sends a new START condition along with device
start is sent by master to initiate the receiving transaction address with R/W bit = 1. After ACK is received, master reads
from slave. Master then sends the STOP condition and the SDA line to receive the content of the register. Master
releases the bus. replies with NCK to inform slave that no more data is needed
(single read) or it can send an ACK to request for sending the
Data Direction Bit and Addressing Slaves next register content (multi-read). This can continue until a
The first byte sent by master after the START is always the NCK is sent by master. A STOP must be sent by master in
target slave address (7 bits) and an eighth data-direction bit any case to end the transaction.
(R/W). R/W bit is 0 for a WRITE transaction and 1 for READ

1 9 1 9 1 9

SCL

SDA R/W

S P

START I2C Slave Address ACK Data Byte ACK Data Byte ACK STOP

Figure 16. Data Transfer Transaction

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Frame 1 Frame 2

1 9 1 9

SCL

SDA 0 0 1 1 0 1 0 W B7 B6 B5 B4 B3 B2 B1 B0

START by Byte#1 I2C Slave Address Byte ACK by Byte#2 Register Address Byte ACK by
Master Device Device

Frame 3

1 9
SCL
(Continued)

SDA D7 D6 D5 D4 D3 D2 D1 D0
(Continued)

Byte#3 Data Byte 1 to ACK by STOP by

SGM41513/SGM41513A/SGM41513D Register Device Master

Figure 17. A Single Write Transaction

Frame 1 Frame 2

1 9 1 9

SCL

SDA 0 0 1 1 0 1 0 W B7 B6 B5 B4 B3 B2 B1 B0

START by Byte#1 I2C Slave Address Byte ACK by Byte#2 Register Address Byte ACK by
Master Device Device

Frame 3 Frame 4

1 9 1 9
SCL
(Continued)

SDA 0 0 1 1 0 1 0 R D7 D6 D5 D4 D3 D2 D1 D0
(Continued)

START by Byte#3 I2C Slave Address Byte ACK by Byte#4 Data Byte from Device NCK by STOP by
Master Device Master Master

Figure 18. A Single Read Transaction

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Data Transactions with Multi-Read or Multi-Write In a multi-read transaction, after receiving the first register
Multi-read and multi-write are supported by SGM41513/ data (its address is already written to the slave), the master
SGM41513A/SGM41513D for REG00 through REG0F replies with an ACK to ask the slave for sending the next
registers, except for REG09 and REG0E as explained in register data. This can continue as much as it is needed by
Figure 19 and Figure 20. REG09 (fault register) and REG0E master. Master sends back an NCK after the last received
(Flag register) are skipped in multi-read/writes. In the byte and issues a STOP condition.
multi-write, every new data byte sent by master is written to
the next register of the device. A STOP is sent whenever
master is done with writing into device registers.

Frame 1 Frame 2

1 9 1 9

SCL

SDA 0 0 1 1 0 1 0 W B7 B6 B5 B4 B3 B2 B1 B0

START by Byte#1 I2C Slave Address Byte ACK by Byte#2 Register Address Byte ACK by
Master Device Device

Frame 3 Frame 4

1 9 1 9
SCL
(Continued)

SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(Continued)

Byte#3 Data Byte 1 to ACK by Byte#4 Data Byte 2 to ACK by

SGM41513/SGM41513A/SGM41513D Register Device SGM41513/SGM41513A/SGM41513D Register Device

Frame N

1 9
SCL
(Continued)

SDA
(Continued) D7 D6 D5 D4 D3 D2 D1 D0

Byte#N Data Byte n to ACK by STOP by

SGM41513/SGM41513A/SGM41513D Register Device Master

Figure 19. A Multi-Write Transaction

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Frame 1 Frame 2

1 9 1 9

SCL

SDA 0 0 1 1 0 1 0 W B7 B6 B5 B4 B3 B2 B1 B0

START by Byte#1 I2C Slave Address Byte ACK by Byte#2 Register Address Byte ACK by
Master Device Device

Frame 3 Frame 4

1 9 1 9
SCL
(Continued)

SDA 0 0 1 1 0 1 0 R D7 D6 D5 D4 D3 D2 D1 D0
(Continued)

START by Byte#3 I2C Slave Address Byte ACK by Byte#4 Data Byte 1 from Device ACK by
Master Device Master

Frame 5 Frame N

1 9 1 9
SCL
(Continued)

SDA
(Continued) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Byte#5 Data Byte 2 from Device ACK by Byte#N Data Byte n from Device NCK by STOP by
Master Master Master

Figure 20. A Multi-Read Transaction

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS
All registers are 8-bit and individual bits are named from D[0] (LSB) to D[7] (MSB).

I2C Slave Address of SGM41513/SGM41513A/SGM41513D: 0x1A

R/W: Read/Write bit(s)
R: Read only bit(s)
PORV: Power-On Reset Value
n: Parameter code formed by the bits as an unsigned binary number.

REG00
Register address: 0x00; R/W
PORV = 00010111
Table 7. REG00 Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
Enable HIZ Mode In HIZ mode, the VBUS pin is effectively
REG_RST
D[7] EN_HIZ 0 = Disable (default) disconnected from internal circuit. Some 0 R/W
or Watchdog
1 = Enable leakage current may exist.
Enable STAT Pin Function
00 = Enable following
charging state (default) These bits turn on or off the function of the
D[6:5] EN_ICHG_MON[1:0] 01 = Enable following STAT open-drain output pin (charge status 00 R/W REG_RST
STAT_SET[1:0] bits or customer customized indicator).
10 = Disable (float pin)
11 = Disable (float pin)
IINDPM[4] Input Current Limit Value (n: 5 bits):
1 = 1600mA = 100 + 100n (mA)
IINDPM[3]
1 = 800mA Offset: 100mA
Range: 100mA (00000) - 3.2A (11111)
IINDPM[2] Default: 2400mA (10111), not typical
D[4:0] IINDPM[4:0] 10111 R/W REG_RST
1 = 400mA
IINDPM[1] IINDPM changes after an input source
1 = 200mA detection.

IINDPM[0] Host can overwrite IINDPM after input

1 = 100mA source detection is completed.

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG01
Register address: 0x01; R/W
PORV = 00011010
Table 8. REG01 Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
Enable Pulse Frequency Modulation.
Enable PFM Mode
PFM is normally used to save power at light
D[7] PFM_DIS 0 = Enable (default) 0 R/W REG_RST
load by reducing converter switching
1 = Disable
frequency.
Watchdog Timer Reset Control Bit.
I2C Watchdog Timer Reset
Write 1 to this bit to avoid watchdog expiry. REG_RST
D[6] WD_RST 0 = Normal (default) 0 R/W
WD_RST resets to 0 after watchdog timer or Watchdog
1 = Reset
reset (expiry).
Enable OTG
This bit has priority over charge enable in REG_RST
D[5] OTG_CONFIG 0 = OTG disable (default) 0 R/W
the CHG_CONFIG. or Watchdog
1 = OTG enable
Enable Battery Charging
Charge is enabled when CHG_CONFIG bit REG_RST
D[4] CHG_CONFIG 0 = Charge disable 1 R/W
is 1 and nCE pin is pulled low. or Watchdog
1 = Charge enable (default)
Minimum System Voltage
000 = 2.6V
001 = 2.8V Minimum System Voltage Value.
010 = 3V
D[3:1] SYS_MIN[2:0] 011 = 3.2V Offset: 2.6V 101 R/W REG_RST
100 = 3.4V Range: 2.6V (000) - 3.7V (111)
101 = 3.5V (default) Default: 3.5V (101)
110 = 3.6V
111 = 3.7V
Minimum Battery Voltage for
Default:
OTG Mode
D[0] MIN_BAT_SEL VBAT falling, VBATLOW_OTG = 2.95V. 0 R/W REG_RST
0 = 2.95V VBAT falling (default)
VBAT rising, VBATLOW_OTG = 3.15V.
1 = 2.6V VBAT falling

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG02
Register address: 0x02; R/W
PORV = 10110100
Table 9. REG02 Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
Boost Mode Current Limit The current limit options listed values are
REG_RST
D[7] BOOST_LIM 0 = 0.5A the minimum specs. Actual value is 1 R/W
or Watchdog
1 = 1.2A (default) typically higher.
Used to control the on-resistance of Q1
VBUS FET Switch (Q1)
(VBUS switch) for better input current
0 = Use higher RDSON if IINDPM < 700mA
measurement accuracy.
D[6] Q1_FULLON (for better accuracy) 0 R/W REG_RST
1 = Use lower RDSON always (fully ON for
In Boost mode, full FET is always used,
better efficiency)
and this bit has no effect.
REG_RST
D[5:0] ICHG[5:0] See Table 10 Default: 1980mA (110100) 110100 R/W
or Watchdog

Table 10. ICHG[5:0] Description

ICHG[5:0] ICHG (mA) ICHG[5:0] ICHG (mA) ICHG[5:0] ICHG (mA) ICHG[5:0] ICHG (mA)
000000 0 010000 130 100000 540 110000 1500
000001 5 010001 150 100001 600 110001 1620
000010 10 010010 170 100010 660 110010 1740
000011 15 010011 190 100011 720 110011 1860
000100 20 010100 210 100100 780 110100 1980
000101 25 010101 230 100101 840 110101 2100
000110 30 010110 250 100110 900 110110 2220
000111 35 010111 270 100111 960 110111 2340
001000 40 011000 300 101000 1020 111000 2460
001001 50 011001 330 101001 1080 111001 2580
001010 60 011010 360 101010 1140 111010 2700
001011 70 011011 390 101011 1200 111011 2820
001100 80 011100 420 101100 1260 111100 2940
001101 90 011101 450 101101 1320 111101 3000
001110 100 011110 480 101110 1380 111110 3000
001111 110 011111 510 101111 1440 111111 3000

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG03 (Pre-Charge and Termination Current Settings)
Register address: 0x03; R/W
PORV = 10101010
Table 11. REG03 Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
REG_RST
D[7:4] IPRECHG[3:0] See Table 12 1010 R/W
or Watchdog
REG_RST
D[3:0] ITERM[3:0] See Table 13 1010 R/W
or Watchdog

Table 12. IPRECHG[3:0] Description Table 13. ITERM[3:0] Description

IPRECHG[3:0] IPRECHG (mA) IPRECHG[3:0] IPRECHG (mA) ITERM[3:0] ITERM (mA) ITERM[3:0] ITERM (mA)
0000 5 1000 80 0000 5 1000 80
0001 10 1001 100 0001 10 1001 100
0010 15 1010 120 0010 15 1010 120
0011 20 1011 140 0011 20 1011 140
0100 30 1100 160 0100 30 1100 160
0101 40 1101 180 0101 40 1101 180
0110 50 1110 200 0110 50 1110 200
0111 60 1111 240 0111 60 1111 240

REG04
Register address: 0x04; R/W
PORV = 01011000
Table 14. REG04 Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
VREG[4]
Charge Voltage Limit (n: 5 bits): 0 R/W
1 = 512mV
= 3856 + 32n (mV) if n ≤ 24, n≠15;
VREG[3] = 4.35V if n = 15
1 R/W
1 = 256mV Offset: 3.856V
Range: 3.856V (00000) - 4.624V (11000)
VREG[2] REG_RST
D[7:3] VREG[4:0] Default: 4.208V (01011) 0 R/W
1 = 128mV or Watchdog
Special Value: 4.350V (01111)
VREG[1]
1 R/W
1 = 64mV Note:
Values above 24D = 11000 (4.624V) are
VREG[0]
clamped to 24D = 11000 (4.624V). 1 R/W
1 = 32mV
Top-Off Timer The charge extension time added after the
00 = Disabled (default) termination condition is detected. 0 R/W
REG_RST
D[2:1] TOPOFF_TIMER[1:0] 01 = 15 minutes
or Watchdog
10 = 30 minutes If disabled, charging terminates as soon as 0 R/W
11 = 45 minutes termination conditions are met.
Battery Recharge Threshold
A recharge cycle will start if a fully charged
0 = 100mV below VREG[4:0] REG_RST
D[0] VRECHG battery voltage drops below VREG - VRECHG 0 R/W
(default) or Watchdog
settings.
1 = 200mV below VREG[4:0]

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG05
Register address: 0x05; R/W
PORV = 10111111
Table 15. REG05 Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
Charging Termination Enable
REG_RST
D[7] EN_TERM 0 = Disable 1 R/W
or Watchdog
1 = Enable (default)
ITERM Deglitch Timer Setting
REG_RST
D[6] ITERM_TIMER 0 = 200ms (default) 0 R/W
or Watchdog
1 = 16ms
Watchdog Timer Setting
00 = Disable watchdog timer
Expiry time of the watchdog timer if it is REG_RST
D[5:4] WATCHDOG[1:0] 01 = 40s 11 R/W
not reset. or Watchdog
10 = 80s
11 = 160s(default)
Charge Safety Timer Enable
When enabled the pre-charge and fast REG_RST
D[3] EN_TIMER 0 = Disable 1 R/W
charge periods are included in the timing. or Watchdog
1 = Enable (default)
Charge Safety Timer Setting
REG_RST
D[2] CHG_TIMER 0 = 7h 1 R/W
or Watchdog
1 = 16h (default)
Thermal Regulation Threshold
REG_RST
D[1] TREG 0 = 80℃ For Buck mode. 1 R/W
or Watchdog
1 = 120℃ (default)
JEITA Charging Current
JEITA_ISET_L REG_RST
D[0] 0 = 50% of ICHG When JEITA_ISET_L_EN = 1. 1 R/W
(0℃ - 10℃) or Watchdog
1 = 20% of ICHG (default)

REG06
Register address: 0x06; R/W
PORV = 11100110
Table 16. REG06 Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
VAC Pin OVP Threshold
00 = 5.5V 1 R/W
D[7:6] OVP[1:0] 01 = 6.5V (5V input) OVP Threshold for Input Supply. REG_RST
10 = 10.5V (9V input) 1 R/W
11 = 14V (12V input) (default)
Boost Mode Voltage Regulation
00 = 4.85V 1 R/W
D[5:4] BOOSTV[1:0] 01 = 5.00V REG_RST
10 = 5.15V (default) 0 R/W
11 = 5.30V
VINDPM Threshold (n: 4 bits):
VINDPM[3] = Offset + 0.1n (V) 0 R/W
1 = 800mV
Offset: 3.9V (VINDPM_OS = 00, default)
Range: 3.9V (0000) - 5.4V (1111)
VINDPM[2] Default: 4.5V (0110) 1 R/W
1 = 400mV
D[3:0] VINDPM[3:0] Offset: 5.9V (VINDPM_OS = 01) REG_RST
VINDPM[1] Range: 5.9V (0000) – 7.4V (1111)
1 R/W
1 =200mV
Offset: 7.5V (VINDPM_OS = 10)
Range: 7.5V (0000) - 9V (1111)
VINDPM[0]
Offset: 10.5V (VINDPM_OS = 10) 0 R/W
1 =100mV
Range: 10.5V (0000) - 12V (1111)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG07
Register address: 0x07; R/W
PORV = 01001100
Table 17. REG07 Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
Input Current Limit Detection
0 = Not in input current limit detection
Reloads with 0 when input detection REG_RST
D[7] IINDET_EN (default) 0 R/W
is completed. or Watchdog
1 = Force input current limit detection
when VBUS is present
Enable Half Clock Rate Safety Timer
0 = Disable
REG_RST
D[6] TMR2X_EN 1 = Safety timer slow down during Slow down by a factor of 2. 1 R/W
or Watchdog
DPM, JEITA cool, or thermal
regulation (default)
Disable BATFET
0 = Allow BATFET (Q4) to turn on
D[5] BATFET_DIS (default) tSM_DLY is typically 12 seconds. 0 R/W REG_RST
1 = Turn off BATFET (Q4) after a
tSM_DLY delay time (REG07 D[3])
JEITA Charging Voltage
JEITA_VSET_H 0 = Set charge voltage to the lower of REG_RST
D[4] 0 R/W
(45℃ - 60℃) 4.1V (default) or Watchdog
1 = Set charge voltage to VREG
BATFET Turn Off Delay Control
0 = Turn off BATFET immediately
D[3] BATFET_DLY BATFET_DIS bit is set. 1 R/W REG_RST
1 = Turn off BATFET after tSM_DLY
(default)
Enable BATFET Reset
REG_RST
D[2] BATFET_RST_EN 0 = Disable BATFET reset 1 R/W
or Watchdog
1 = Enable BATFET reset (default)
Dynamic VINDPM Tracking
00 = Disable (VINDPM set by register) Set VINDPM to track VBAT voltage. Actual 0 R/W
VDPM_BAT_
D[1:0] 01 = VBAT + 200mV VINDPM is the larger of VINDPM[3:0] and REG_RST
TRACK[1:0]
10 = VBAT + 250mV this register value. 0 R/W
11 = VBAT + 300mV

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG08 (Status Bits, Read Only)
Register address: 0x08; R
PORV = xxxxxxxx
Table 18. REG08 Register Details
BITS BIT NAME DESCRIPTION PORV TYPE RESET BY
VBUS Status Register (SGM41513D)
000 = No input
001 = USB host SDP x R
010 = USB CDP (1.5A)
011 = USB DCP (2.4A)
101 = Unknown adapter (500mA)
110 = Non-standard adapter (1A/2A/2.1A/2.4A)
111 = OTG
D[7:5] VBUS_STAT[2:0] x R NA
VBUS Status Register (SGM41513)
000 = No input
001 = USB host SDP (500mA) → PSEL HIGH
010 = Adapter 2.4A → PSEL LOW
111 = OTG x R
Other values are reserved.
Current limit value is reported in IINDPM[4:0] register.
Charging Status
00 = Charge disable x R
D[4:3] CHRG_STAT[1:0] 01 = Pre-charge (VBAT < VBATLOW) NA
10 = Fast charging (constant current or voltage) x R
11 = Charging terminated
Input Power Status (VBUS in good voltage range and not poor)
D[2] PG_STAT 0 = Input power source is not good x R NA
1 = Input power source is good
Thermal Regulation Status
D[1] THERM_STAT 0 = Not in thermal regulation x R NA
1 = In thermal regulation
System Voltage Regulation Status
D[0] VSYS_STAT 0 = Not in VSYS_MIN regulation (VBAT > VSYS_MIN) x R NA
1 = In VSYS_MIN regulation (VBAT < VSYS_MIN)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG09 (Fault Bits, Read Only)
Register address: 0x09; R
PORV = xxxxxxxx
Table 19. REG09 Register Details
BITS BIT NAME DESCRIPTION PORV TYPE RESET BY
Watchdog Fault Status
D[7] WATCHDOG_FAULT 0 = Normal (no fault) x R NA
1 = Watchdog timer expired
Boost Mode Fault Status
0 = Normal
D[6] BOOST_FAULT x R NA
1 = VBUS overloaded in OTG, or VBUS OVP, or battery voltage too low
(any condition that prevents Boost starting)
Charging Fault Status
00 = Normal x R
D[5:4] CHRG_FAULT[1:0] 01 = Input fault (VAC OVP or VBAT < VVBUS < 3.8V) NA
10 = Thermal shutdown x R
11 = Charge safety timer expired
Battery Fault Status
D[3] BAT_FAULT 0 = Normal x R NA
1 = Battery over-voltage (BATOVP)
JEITA Condition Based on Battery NTC Temperature Measurement
000 = Normal x R
010 = Warm
011 = Cool (Buck mode only) x R
D[2:0] NTC_FAULT[2:0] NA
101 = Cold
110 = Hot
NTC fault bits are updated in real-time and does not need a read to x R
reset.

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG0A
Register address: 0x0A; R and R/W
PORV = xxxxxx00
Table 20. REG0A Register Details
BITS BIT NAME DESCRIPTION PORV TYPE RESET BY
Good Input Source Detected
D[7] VBUS_GD 0 = A good VBUS is not attached x R NA
1 = A good VBUS attached
Input Voltage Regulation (Dynamic Power Management)
D[6] VINDPM_STAT 0 = Not in VINDPM x R NA
1 = In VINDPM
Input Current Regulation (Dynamic Power Management)
D[5] IINDPM_STAT 0 = Not in IINDPM x R NA
1 = In IINDPM
D[4] Reserved Reserved. x R NA
Active Top-Off Timer Counting Status
D[3] TOPOFF_ACTIVE 0 = Top-off timer not counting x R NA
1 = Top-off timer counting
Input Over-Voltage Status (AC adaptor is the input source)
D[2] ACOV_STAT 0 = No over-voltage (no ACOV) x R NA
1 = Over-voltage detected (ACOV)
VINDPM Event Detection Interrupt Mask
D[1] VINDPM_INT_MASK 0 = Allow VINDPM INT pulse 0 R/W REG_RST
1 = Mask VINDPM INT pulse
IINDPM Event Detection Mask
D[0] IINDPM_INT_MASK 0 = Allow IINDPM to send INT pulse 0 R/W REG_RST
1 = Mask IINDPM INT pulse

REG0B
Register address: 0x0B; R and R/W
PORV = 0000x0xx
Table 21. REG0B Register Description
BITS BIT NAME DESCRIPTION PORV TYPE RESET BY
Register Reset
0 = No effect (keep current register settings)
D[7] REG_RST 0 R/W REG_RST
1 = Reset R/W bits of all registers to the default and reset safety timer
(It also resets itself to 0 after register reset is completed.)
0 R
Part ID 0 R
D[6:3] PN[3:0] 0000 = SGM41513 NA
0001 = SGM41513A or SGM41513D 0 R
x R
D[2] SGMPART 0 R NA
x R
D[1:0] DEV_REV[1:0] Revision NA
x R

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG0C
Register address: 0x0C; R/W
PORV = 01110101
Table 22. REG0C Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
JEITA Charging Voltage
JEITA_VSET_L 0 = Set charge voltage to VREG (default) REG_RST
D[7] 0 R/W
(0℃ - 10℃) 1 = Set charge voltage to the lower of 4.1V or Watchdog
and VREG
Charge Enable During Cool Temperature
JEITA_ISET_L_EN REG_RST
D[6] 0 = Disable 1 R/W
(0℃ - 10℃) or Watchdog
1 = Enable (default)
Charge Current Setting during Warm
Temperature
JEITA_ISET_H[1:0] 00 = 0% of ICHG In warm condition, the safety REG_RST
D[5:4] 11 R/W
(45℃ - 60℃) 01 = 20% of ICHG timer does not become 2X. or Watchdog
10 = 50% of ICHG
11 = 100% of ICHG (default)
JEITA Cool Threshold Setting
00 = VT2 = 70.75% (5.5℃)
REG_RST
D[3:2] JEITA_VT2[1:0] 01 = VT2 = 68.25% (10℃) (default) 01 R/W
or Watchdog
10 = VT2 = 65.25% (15℃)
11 = VT2 = 62.25% (20℃)
JEITA Warm Threshold Setting
00 = VT3 = 48.25% (40℃)
REG_RST
D[1:0] JEITA_VT3[1:0] 01 = VT3 = 44.75% (44.5℃) (default) 01 R/W
or Watchdog
10 = VT3 = 40.75% (50.5℃)
11 = VT3 = 37.75% (54.5℃)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG0D
Register address: 0x0D; R/W
PORV = 00000001
Table 23. REG0D Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
Current Pulse Control Enable
REG_RST
D[7] EN_PUMPX 0 = Disable (default) 0 R/W
or Watchdog
1 = Enable (PUMPX_UP and PUMPX_DN)
This bit can only be set
Current Pulse Control Voltage up Enable when EN_PUMPX bit is set
REG_RST
D[6] PUMPX_UP 0 = Disable (default) and returns to 0 after current 0 R/W
or Watchdog
1 = Enable pulse control sequence is
completed.
This bit can only be set
Current Pulse Control Voltage down Enable when EN_PUMPX bit is set
REG_RST
D[5] PUMPX_DN 0 = Disable (default) and returns to 0 after current 0 R/W
or Watchdog
1 = Enable pulse control sequence is
completed.
D+ Output Voltage Setting Register bits are reset to
00 = HIZ (default) default value when input
REG_RST
D[4:3] DP_VSET[1:0] 01 = 0V source is plugged-in and 00 R/W
or Watchdog
10 = 0.6V can be changed after D+/D-
11 = 3.3V detection is completed.
D- Output Voltage Setting Register bits are reset to
00 = HIZ(default) default value when input
REG_RST
D[2:1] DM_VSET[1:0] 01 = 0V source is plugged-in and 00 R/W
or Watchdog
10 = 0.6V can be changed after D+/D-
11 = 3.3V detection is completed.
Frequency Select in Boost Mode:
0 = 500kHz
This bit can set boost mode
1 = 1.5MHz (default)
switching frequency and REG_RST
D[0] OTGF_ITREMR ITERM Range Select in Charge Mode: 1 R/W
charge mode termination or Watchdog
0 = ITERM[3:0] × 6 (active when ICHG[5:0] >
current range.
300mA)
1 = ITERM[3:0] (default)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

REGISTER MAPS (continued)

REG0E
Register address: 0x0E; R or R/W
PORV = xxxxxxxx
Table 24. REG0E Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
VBUS Input Detection Done Flag PSEL or DPDM detection done flag
D[7] INPUT_DET_DONE 0 = Normal after VBUS plug In or set X R NA
1 = Detection done FORCE_DPDM = 1

D[6:0] Reserved Reserved. X R NA

REG0F
Register address: 0x0F; R or R/W
PORV = 00000000
Table 25. REG0F Register Details
BITS BIT NAME DESCRIPTION COMMENT PORV TYPE RESET BY
VREG Fine Tuning
00 = Disable (default)
REG_RST
D[7:6] VREG_FT 01 = VREG + 8mV 00 R/W
or Watchdog
10 = VREG - 8mV
11 = VREG - 16mV
REG_RST
D[5] Reserved Reserved. 0 R/W
or Watchdog
Trickle Charge Current Setting
REG_RST
D[4] ISHORT_SET 0 = 90mA (default) 0 R/W
or Watchdog
1 = 30mA
STAT Pin Output Setting
00 = LED off (HIZ) (default)
This bits only takes effect when REG_RST
D[3:2] STAT_SET[1:0] 01 = LED on (low) 00 R/W
EN_ICHG_MON[1:0] = 01 or Watchdog
10 = LED Blinking 1s on 1s off
11 = LED Blinking 1s on 3s off
VINDPM Offset
00 = 3.9V (default)
D[1:0] VINDPM_OS[1:0] 01 = 5.9V 00 R/W REG_RST
10 = 7.5V
11 = 10.5V

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

APPLICATION INFORMATION
The SGM41513/SGM41513A/SGM41513D are typically used For the SGM41513/SGM41513A/SGM41513D, place CIN
as a charger with power path management in smart phones, across PMID and GND pins close to the chip. Voltage rating
tablets and other portable devices. In the design, it comes of the capacitor must be at least 25% higher than the normal
2
along with a host controller (a processor with I C interface) input voltage to minimize voltage derating. For a 15V input
voltage, the preferred rating is 25V or higher.
and a single-cell Li-Ion or Li-polymer battery.
A CIN = 22μF is suggested.
Detailed Design Procedure
Inductor Design Output Capacitor Design
Small energy storage elements (inductor and capacitor) can The output capacitance (on the system) must have enough
be used due to the high frequency (1.5MHz) switching RMS (ripple) current rating to carry the inductor switching
converter used in the SGM41513/SGM41513A/SGM41513D. ripple and provide enough energy for system transient current
Inductor should tolerate currents higher than the maximum demands. ICOUT (COUT RMS current) can be calculated by:
charge current (ICHG) plus half the inductor peak to peak ripple
I RIPPLE
current (∆I) without saturation: ICOUT= ≈ 0.29 × IRIPPLE
2× 3 (6)
∆I (3)
ISAT > ICHG +
2 And the output voltage ripple can be calculated by:

The inductor ripple current is determined by the input voltage VOUT  VOUT  (7)
∆VO
= 1− 
(VVBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fS = 8LCOUT fS 2  VVBUS 
1.5MHz) and the inductance (L). In CCM:
Increasing L or COUT (the LC filter) can reduce the ripple.
V × D × (1 − D ) (4)
∆I = VBUS The internal loop compensation of the device is optimized for >
fS × L
22μF ceramic output capacitor. 10V, X7R (or X5R) ceramic
Inductor ripple current is maximum when D ≈ 0.5. If the input capacitors are recommended for the output.
voltage range (VVBUS) is limited higher, D values can be The design is based on Buck mode operation that has almost
considered. 2.5 times higher current rating (3A) compared to the Boost
In the practical designs, inductor peak to peak current ripple mode (1.2A). The design is sufficient for proper Boost
is selected in a range between 20% to 40% of the maximum operation, because converter is bidirectional and only the
DC current ∆I = (0.2 ~ 0.4) × ICHG for a good trade-off between direction of currents is reversed.
inductor size and efficiency. Selecting higher ripple allows
choosing of smaller inductance. Input Power Supply Considerations
To power the system from the SGM41513/SGM41513A/
For each application, VVBUS and ICHG are known, so L can be SGM41513D, either an input power source with a voltage
calculated from (4) and current rating of the inductor can be between 3.9V to 13.5V and at least 100mA current rating
selected from (3). Choose an inductor that has small DCR should power VBUS, or a single-cell Li-Ion battery with
and core losses at 1.5MHz to have high efficiency and cool voltage higher than VBAT_UVLOZ should be connected to BAT
operation at full load. pin of the device. The input source must have enough current
rating to allow maximum power delivery through charger
Input Capacitor Design (Buck converter) to the system.
Select low ESR ceramic input capacitor (X7R or X5R) with
sufficient voltage and RMS ripple current rating for decoupling
of the input switching ripple current (ICIN). The RMS ripple
current in the worst case is around the ICHG/2 when D ≈ 0.5. If
the converter does not operate at D ≈ 50%, the worst case
capacitor RMS current can be estimated from (5) in which D
is the closest operating duty cycle to 0.5.

ICIN= ICHG × D × (1 − D )
(5)

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SGM41513 High Input Voltage, 3A Single-Cell Battery Charger
SGM41513A/SGM41513D with NVDC Power Path Management

APPLICATION INFORMATION (continued)

Layout Guidelines It is better to avoid using vias for these connections and keep
The switching node (SW) creates very high frequency noises, the high frequency current paths short enough and on the
which are several times higher than fSW (1.5MHz) due to same layer. A GND copper layer under the component layer
sharp rise and fall of the voltage and current in the switches. helps to reduce noise emissions. Pay attention to the DC
To reduce the ringing issues and noise generation, it is current and AC current paths in the layout and keep them
important to design a proper layout for minimizing the current short and decoupled as much as possible.
path impedance and loop area. A graphical guideline for the
4. For analog signals, it is better to use a separate analog
current loops and their frequency content is provided in
ground (AGND) branched only at one point from GND pin. To
Figure 21. The following considerations can help to make a
avoid high current flow through the AGND path, it should be
better layout.
connected to GND only at one point (preferably the GND pin).
1. Place the input capacitor between PMID and GND pins as
5. Place decoupling capacitors close to the IC pins with the
close as possible to the chip with shortest copper connections
shortest copper connections.
(avoid vias). Choose the smallest capacitor size.
6. Solder the exposed thermal pad of the package to the PCB
2. Connect one pin of the inductor as close as possible to the
ground planes. Ensure that there are enough thermal vias
SW pin of the device and minimize the copper area
directly under the IC, connecting to the ground plane on the
connected to the SW node to reduce capacitive coupling from
other layers for better heat dissipation and cooling of the
SW area to nearby signal traces. This decreases the noise
device.
induced through parasitic stray capacitances and
displacement currents to other conductors. SW connection 7. Select proper sizes for the vias and ensure enough copper
should be wide enough to carry the charging current. Keep is available to carry the current for a given current path. Vias
other signals and traces away from SW if possible. usually have some considerable parasitic inductance and
resistance.
3. Place output capacitor GND pin as close as possible to the
GND pin of the device and the GND pin of input capacitor CIN.

DC Current DC Current Path

(IAC ≈ 0) (IAC ≈ 0)
SYS
SW

(Boost Mode
Direction)
Very High Switching Frequency and
Frequency Its Low Order Harmonics
(Current Path) SYS
(Current Path)

CIN Load Transient

COUT Current Path

Figure 21. The Paths and Loops Carrying High Frequency, DC Currents and Very High Frequency
(for Layout Design Consideration)

REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (SEPTEMBER 2022) to REV.B Page

Changed from product preview to production data ............................................................................................................................................. All

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 PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

TQFN-4×4-24L

D e

L D1

E E1

N24

k
PIN 1# N1
DETAIL A b

TOP VIEW BOTTOM VIEW

3.8
C 2.7
SEATING PLANE

A1
A2 eee C

2.7 3.8
SIDE VIEW

0.7
ALTERNATE A-1 ALTERNATE A-2

DETAIL A 0.24 0.5

ALTERNATE TERMINAL
CONSTRUCTION
RECOMMENDED LAND PATTERN (Unit: mm)

Dimensions In Millimeters
Symbol
MIN MOD MAX
A 0.700 - 0.800
A1 0.000 - 0.050
A2 0.203 REF
b 0.180 - 0.300
D 3.900 - 4.100
E 3.900 - 4.100
D1 2.600 - 2.800
E1 2.600 - 2.800
e 0.500 BSC
k 0.200 MIN
L 0.300 - 0.500
eee 0.080

NOTE: This drawing is subject to change without notice.

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 PACKAGE INFORMATION

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

P2 P0

W
Q1 Q2 Q1 Q2 Q1 Q2
B0
Q3 Q4 Q3 Q4 Q3 Q4

Reel Diameter

P1 A0 K0

Reel Width (W1)

DIRECTION OF FEED

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF TAPE AND REEL

Reel Width
Reel A0 B0 K0 P0 P1 P2 W Pin1
Package Type W1
Diameter (mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
(mm)

DD0001
TQFN-4×4-24L 13″ 12.4 4.30 4.30 1.10 4.0 8.0 2.0 12.0 Q2

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 PACKAGE INFORMATION
CARTON BOX DIMENSIONS

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF CARTON BOX

Length Width Height

Reel Type Pizza/Carton
(mm) (mm) (mm) DD0002

13″ 386 280 370 5

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