M27C512

512 Kbit (64Kb x8) UV EPROM and OTP EPROM

5V ± 10% SUPPLY VOLTAGE in READ

OPERATION
FAST ACCESS TIME: 45ns
LOW POWER “CMOS” CONSUMPTION:
– Active Current 30mA 28 28
– Standby Current 100µA
PROGRAMMING VOLTAGE: 12.75V ± 0.25V 1 1
PROGRAMMING TIMES of AROUND 6sec. FDIP28W (F) PDIP28 (B)
(PRESTO IIB ALGORITHM)
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 3Dh

DESCRIPTION
The M27C512 is a 512 Kbit EPROM offered in the PLCC32 (C) TSOP28 (N)
two ranges UV (ultra violet erase) and OTP (one 8 x 13.4mm
time programmable). It is ideally suited for applica-
tions where fast turn-around and pattern experi-
mentation are important requirements and is
organized as 65,536 by 8 bits. Figure 1. Logic Diagram
The FDIP28W (window ceramic frit-seal package)
has transparent lid which allows the user to expose
the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written to the device by VCC
following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the 16 8
M27C512 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages. A0-A15 Q0-Q7

E M27C512
Table 1. Signal Names
GVPP
A0-A15 Address Inputs

Q0-Q7 Data Outputs

E Chip Enable

GVPP Output Enable / Program Supply VSS

AI00761B

VCC Supply Voltage

VSS Ground

November 1998 1/15

M27C512

Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections

VCC
A12
A15

A14
A13
A15 1 28 VCC

DU
A7
A12 2 27 A14
A7 3 26 A13 1 32
A6 4 25 A8 A6 A8
A5 5 24 A9 A5 A9
A4 6 23 A11 A4 A11
A3 7 22 GVPP A3 NC
M27C512 A2 9 M27C512 25 GVPP
A2 8 21 A10
A1 9 20 E A1 A10
A0 10 19 Q7 A0 E
Q0 11 18 Q6 NC Q7
Q1 12 17 Q5 Q0 Q6
17
Q2 13 16 Q4

Q1
Q2
VSS
DU
Q3
Q4
Q5
VSS 14 15 Q3
AI00762
AI00763

Warning: NC = Not Connected, DU = Don’t Use

Figure 2C. TSOP Pin Connections DEVICE OPERATION

The modes of operations of the M27C512 are listed
in the Operating Modes table. A single power
supply is required in the read mode. All inputs are
TTL levels except for GVPP and 12V on A9 for
Electronic Signature.
GVPP 22 21 A10
A11 E
Read Mode
A9 Q7 The M27C512 has two control functions, both of
A8 Q6 which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
A13 Q5 control and should be used for device selection.
A14 Q4 Output Enable (G) is the output control and should
VCC 28 15 Q3 be used to gate data to the output pins, inde-
M27C512 pendent of device selection. Assuming that the
A15 1 14 VSS
A12 Q2
addresses are stable, the address access time
(tAVQV) is equal to the delay from E to output (tELQV).
A7 Q1 Data is available at the output after a delay of tGLQV
A6 Q0 from the falling edge of G, assuming that E has
A5 A0 been low and the addresses have been stable for
A4 A1 at least tAVQV-tGLQV.
A3 7 8 A2 Standby Mode
AI00764B The M27C512 has a standby mode which reduces
the active current from 30mA to 100µA The
M27C512 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high impedance
state, independent of the GVPP input.

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 M27C512

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
TA Ambient Operating Temperature (3)
–40 to 125 °C
TBIAS Temperature Under Bias –50 to 125 °C
TSTG Storage Temperature –65 to 150 °C
(2)
VIO Input or Output Voltages (except A9) –2 to 7 V
VCC Supply Voltage –2 to 7 V
(2)
VA9 A9 Voltage –2 to 13.5 V
VPP Program Supply Voltage –2 to 14 V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.

Table 3. Operating Modes

Mode E GVPP A9 Q0 - Q7
Read VIL VIL X Data Out
Output Disable VIL VIH X Hi-Z
Program VIL Pulse VPP X Data In
Program Inhibit VIH VPP X Hi-Z
Standby VIH X X Hi-Z
Electronic Signature VIL VIL VID Codes
Note: X = VIH or VIL, VID = 12V ± 0.5V

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h
Device Code VIH 0 0 1 1 1 1 0 1 3Dh

Two Line Output Control For the most efficient use of these two control lines,
Because EPROMs are usually used in larger mem- E should be decoded and used as the primary
ory arrays, the product features a 2 line control device selecting function, while G should be made
function which accommodates the use of multiple a common connection to all devices in the array
memory connection. The two line control function and connected to the READ line from the system
allows: control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
a. the lowest possible memory power dissipation, and that the output pins are only active when data
b. complete assurance that output bus contention is required from a particular memory device.
will not occur.

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M27C512

Table 5. AC Measurement Conditions

High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit

1.3V
High Speed

3V 1N914

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V

0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Note. 1. Sampled only, not 100% tested.

System Considerations The associated transient voltage peaks can be

The power switching characteristics of Advanced suppressed by complying with the two line output
CMOS EPROMs require careful decoupling of the control and by properly selected decoupling ca-
devices. The supply current, ICC, has three seg- pacitors. It is recommended that a 0.1µF ceramic
ments that are of interest to the system designer: capacitor be used on every device between VCC
the standby current level, the active current level, and VSS. This should be a high frequency capacitor
and transient current peaks that are produced by of low inherent inductance and should be placed
the falling and rising edges of E. The magnitude of as close to the device as possible. In addition, a
the transient current peaks is dependent on the 4.7µF bulk electrolytic capacitor should be used
capacitive and inductive loading of the device at the between VCC and VSS for every eight devices. The
output. bulk capacitor should be located near the power
supplyconnection point.The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.

4/15
 M27C512

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

E = VIL, G = VIL,
ICC Supply Current 30 mA
IOUT = 0mA, f = 5MHz

ICC1 Supply Current (Standby) TTL E = VIH 1 mA

ICC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA

IPP Program Current VPP = VCC 10 µA

VIL Input Low Voltage –0.3 0.8 V

(2)
VIH Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

Output High Voltage TTL IOH = –1mA 3.6 V

VOH
Output High Voltage CMOS IOH = –100µA VCC –0.7V V
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C512
Symbol Alt Parameter Test Condition -45 (3) -60 -70 -80 Unit

Min Max Min Max Min Max Min Max

Address Valid to
tAVQV tACC E = VIL, G = VIL 45 60 70 80 ns
Output Valid
Chip Enable
tELQV tCE Low to Output G = VIL 45 60 70 80 ns
Valid
Output Enable
tGLQV tOE Low to Output E = VIL 25 30 35 40 ns
Valid
Chip Enable
tEHQZ (2) tDF High to Output G = VIL 0 25 0 25 0 30 0 30 ns
Hi-Z
Output Enable
tGHQZ (2) tDF High to Output E = VIL 0 25 0 25 0 30 0 30 ns
Hi-Z
Address
tAXQX tOH Transition to E = VIL, G = VIL 0 0 0 0 ns
Output Transition
Notes. 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. In case of 45ns speed see High Speed AC measurement conditions.

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M27C512

Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C512
Symbol Alt Parameter Test Condition -90 -10 -12 -15/-20/-25 Unit

Min Max Min Max Min Max Min Max

Address Valid to
tAVQV tACC E = VIL, G = VIL 90 100 120 150 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 90 100 120 150 ns
Output Valid
Output Enable Low
tGLQV tOE E = VIL 40 40 50 60 ns
to Output Valid
Chip Enable High to
tEHQZ (2) tDF G = VIL 0 30 0 30 0 40 0 50 ns
Output Hi-Z
Output Enable High
tGHQZ (2) tDF E = VIL 0 30 0 30 0 40 0 50 ns
to Output Hi-Z
Address Transition
tAXQX tOH to E = VIL, G = VIL 0 0 0 0 ns
Output Transition
Notes. 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A15 VALID VALID

tAVQV tAXQX

tEHQZ
tGLQV

tELQV tGHQZ

Hi-Z
Q0-Q7

AI00735B

Programming E is pulsed to VIL. The data to be programmed is

When delivered (and after each erasure for UV applied to 8 bits in parallel to the data output pins.
EPROM), all bits of the M27C512 are in the ’1’ The levels required for the address and data inputs
state. Data is introduced by selectively program- are TTL. VCC is specified to be 6.25V ± 0.25V.
ming ’0’s into the desired bit locations. Although The M27C512 can use PRESTO IIB Programming
only ’0’s will be programmed, both ’1’s and ’0’s can Algorithm that drastically reduces the programming
be present in the data word. The only way to time (typically less than 6 seconds). Nevertheless
change a ’0’ to a ’1’ is by die exposure to ultraviolet to achieve compatibility with all programming
light (UV EPROM). The M27C512 is in the pro- equipments, PRESTO Programming Algorithm can
gramming mode when VPP input is at 12.75V and be used as well.

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 M27C512

Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA
ICC Supply Current 50 mA
IPP Program Current E = VIL 50 mA
VIL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1mA 0.4 V
VOH Output High Voltage TTL IOH = –1mA 3.6 V
VID A9 Voltage 11.5 12.5 V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

Table 10. MARGIN MODE AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tA9HVPH tAS9 VA9 High to VPP High 2 µs
tVPHEL tVPS VPP High to Chip Enable Low 2 µs
tA10HEH tAS10 VA10 High to Chip Enable High (Set) 1 µs
tA10LEH tAS10 VA10 Low to Chip Enable High (Reset) 1 µs
tEXA10X tAH10 Chip Enable Transition to VA10 Transition 1 µs
tEXVPX tVPH Chip Enable Transition to VPP Transition 2 µs
tVPXA9X tAH9 VPP Transition to VA9 Transition 2 µs
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

Table 11. Programming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVEL tAS Address Valid to Chip Enable Low 2 µs
tQVEL tDS Input Valid to Chip Enable Low 2 µs
tVCHEL tVCS VCC High to Chip Enable Low 2 µs
tVPHEL tOES VPP High to Chip Enable Low 2 µs
tVPLVPH tPRT VPP Rise Time 50 ns
tELEH tPW Chip Enable Program Pulse Width (Initial) 95 105 µs
tEHQX tDH Chip Enable High to Input Transition 2 µs
tEHVPX tOEH Chip Enable High to VPP Transition 2 µs
tVPLEL tVR VPP Low to Chip Enable Low 2 µs
tELQV tDV Chip Enable Low to Output Valid 1 µs
(2)
tEHQZ tDFP Chip Enable High to Output Hi-Z 0 130 ns
tEHAX tAH Chip Enable High to Address Transition 0 ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.

7/15
M27C512

Figure 6. MARGIN MODE AC Waveforms

VCC

A8

A9

tA9HVPH tVPXA9X

GVPP

tVPHEL tEXVPX

tA10HEH tEXA10X

A10 Set

A10 Reset

tA10LEH

AI00736B

Note: A8 High level = 5V; A9 High level = 12V.

Figure 7. Programming and Verify Modes AC Waveforms

A0-A15 VALID

tAVEL tEHAX

Q0-Q7 DATA IN DATA OUT

tQVEL tEHQX tEHQZ

VCC tELQV

tVCHEL tEHVPX
GVPP

tVPHEL tVPLEL

E
tELEH

PROGRAM VERIFY

AI00737

8/15
Figure 8. Programming Flowchart

VCC = 6.25V, VPP = 12.75V

SET MARGIN MODE

n=0

E = 100µs Pulse

NO

++n NO
= 25 VERIFY ++ Addr

YES YES

Last NO
FAIL Addr

YES

RESET MARGIN MODE

CHECK ALL BYTES

1st: VCC = 6V
2nd: VCC = 4.2V

AI00738B

PRESTO IIB Programming Algorithm

PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 6.5 seconds. This can
be achieved with STMicroelectronics M27C512
due to several design innovations described in the
M27C512 datasheet to improve programming effi-
ciency and to provide adequate margin for reliabil-
ity. Before starting the programming the internal
MARGIN MODE circuit is set in order to guarantee
that each cell is programmed with enough margin.
Then a sequence of 100µs program pulses are
applied to each byte until a correct verify occurs.
No overprogram pulses are applied since the verify
in MARGIN MODE provides the necessary margin.
Program Inhibit
Programming of multiple M27C512s in parallel with
different data is also easily accomplished. Except
for E, all like inputs including GVPP
M27C512

ORDERING INFORMATION SCHEME

Example: M27C512 -70 X C 1 TR

Speed VCC Tolerance Package Temperature Range Option

-45 (1)
45 ns X ± 5% F FDIP28W 1 0 to 70 °C X Additional
± 10% –40 to 85 °C Burn-in
-60 60 ns blank B PDIP28 6
–40 to 125 °C TR Tape & Reel
-70 70 ns C PLCC32 3
Packing
-80 80 ns N TSOP28
8 x 13.4mm
-90 90 ns
-10 100 ns
-12 120 ns
-15 150 ns
-20 200 ns
-25 250 ns

Note: 1. High Speed, see AC Characteristics section for further information

For a list of available options (Speed, V CC Tolerance, Package, etc...) or for further information on any
aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.

10/15
 M27C512

FDIP28W - 28 pin Ceramic Frit-seal DIP, with window

mm inches
Symb
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 36.50 37.34 1.437 1.470
D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N 28 28

A2 A3 A

A1 L α
B1 B e C
eA
D2
eB
D
S
N

∅ E1 E

1
FDIPW-a

Drawing is not to scale

11/15
M27C512

PDIP28 - 28 pin Plastic DIP, 600 mils width

mm inches
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 36.83 37.34 1.450 1.470
D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α 0° 10° 0° 10°
N 28 28

A2 A

A1 L α
B1 B e1 C
eA
D2 eB

D
S
N

E1 E

1
PDIP

Drawing is not to scale

12/15
 M27C512

PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular

mm inches
Symb
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N 32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004

D A1
D1 A2

1 N
B1

E1 E e
Ne F D2/E2
B
0.51 (.020)

1.14 (.045)

Nd A

R CP
PLCC

Drawing is not to scale

13/15
M27C512

TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm

mm inches
Symb
Typ Min Max Typ Min Max
A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469
E 7.90 8.10 0.311 0.319
e 0.55 – – 0.022 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N 28 28
CP 0.10 0.004

A2

22 21
e

28
1 E

B
7 8

D1 A
D CP

DIE

TSOP-c A1 α L

Drawing is not to scale

14/15
 M27C512

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

© 1998 STMicroelectronics - All Rights Reserved

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