M27C4001

4 Mbit (512Kb x 8) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION
■ FAST ACCESS TIME: 35ns
■ LOW POWER CONSUMPTION: 32 32

– Active Current 30mA at 5MHz

1 1
– Standby Current 100µA
FDIP32W (F) PDIP32 (B)
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/byte (typical)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 41h
LCCC32W (L)
DESCRIPTION
The M27C4001 is a 4 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs and
is organised as 524,288 by 8 bits. TSOP32 (N)
PLCC32 (C) 8 x 20 mm
The FDIP32W (window ceramic frit-seal package)
and LCCC32W (leadless chip carrier package)
have a transparent lid which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
Figure 1. Logic Diagram
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the VCC VPP
M27C4001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20mm) packages.
19 8
A0-A18 Q0-Q7
Table 1. Signal Names
A0-A18 Address Inputs
E M27C4001
Q0-Q7 Data Outputs
G
E Chip Enable

G Output Enable

VPP Program Supply

VCC Supply Voltage VSS

AI00721B

VSS Ground

July 1998 1/16

M27C4001

Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections

VPP 1 32 VCC

VCC
VPP
A12
A15
A16

A18
A17
A16 2 31 A18
A15 3 30 A17
A12 4 29 A14 1 32
A7 5 28 A13 A7 A14
A6 A13
A6 6 27 A8
A5 7 26 A9 A5 A8
A4 A9
A4 8 25 A11
M27C4001 A3 9 M27C4001 25 A11
A3 9 24 G
A2 10 23 A10 A2 G
A1 A10
A1 11 22 E
A0 12 21 Q7 A0 E
Q0 Q7
Q0 13 20 Q6
17
Q1 14 19 Q5

Q1
Q2
VSS
Q3
Q4
Q5
Q6
Q2 15 18 Q4
VSS 16 17 Q3
AI00723
AI00722

Figure 2C. TSOP Pin Connections DEVICE OPERATION

The operating modes of the M27C4001 are listed
in the Operating Modes table. A single power sup-
ply is required in the read mode. All inputs are TTL
levels except for VPP and 12V on A9 for Electronic
A11 1 32 G Signature.
A9 A10 Read Mode
A8 E The M27C4001 has two control functions, both of
A13 Q7 which must be logically active in order to obtain
A14 Q6 data at the outputs. Chip Enable (E) is the power
A17 Q5
control and should be used for device selection.
Output Enable (G) is the output control and should
A18 Q4 be used to gate data to the output pins, indepen-
VCC 8 M27C4001 25 Q3 dent of device selection. Assuming that the ad-
VPP 9 (Normal) 24 VSS dresses are stable, the address access time
A16 Q2 (tAVQV) is equal to the delay from E to output
A15 Q1
(tELQV). Data is available at the output after a delay
of t GLQV from the falling edge of G, assuming that
A12 Q0 E has been low and the addresses have been sta-
A7 A0 ble for at least tAVQV-tGLQV.
A6 A1 Standby Mode
A5 A2 The M27C4001 has a standby mode which reduc-
A4 16 17 A3 es the supply current from 30mA to 100µA. The
AI01155B M27C4001 is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.

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 M27C4001

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit

TA Ambient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.

Table 3. Operating Modes (1)

Mode E G A9 Vpp Q0 - Q7

Read VIL VIL X VCC or VSS Data Out

Output Disable VIL V IH X VCC or VSS Hi-Z

Program VIL Pulse V IH X VPP Data In

Verify VIH VIL X VPP Data Out

Program Inhibit VIH V IH X VPP Hi-Z

Standby VIH X X VCC or VSS Hi-Z

Electronic Signature VIL VIL VID VCC Codes

Note: 1. X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h

Electronic Signature VIH 0 1 0 0 0 0 0 1 41h

Two Line Output Control For the most efficient use of these two control
Because EPROMs are usually used in larger lines, E should be decoded and used as the prima-
memory arrays, this product features a 2 line con- ry device selecting function, while G should be
trol function which accommodates the use of mul- made a common connection to all devices in the
tiple memory connection. The two line control array and connected to the READ line from the
function allows: system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
a. the lowest possible memory power dissipation,
mode and that the output pins are only active
b. complete assurance that output bus contention when data is required from a particular memory
will not occur. device.

3/16
M27C4001

Table 5. AC Measurement Conditions

High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4 to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8 and 2V

Figure 3. Testing Input Output Waveform Figure 4. AC Testing Load Circuit

1.3V
High Speed

1N914
3V

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V

0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit
C IN Input Capacitance V IN = 0V 6 pF

COUT Output Capacitance VOUT = 0V 12 pF

Note: 1. Sampled only, not 100% tested.

System Considerations control and by properly selected decoupling ca-

The power switching characteristics of Advanced pacitors. It is recommended that a 0.1µF ceramic
CMOS EPROMs require careful decoupling of the capacitor be used on every device between VCC
devices. The supply current, ICC, has three seg- and VSS. This should be a high frequency capaci-
ments that are of interest to the system designer: tor of low inherent inductance and should be
the standby current level, the active current level, placed as close to the device as possible. In addi-
and transient current peaks that are produced by tion, a 4.7µF bulk electrolytic capacitor should be
the falling and rising edges of E. The magnitude of used between VCC and VSS for every eight devic-
the transient current peaks is dependent on the es. The bulk capacitor should be located near the
capacitive and inductive loading of the device at power supply connection point. The purpose of the
the output. bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
The associated transient voltage peaks can be
suppressed by complying with the two line output

4/16
 M27C4001

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

E = VIL, G = V IL,
ICC Supply Current 30 mA
IOUT = 0mA, f = 5MHz

ICC1 Supply Current (Standby) TTL E = VIH 1 mA

ICC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA

IPP Program Current VPP = VCC 10 µA

V IL Input Low Voltage –0.3 0.8 V

VIH (2) Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

Output High Voltage TTL IOH = –400µA 2.4 V

VOH
Output High Voltage CMOS IOH = –100µA V CC – 0.7 V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M24C4001

Symbol Alt Parameter Test Condit ion -35 (3) -45 (3) -55 (3) Unit

Min Max Min Max Min Max

Address Valid to
tAVQV tACC E = VIL, G = VIL 35 45 55 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 35 45 55 ns
Output Valid
Output Enable Low to
tGLQV tOE E = VIL 20 25 30 ns
Output Valid
Chip Enable High to
t EHQZ (2) tDF G = VIL 0 30 0 30 0 30 ns
Output Hi-Z
Output Enable High to
tGHQZ (2) tDF E = VIL 0 30 0 30 0 30 ns
Output Hi-Z
Address Transition to
tAXQX tOH E = VIL, G = VIL 0 0 0 ns
Output Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.

5/16
M27C4001

Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C4001
Symbol Alt Parameter Test Conditi on -70 -80/-90 -10/-12/-15 Unit
Min Max Min Max Min Max
Address Valid to
tAVQV tACC E = VIL, G = VIL 70 80 100 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 70 80 100 ns
Output Valid
Output Enable Low to
tGLQV tOE E = VIL 35 40 50 ns
Output Valid
Chip Enable High to
t EHQZ (2) tDF G = VIL 0 30 0 30 0 30 ns
Output Hi-Z
Output Enable High to
tGHQZ (2) tDF E = VIL 0 30 0 30 0 30 ns
Output Hi-Z
Address Transition to
tAXQX tOH E = VIL, G = VIL 0 0 0 ns
Output Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A18 VALID VALID

tAVQV tAXQX

tEHQZ
tGLQV

tELQV tGHQZ

Hi-Z
Q0-Q7

AI00724B

Programming change a ’0’ to a ’1’ is by die exposition to ultravio-

When delivered (and after each erasure for UV let light (UV EPROM). The M27C4001 is in the
EPROM), all bits of the M27C4001 are in the ’1’ programming mode when VPP input is at 12.75V,
state. Data is introduced by selectively program- G is at VIH and E is pulsed to VIL. The data to be
ming ’0’s into the desired bit locations. Although programmed is applied to 8 bits in parallel to the
only ’0’s will be programmed, both ’1’s and ’0’s can data output pins. The levels required for the ad-
be present in the data word. The only way to dress and data inputs are TTL. VCC is specified to
be 6.25V ± 0.25V.

6/16
 M27C4001

Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Parameter Test Conditio n Min Max Unit
ILI Input Leakage Current 0 ≤ V IN ≤ VCC ±10 µA

ICC Supply Current 50 mA

IPP Program Current E = VIL 50 mA

V IL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL I OH = –400µA 2.4 V

VID A9 Voltage 11.5 12.5 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.

Table 10. Programming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVEL tAS Address Valid to Chip Enable Low 2 µs

tQVEL tDS Input Valid to Chip Enable Low 2 µs

tVPHEL tVPS VPP High to Chip Enable Low 2 µs

tVCHEL tVCS VCC High to Chip Enable Low 2 µs

tELEH tPW Chip Enable Program Pulse Width 95 105 µs

Chip Enable High to Input

t EHQX tDH 2 µs
Transition
Input Transion to Output Enable
tQXGL t OES 2 µs
Low
tGLQV tOE Output Enable Low to Output Valid 100 ns

tGHQZ tDFP Output Enable High to Output Hi-Z 0 130 ns

Output Enable High to Address

t GHAX tAH 0 ns
Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.

7/16
M27C4001

Figure 6. Programming and Verify Modes AC Waveforms

A0-A18 VALID

tAVPL

Q0-Q7 DATA IN DATA OUT

tQVEL tEHQX

VPP

tVPHEL tGLQV tGHQZ

VCC

tVCHEL tGHAX

E
tELEH tQXGL

PROGRAM VERIFY
AI00725

Figure 7. Programming Flowchart PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. Pro-
VCC = 6.25V, VPP = 12.75V gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
n=0
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
E = 100µs Pulse guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
NO
since the verify in MARGIN MODE provides the
++n NO necessary margin to each programmed cell.
= 25 VERIFY ++ Addr
Program Inhibit
YES YES Programming of multiple M27C4001s in parallel
with different data is also easily accomplished. Ex-
Last NO
cept for E, all like inputs including G of the parallel
FAIL Addr M27C4001 may be common. A TTL low level
pulse applied to a M27C4001’s E input, with VPP
YES at 12.75V, will program that M27C4001. A high
level E input inhibits the other M27C4001s from
CHECK ALL BYTES
1st: VCC = 6V
being programmed.
2nd: VCC = 4.2V Program Verify
A verify (read) should be performed on the pro-
AI00760B
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.

8/16
 M27C4001

On-Board Programming ERASURE OPERATION (applies to UV EPROM)

The M27C4001 can be directly programmed in the The erasure characteristics of the M27C4001 are
application circuit. See the relevant Application such that erasure begins when the cells are ex-
Note AN620. posed to light with wavelengths shorter than ap-
Electronic Signature proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
The Electronic Signature (ES) mode allows the
wavelengths in the 3000-4000 Å range. Data
reading out of a binary code from an EPROM that shows that constant exposure to room level fluo-
will identify its manufacturer and type. This mode
rescent lighting could erase a typical M27C4001 in
is intended for use by programming equipment to
about 3 years, while it would take approximately 1
automatically match the device to be programmed
week to cause erasure when exposed to direct
with its corresponding programming algorithm.
sunlight. If the M27C4001 is to be exposed to
The ES mode is functional in the 25°C ± 5°C am-
these types of lighting conditions for extended pe-
bient temperature range that is required when pro-
riods of time, it is suggested that opaque labels be
gramming the M27C4001. To activate the ES
put over the M27C4001 window to prevent unin-
mode, the programming equipment must force
tentional erasure. The recommended erasure pro-
11.5V to 12.5V on address line A9 of the
cedure for the M27C4001 is exposure to short
M27C4001 with VPP=VCC=5V. Two identifier wave ultraviolet light which has wavelength of
bytes may then be sequenced from the device out-
2537 Å. The integrated dose (i.e. UV intensity x
puts by toggling address line A0 from VIL to VIH. All
exposure time) for erasure should be a minimum
other address lines must be held at V IL during
of 15 W-sec/cm2. The erasure time with this dos-
Electronic Signature mode. Byte 0 (A0=VIL) repre- age is approximately 15 to 20 minutes using an ul-
sents the manufacturer code and byte 1 (A0=VIH)
traviolet lamp with 12000 µW/cm2 power rating.
the device identifier code.
The M27C4001 should be placed within 2.5 cm (1
For the STMicroelectronics M27C4001, these two inch) of the lamp tubes during the erasure. Some
identifier bytes are given in Table 4 and can be lamps have a filter on their tubes which should be
read-out on outputs Q0 to Q7. removed before erasure.

9/16
M27C4001

Table 11. Ordering Information Scheme

Example: M27C4001 -45 X C 1 TR

Device Type

Operating Voltage
C = 5V

Speed
-35 (1)= 35 ns
-45 (1)= 45 ns
(1)
-55 = 55 ns
-70 = 70 ns
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns

V CC Tolerance
blank = ± 10%
X = ± 5%

Package
F = FDIP32W
L = LCCC32W
B = PDIP32
C = PLCC32
N = TSOP32: 8 x 20mm

Temperature Range
1 = –0 to 70 °C
6 = –40 to 85 °C

Optio n
X = Additional Burn-in
TR =Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.

10/16
 M27C4001

Table 12. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 41.73 42.04 1.643 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
Ø 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N 32 32

Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline

A2 A3 A

A1 L α
B1 B e C
eA
D2
eB
D
S
N

∅ E1 E

1
FDIPW-a

Drawing is not to scale.

11/16
M27C4001

Table 13. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 41.78 42.04 1.645 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.03 0.070 0.080
α 0° 10° 0° 10°
N 32 32

Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline

A2 A

A1 L α
B1 B e1 C
eA
D2 eB

D
S
N

E1 E

1
PDIP

Drawing is not to scale.

12/16
 M27C4001

Table 14. LCCC32W - 32 lead Leadless Ceramic Chip Carrier rectangular window,
Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 2.80 0.110
B 0.51 0.71 0.020 0.028
D 11.53 11.63 0.442 0.458

E 13.72 14.22 0.540 0.560

e 1.27 – – 0.050 – –
e1 0.39 – 0.015 –
e2 7.62 – – 0.300 – –
e3 10.16 – – 0.400 – –
h 1.02 – – 0.040 – –
j 0.51 – – 0.020 – –
L 1.14 1.40 0.045 0.055
L1 1.96 2.36 0.077 0.093

K 10.50 10.80 0.413 0.425

K1 8.03 8.23 0.316 0.324
N 32 32

Figure 10. LCCC32W - 32 lead Leadless Ceramic Chip Carrier rectangular window, Package Outline

e2
D e j x 45o

N
1
L1
K E e3 e1
B

K1

A h x 45o L

LCCCW-a

Drawing is not to scale.

13/16
M27C4001

Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N 32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004

Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline

D A1
D1 A2

1 N
B1

Ne E1 E D2/E2 e
F
B
0.51 (.020)

1.14 (.045)

Nd A

R CP
PLCC

Drawing is not to scale.

14/16
 M27C4001

Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max

A 1.20 0.047
A1 0.05 0.17 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728

E 7.90 8.10 0.311 0.319

e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N 32 32
CP 0.10 0.004

Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L

Drawing is not to scale.

15/16
M27C4001

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.

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