RT3663BC RichTek

®
RT3663BC
Dual-Output PWM Controller with 3 Integrated Drivers for

AMD SVI2 Mobile CPU Power Supply
General Description Features
The RT3663BC is a 3 + 2 phases PWM controller, and is  3/2/1-Phase (VDD) + 2/1/0-Phase (VDDNB) PWM
compliant with AMD SVI2 Voltage Regulator Specification Controller
to support both CPU core (VDD) and Northbridge portion  3 Embedded MOSFET Drivers
of the CPU (VDDNB). The RT3663BC features CCRCOT  G-NAVPTM Topology
(Constant Current Ripple Constant On-Time) with G-NAVP  Support Dynamic Load-Line and Zero Load-Line
(Green-Native AVP), which is Richtek's proprietary  Diode Emulation Mode at Light Load Condition
topology. The G-NAVP makes it an easy setting controller  SVI2 Interface to Comply with AMD Power
to meet all AMD AVP (Adaptive Voltage Positioning) VDD/ Management Protocol
VDDNB requirements. The droop is easily programmed  Built-In ADC for VOUT and IOUT Reporting
by setting the DC gain of the error amplifier. With proper  Immediate OV, UV and NV Protections and UVLO
compensation, the load transient response can achieve  Programmable Dual OCP Mechanism
optimized AVP performance. The controller also uses the  0.5% DAC Accuracy
interface to issue VOTF Complete and to send digitally  Fast Transient Response
encoded voltage and current values for the VDD and  Power Good Indicator
VDDNB domains. It can operate in single phase and diode  Over-Current Indicator
emulation mode and reach up to 90% efficiency in different
modes according to different loading conditions. The Applications
RT3663BC provides special purpose offset capabilities by  AMD SVI2 Mobile CPU
pin setting. The RT3663BC also provides power good  Laptop Computer
indication, over-current indication (OCP_L) and dual OCP
mechanism for AMD SVI2 CPU core and NB. It also
features complete fault protection functions including over-
voltage, under-voltage and negative-voltage protections.
Simplified Application Circuit
RT3663BC
OCP_L PHASE1 MOSFET VVDD
PHASE2 MOSFET
SVC
To CPU PWM3 RT9610 MOSFET
SVD
PHASEA1 MOSFET VVDDNB
SVT PWMA2 RT9610 MOSFET
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS3663BC-03 August 2019 www.richtek.com

1
RT3663BC
Ordering Information Pin Configuration
RT3663BC (TOP VIEW)
Package Type
TONSETA
UGATEA1
PHASEA1
LGATEA1
BOOTA1
UGATE1
PHASE2
PHASE1
LGATE2
LGATE1
PWMA2
BOOT1
QW : WQFN-52L 6x6 (W-Type)
PVCC
Lead Plating System
G : Green (Halogen Free and Pb Free) 52 51 50 49 48 47 46 45 44 43 42 41 40
Note : UGATE2 1 39 PGOOD

Richtek products are : BOOT2 2 38 PGOODA
PWM3 3 37 EN
 RoHS compliant and compatible with the current require- TONSET 4 36 ISENA1P
ments of IPC/JEDEC J-STD-020. ISEN2P 5 35 ISENA1N
ISEN2N 6 34 ISENA2N
 Suitable for use in SnPb or Pb-free soldering processes. ISEN1N 7 GND 33 ISENA2P
ISEN1P 8 32 VSENA
ISEN3P 9 31 FBA
ISEN3N 10 53 30 COMPA
Marking Information VSEN 11 29 IBIAS
RT3663BCGQW : Product Number FB 12 28 VCC
COMP 13 27 OCP_L
RT3663BC YMDNN : Date Code
14 15 16 17 18 19 20 21 22 23 24 25 26
GQW
IMONA
PWROK
OFS
OFSA
SVT
V064/SET3
VDDIO
SET1
SET2
RGND
IMON
SVC
SVD
YMDNN
WQFN-52L 6x6
www.richtek.com DS3663BC-03 August 2019

2
RT3663BC
Functional Pin Description
Pin No. Pin Name Pin Function
3 PWM3 PWM outputs for Channel 3 VDD controller.
VDD controller on-time setting. Connect this pin to the converter input
4 TONSET voltage, VIN, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
5, 8, 9 ISEN1P to ISEN3P Positive current sense input of Channel 1, 2 and 3 for VDD controller.
6, 7, 10 ISEN1N to ISEN3N Negative current sense input of Channel 1, 2 and 3 for VDD controller.
VDD controller voltage sense input. This pin is connected to the terminal of
11 VSEN
VDD controller output voltage.
Output voltage feedback input of VDD controller. This pin is the negative
12 FB
input of the error amplifier for the VDD controller.
13 COMP Compensation node of the VDD controller.
Return ground of VDD and VDDNB controller. This pin is the common
14 RGND negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
Current monitor output for the VDD controller. This pin outputs a voltage
15 IMON
proportional to the output current.
This pin provides two functions: fixed 0.64v reference voltage output and
current gain ratio setting for VDD and VDDNB controller. Connect a
resistive voltage divider from VCC to GND and connect the joint of the
16 V064/SET3 voltage divider to this pin for current gain ratio setting. The pin also used to
offset the output voltage of the IMON pin and the IMONA pin. Bypass this
pin to GND with a 22nF ceramic capacitor for noise decoupling and pin
setting accuracy.
Current monitor output for the VDDNB controller. This pin outputs a voltage
17 IMONA
proportional to the output current.
Processor memory interface power rail and serves as the reference for
18 VDDIO PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System power good input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
19 PWROK
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
20 SVC Serial VID clock input from processor.
21 SVD Serial VID data input from processor. This pin is a serial data line.
22 SVT Serial VID telemetry input from VR. This pin is a push-pull output.
23 OFS Over clocking offset setting for the VDD controller.
24 OFSA Over clocking offset setting for the VDDNB controller.
1st platform setting. Platform can use this pin to set OCP_TDC threshold,
25 SET1
DVID compensation bit1 and internal ramp slew rate.
2nd platform setting. Platform can use this pin to set quick response
26 SET2 threshold, OCP_TDC trigger delay time, DVID compensation bit0 and over
clocking offset enable setting.
Over-current indicator for dual OCP mechanism. This pin is an open-drain
27 OCP_L
output.

3
RT3663BC
Pin No. Pin Name Pin Function
Controller power supply input. Connect this pin to 5V with an 1F or greater
28 VCC
ceramic capacitor for decoupling.
Internal bias current setting. Connect only a 100k resistor from this pin to
29 IBIAS GND to generate bias current for internal circuit. Place this resistor as close to
the IBIAS pin as possible.
30 COMPA Compensation node of the VDDNB controller.
Output voltage feedback input of VDDNB controller. This pin is the negative
31 FBA
input of the error amplifier for the VDDNB controller.
VDDNB controller voltage sense input. This pin is connected to the terminal of
32 VSENA
VDDNB controller output voltage.
ISENA2P,
33, 36 Positive current sense input of Channel 1 and 2 for VDDNB controller.
ISENA1P
ISENA2N,
34, 35 Negative current sense input of Channel 1 and 2 for VDDNB controller.
ISENA1N
37 EN Controller enable control input. A logic high signal enables the controller.
Power good indicator for the VDDNB controller. This pin is an open-drain
38 PGOODA
output.
39 PGOOD Power good indicator for the VDD controller. This pin is an open-drain output.
VDDNB controller on-time setting. Connect this pin to the converter input
40 TONSETA voltage, VIN, through a resistor, RTONNB, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
41 PWMA2 PWM output for Channel 2 of VDDNB controller.
BOOT1,
Bootstrap supply for high-side MOSFET. This pin powers high-side MOSFET
46, 2, 42 BOOT2,
driver.
BOOTA1
UGATE1,
47, 1, 43 UGATE2, High-side gate driver outputs. Connect this pin to Gate of high-side MOSFET.
UGATEA1
PHASE1,
Switch nodes of high-side driver. Connect this pin to high-side MOSFET
48, 52, 44 PHASE2,
Source together with the low-side MOSFET Drain and the inductor.
PHASEA1
LGATE1,
49, 51, 45 LGATE2, Low-side gate driver outputs. This pin drives the Gate of low-side MOSFET.
LGATEA1
50 PVCC Driver power. Connect this pin to GND by ceramic capacitor larger than 1F.
Ground. The exposed pad must be soldered to a large PCB and connected to
53 (Exposed Pad) GND
GND for maximum power dissipation.

4
RT3663BC
Functional Block Diagram
PGOODA
PWROK
PGOOD
VSENA
OCP_L
VDDIO
OFSA
VSEN
SET1
SET2
VCC
OFS
SVD
SVT
SVC
EN
IMONAI
IMONI
SET3
UVLO
MUX GND
ADC
SVI2 Interface OFS/OFSA

IBIAS Loop Control
Configuration Registers
Load Line Protection Logic
Control Logic /Load Line A
From Control Logic
RSET/RSETA
RGND TONSETA
DAC OCP Threshold
ERROR PWMA2
Soft-Start & Slew VSETA AMP
+ Offset + TON
Rate Control BOOTA1
- Cancellation + - QRA GENA PWMA1
PWM UGATEA1
CMPA 1-PH
FBA TONA Driver PHASEA1
COMPA Current mirror 0.4 x Ai_VDDNB
LGATEA1
ISENA1P +
x2 IBA1 +
ISENA1N - V064 Current
-
Balance
Current mirror RSETA
ISENA2P + Average IMONAI IBA1 IBA2
x2 IBA2
ISENA2N -
Driver
PVCC
IMONA + OCA POR
OCP_TDCA, To Protection Logic
OCP_SPIKEA -
From Control Logic
VSENA OV/UV/NV TONSET
RGND DAC
ERROR PWM1 BOOTx
Soft-Start & Slew Rate AMP UGATEx
VSET Offset 2-PH
Control + + PWM2
Cancellation TON Driver PHASEx
FB - + - GEN LGATEx
PWM QR
COMP CMP PWM3
Current mirror TON
ISEN1P + 0.4 x Ai_VDD
x1 IB1
ISEN1N - +
-
Current mirror RSET
V064
ISEN2P +
x1 IB2
ISEN2N - Current Balance
Average IMONI
Current mirror IB1 IB2 IB3
ISEN3P +
x1 IB3
ISEN3N -
SET3
+ OC
OCP_TDC, To Protection Logic
-
OCP_SPIKE
VSEN OV/UV/NV
IMON V064/SET3

5
RT3663BC
Operation
MUX and ADC Error Amplifier
The MUX supports the inputs from SET1, SET2, SET3, The Error amplifier generates COMP/COMPA signal by
OFS, OFSA, IMON, IMONA, VSEN, or VSENA. The ADC the difference between VSET/VSETA and FB/FBA.
converts these analog signals to digital codes for reporting
or performance adjustment. Offset Cancellation
This block cancels the output offset voltage from voltage
SVI2 Interface ripple and current ripple to achieve accurate output voltage.
The SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with CPU. The RT3663BC's performance PWM CMPx
and behavior can be adjusted by commands sent by CPU The PWM comparator compares COMP signal and current
or platform. feedback signal to generate a signal for TONGENx.
UVLO TONGEN/TONGENA
The UVLO detects the VCC pin voltages for under voltage This block generates an on-time pulse which high interval
lockout protection and power on reset operation. is based on the on-time setting and current balance.
Loop Control Protection Logic Current Balance

Loop control protection logic detects EN and UVLO signals Per-phase current is sensed and adjusted by adjusting
to initiate soft-start function and control PGOOD, on-time of each phase to achieve current balance for each
PGOODA and OCP_L signals after soft-start is finished. phase.
When dual OCP event occurs, the OCP_L pin voltage is
OC/OV/UV/NV
pulled low.
VSEN/VSENA and output current are sensed for over-
DAC current, over-voltage, under-voltage, and negative-voltage
The DAC receives VID codes from the SVI2 control logic protections.
to generate an internal reference voltage (VSET/VSETA)
RSET/RSETA
for controller.
The Ramp generator is designed to improve noise immunity
Soft-Start and Slew-Rate Control and reduce jitter.
This block controls the slew rate of the internal reference
voltage when output voltage changes.

6
RT3663BC
Table 1. Serial VID Codes
SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V)
0000_0000 1.55000 0010_0111 1.30625 0100_1110 1.06250 0111_0101 0.81875
0000_0001 1.54375 0010_1000 1.30000 0100_1111 1.05625 0111_0110 0.81250
0000_0010 1.53750 0010_1001 1.29375 0101_0000 1.05000 0111_0111 0.80625
0000_0011 1.53125 0010_1010 1.28750 0101_0001 1.04375 0111_1000 0.80000
0000_0100 1.52500 0010_1011 1.28125 0101_0010 1.03750 0111_1001 0.79375
0000_0101 1.51875 0010_1100 1.27500 0101_0011 1.03125 0111_1010 0.78750
0000_0110 1.51250 0010_1101 1.26875 0101_0100 1.02500 0111_1011 0.78125
0000_0111 1.50625 0010_1110 1.26250 0101_0101 1.01875 0111_1100 0.77500
0000_1000 1.50000 0010_1111 1.25625 0101_0110 1.01250 0111_1101 0.76875
0000_1001 1.49375 0011_0000 1.25000 0101_0111 1.00625 0111_1110 0.76250
0000_1010 1.48750 0011_0001 1.24375 0101_1000 1.00000 0111_1111 0.75625
0000_1011 1.48125 0011_0010 1.23750 0101_1001 0.99375 1000_0000 0.75000
0000_1100 1.47500 0011_0011 1.23125 0101_1010 0.98750 1000_0001 0.74375
0000_1101 1.46875 0011_0100 1.22500 0101_1011 0.98125 1000_0010 0.73750
0000_1110 1.46250 0011_0101 1.21875 0101_1100 0.97500 1000_0011 0.73125
0000_1111 1.45625 0011_0110 1.21250 0101_1101 0.96875 1000_0100 0.72500
0001_0000 1.45000 0011_0111 1.20625 0101_1110 0.96250 1000_0101 0.71875
0001_0001 1.44375 0011_1000 1.20000 0101_1111 0.95625 1000_0110 0.71250
0001_0010 1.43750 0011_1001 1.19375 0110_0000 0.95000 1000_0111 0.70625
0001_0011 1.43125 0011_1010 1.18750 0110_0001 0.94375 1000_1000 0.70000
0001_0100 1.42500 0011_1011 1.18125 0110_0010 0.93750 1000_1001 0.69375
0001_0101 1.41875 0011_1100 1.17500 0110_0011 0.93125 1000_1010 0.68750
0001_0110 1.41250 0011_1101 1.16875 0110_0100 0.92500 1000_1011 0.68125
0001_0111 1.40625 0011_1110 1.16250 0110_0101 0.91875 1000_1100 0.67500
0001_1000 1.40000 0011_1111 1.15625 0110_0110 0.91250 1000_1101 0.66875
0001_1001 1.39375 0100_0000 1.15000 0110_0111 0.90625 1000_1110 0.66250
0001_1010 1.38750 0100_0001 1.14375 0110_1000 0.90000 1000_1111 0.65625
0001_1011 1.38125 0100_0010 1.13750 0110_1001 0.89375 1001_0000 0.65000
0001_1100 1.37500 0100_0011 1.13125 0110_1010 0.88750 1001_0001 0.64375
0001_1101 1.36875 0100_0100 1.12500 0110_1011 0.88125 1001_0010 0.63750
0001_1110 1.36250 0100_0101 1.11875 0110_1100 0.87500 1001_0011 0.63125
0001_1111 1.35625 0010_0110 1.11250 0110_1101 0.86875 1001_0100 0.62500
0010_0000 1.35000 0100_0111 1.10625 0110_1110 0.86250 1001_0101 0.61875
0010_0001 1.34375 0100_1000 1.10000 0110_1111 0.85625 1001_0110 0.61250
0010_0010 1.33750 0100_1001 1.09375 0111_0000 0.85000 1001_0111 0.60625
0010_0011 1.33125 0100_1010 1.08750 0111_0001 0.84375 1001_1000 0.60000
0010_0100 1.32500 0100_1011 1.08125 0111_0010 0.83750 1001_1001 0.59375
0010_0101 1.31875 0100_1100 1.07500 0111_0011 0.83125 1001_1010 0.58750
0010_0110 1.31250 0100_1101 1.06875 0111_0100 0.82500 1001_1011 0.58125

7
RT3663BC
SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V)
1001_1100 0.57500 1011_0101 * 0.41875 1100_1110 * 0.26250 1110_0111* 0.10625
1001_1101 0.56875 1011_0110 * 0.41250 1100_1111 * 0.25625 1110_1000* 0.10000
1001_1110 0.56250 1011_0111 * 0.40625 1101_0000 * 0.25000 1110_1001* 0.09375
1001_1111 0.55625 1011_1000 * 0.40000 1101_0001 * 0.24375 1110_1010* 0.08750
1010_0000 0.55000 1011_1001 * 0.39375 1101_0010 * 0.23750 1110_1011* 0.08125
1010_0001 0.54375 1011_1010 * 0.38750 1101_0011 * 0.23125 1110_1100* 0.07500
1010_0010 0.53750 1011_1011 * 0.38125 1101_0100 * 0.22500 1110_1101* 0.06875
1010_0011 0.53125 1011_1100 * 0.37500 1101_0101 * 0.21875 1110_1110* 0.06250
1010_0100 0.52500 1011_1101 * 0.36875 1101_0110 * 0.21250 1110_1111* 0.05625
1010_0101 0.51875 1011_1110 * 0.36250 1101_0111 * 0.20625 1111_0000* 0.05000
1010_0110 0.51250 1011_1111 * 0.35625 1101_1000 * 0.20000 1111_0001* 0.04375
1010_0111 0.50625 1100_0000 * 0.35000 1101_1001 * 0.19375 1111_0010* 0.03750
1010_1000 * 0.50000 1100_0001 * 0.34375 1101_1010 * 0.18750 1111_0011* 0.03125
1010_1001 * 0.49375 1100_0010 * 0.33750 1101_1011 * 0.18125 1111_0100* 0.02500
1010_1010 * 0.48750 1100_0011 * 0.33125 1101_1100 * 0.17500 1111_0101* 0.01875
1010_1011 * 0.48125 1100_0100 * 0.32500 1101_1101 * 0.16875 1111_0110* 0.01250
1010_1100 * 0.47500 1100_0101 * 0.31875 1101_1110 * 0.16250 1111_0111* 0.00625
1010_1101 * 0.46875 1100_0110 * 0.31250 1101_1111 * 0.15625 1111_1000* 0.00000
1010_1110 * 0.46250 1100_0111 * 0.30625 1110_0000* 0.15000 1111_1001* OFF
1010_1111 * 0.45625 1100_1000 * 0.30000 1110_0001* 0.14375 1111_1010* OFF
1011_0000 * 0.45000 1100_1001 * 0.29375 1110_0010* 0.13750 1111_1011* OFF
1011_0001 * 0.44375 1100_1010 * 0.28750 1110_0011* 0.13125 1111_1100* OFF
1011_0010 * 0.43750 1100_1011 * 0.28125 1110_0100* 0.12500 1111_1101* OFF
1011_0011 * 0.43125 1100_1100 * 0.27500 1110_0101* 0.11875 1111_1110* OFF
1011_0100 * 0.42500 1100_1101 * 0.26875 1110_0110* 0.11250 1111_1111* OFF
* Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes

8
RT3663BC
Table 2. SET1 Pin Setting for VDD Controller OCP_TDC threshold, DVID Compensation
and RSET under VCC5 = 5V
SET1 Pin SET1 Pin
Voltage OCP_TDC Voltage OCP_TDC
DVID DVID
Before (Respect Before (Respect
Compensation RSET Compensation RSET
Current to OCP_ Current to OCP_
[1] [1]
Injection SPIKE) Injection SPIKE)
VSET1 (mV) VSET1 (mV)
34 145% 836 145%
59 130% 861 130%
85 115% 886 115%
60% 0 60% 1
110 100% 911 100%
135 85% 936 85%
160 70% 961 70%
235 145% 1036 145%
260 130% 1061 130%
285 115% 1086 115%
70% 0 70% 1
310 100% 1112 100%
335 85% 1137 85%
360 70% 1162 70%
435 145% 1237 145%
460 130% 1262 130%
485 115% 1287 115%
75% 0 75% 1
510 100% 1312 100%
535 85% 1337 85%
560 70% 1362 70%
636 145% 1437 145%
661 130% 1462 130%
686 115% 1487 115%
Disable 0 Disable 1
711 100% 1512 100%
736 85% 1537 85%
761 70% 1562 70%

9
RT3663BC
Table 3. SET1 Pin Setting for VDDNB Controller OCP_TDCA threshold, DVIDA Compensation
and RSETA under VCC5 = 5V
SET1 Pin SET1 Pin
Voltage Voltage
OCP_TDCA OCP_TDCA
Difference DVIDA Difference DVIDA
(Respect to (Respect to
VSET1 (Before Compensation RSETA VSET1 (Before Compensation RSETA
OCP_ OCP_
and After [1] and After [1]
SPIKEA) SPIKEA)
Current Current
Injection) (mV) Injection) (mV)
34 145% 836 145%
59 130% 861 130%
85 115% 886 115%
60% 0 60% 1
110 100% 911 100%
135 85% 936 85%
160 70% 961 70%
235 145% 1036 145%
260 130% 1061 130%
285 115% 1086 115%
70% 0 70% 1
310 100% 1112 100%
335 85% 1137 85%
360 70% 1162 70%
435 145% 1237 145%
460 130% 1262 130%
485 115% 1287 115%
75% 0 75% 1
510 100% 1312 100%
535 85% 1337 85%
560 70% 1362 70%
636 145% 1437 145%
661 130% 1462 130%
686 115% 1487 115%
Disable 0 Disable 1
711 100% 1512 100%
736 85% 1537 85%
761 70% 1562 70%

10
RT3663BC
Table 4. SET2 Pin Setting for VDD Controller QR threshold,DVID Compensation
and OCP Trigger Delay under VCC5 = 5V
SET2 Pin Voltage QRTH DVID Compensation OCPTRGDELAY
Before Current Injection VSET2 (mV) (for VDD) [0] (for VDD/VDDNB)
19 10ms
72 40ms
Disable 0
122 10ms
172 40ms
222 10ms
272 40ms
39mV 0
323 10ms
373 40ms
423 10ms
473 40ms
47mV 0
523 10ms
573 40ms
623 10ms
673 40ms
55mV 0
723 10ms
773 40ms
823 10ms
874 40ms
Disable 1
924 10ms
974 40ms
1024 10ms
1074 40ms
39mV 1
1124 10ms
1174 40ms
1224 10ms
1274 40ms
47mV 1
1324 10ms
1375 40ms
1425 10ms
1475 40ms
55mV 1
1525 10ms
1575 40ms

11
RT3663BC
Table 5. SET2 Pin Setting for VDDNB Controller QR threshold,DVIDA Compensation
and External Offset Function under VCC5 = 5V
DVIDA
SET2 Pin Voltage Difference VSET2 QRTHA
OFSENABLE OFSAENABLE Compensation
(Before and After Current Injection) (mV) (for VDDNB)
[0]
19 Disable
72 39mV
0
122 47mV
172 55mV
0 0
222 Disable
272 39mV
1
323 47mV
373 55mV
1224 Disable
1274 39mV
0
1324 47mV
1375 55mV
1 1
1425 Disable
1475 39mV
1
1525 47mV
1575 55mV

12
RT3663BC
Table 6. DVID Boost Compensation Setting
DVID Compensation [1] DVID Compensation [0] DVID Boost Compensation
0 0 22.5mV
0 1 18mV
1 0 13.5mV
1 1 9mV
Table 7. V064/SET3 Pin Setting for VDD and VDDNB Controller Current Gain Ratio under VCC5 =5V
V064/SET3 Pin VDD Current VDDNB Current V064/SET3 Pin VDD Current VDDNB Current
Voltage (mV) Gain Ratio Gain Ratio Voltage (mV) Gain Ratio Gain Ratio
1650 0LL 2450 0LL
1750 25% 2550 25%
0LL 50%
1850 50% 2650 50%
1950 100% 2750 100%
2050 0LL 2850 0LL
2150 25% 2950 25%
25% 100%
2250 50% 3050 50%
2350 100% 3150 100%

13
RT3663BC
Absolute Maximum Ratings (Note 1)
 VCC to GND ---------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
 PVCC to GND -------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
 RGND to GND -------------------------------------------------------------------------------------------------------------- −0.3V to 0.3V
 TONSET, TONSETA to GND -------------------------------------------------------------------------------------------- −0.3V to 28V
 BOOTx to PHASEx
DC ----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V
< 100ns ---------------------------------------------------------------------------------------------------------------------- −5V to 7.5V
 PHASEx to GND
DC ----------------------------------------------------------------------------------------------------------------------------- −0.3V to 32V
< 100ns ---------------------------------------------------------------------------------------------------------------------- −10V to 38V
 LGATEx to GND
DC ----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V
< 100ns ---------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V
 UGATEx to PHASEx
DC ----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V
< 100ns ---------------------------------------------------------------------------------------------------------------------- −5V to 7.5V
 Other Pins ------------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V
 Power Dissipation, PD @ TA = 25°C
WQFN-52L 6x6 ------------------------------------------------------------------------------------------------------------ 3.77W
 Package Thermal Resistance (Note 2)
WQFN-52L 6x6, θJA ------------------------------------------------------------------------------------------------------- 26.5°C/W
WQFN-52L 6x6, θJC ------------------------------------------------------------------------------------------------------ 6.5°C/W
 Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
 Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
 Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)

 Supply Voltage, VCC, PVCC ------------------------------------------------------------------------------------------- 4.5V to 5.5V
 Input Voltage, VIN --------------------------------------------------------------------------------------------------------- 4.5V to 24V
 Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Power Supply
Supply Current IVCC VEN = 3V, not switching -- 12 -- mA
Shutdown Current ISHDN VEN = 0V -- -- 5 A
PVCC Supply Voltage VPVCC 4.5 -- 5.5 V
PVCC Supply Current IPVCC VBOOTx = 5V, not switching -- 150 -- A

14
RT3663BC
Driver Power On Reset (Driver POR)
VPOR_R PVCC rising -- 3.85 4.1
Driver POR Threshold V
VPOR_F PVCC falling 3.4 3.65 --
Driver POR Hysteresis VPOR_HYS -- 200 -- mV
Reference and DAC
VFB = 1.0000  1.5500
0.5 0 0.5 %SVID
(no load, CCM mode )
DC Accuracy VFB VFB = 0.8000  1.0000 5 0 5
VFB = 0.3000  0.8000 8 0 8 mV
VFB = 0.2500  0.3000 80 0 80
RGND Current
RGND Current IRGND EN = 3V, not switching -- 200 -- A
Slew Rate
Dynamic VID Slew Rate SR Set VID 7.5 12 -- mV/s
Error Amplifier
Input Offset VEAOFS -- -- 2 mV
DC Gain ADC RL = 47k 70 80 -- dB
Gain-Bandwidth Product GBW CLOAD = 5pF -- 10 -- MHz
Output Voltage Range VCOMP 0.3 -- 3.6 V
Maximum Source Current IEA, SRC 1 -- -- mA
Maximum Sink Current IEA, SNK 1 -- -- mA
Current Sense Amplifier
Input Offset Voltage VOSCS 0.2 -- 0.2 mV
Current Mirror Gain for
AMIRROR, VDD 97 -- 103 %
CORE
Current Mirror Gain for NB AMIRROR, VDDNB 194 -- 206 %
Internal Sum Current VDD controller current gain ratio
Ai, VDD -- 0.4 -- V/V
Sense DC Gain for CORE = 100%
Internal Sum Current VDDNB controller current gain
Ai, VDDNB -- 0.8 -- V/V
Sense DC Gain for NB ratio = 100%
Maximum Source Current ICS, SRC 0 < VFB < 2.35 100 -- -- A
Maximum Sink Current ICS, SNK 0 < VFB < 2.35 10 -- -- A
Zero Current Detection
Zero Current Detection
VZCD_TH VZCD_TH = GND  VPHASEx -- 1 -- mV
Threshold
Ton Setting
TONSETx Pin Minimum
VTON, MIN -- 0.5 -- V
Voltage
TONSETx TON tON IRTON = 80A, VFB = 1.1V 270 305 340 ns
TONSETx Input Current
IRTON VFB = 1.1V 25 -- 280 A
Range
Minimum TOFF tOFF -- 250 -- ns

15
RT3663BC
IBIAS
IBIAS Pin Voltage VIBIAS RIBIAS = 100k 1.97 2 2.03 V
V064
Reference Voltage Output V064 0.56 0.64 0.72 V
Sink Current Capability IV064, SNK V064 = 0.64V 800 -- -- A
Source Current Capability IV064, SRC -- -- 100 A
Board OFSx
VFB Limit VFB, LIMIT 0 -- 2.35 V
OFS Update Rate fOFS -- 50 -- kHz
Board Offset Resolution VOFS -- 6.25 -- mV
Logic Inputs
EN Input Logic-High VIH_EN 2 -- --
V
Voltage Logic-Low VIL_EN -- -- 0.8
Leakage Current of EN ILEK_EN 1 -- 1 A
SVC, SVD, Logic-High VIH_SVI Respect to VDDIO 70 -- 100
%
SVT, PWROK Logic-Low VIL_SVI Respect to VDDIO 0 -- 35
Hysteresis of SVC, SVD,
V Respect to VDDIO 10 -- -- %
SVT, PWROK Input Voltage HYS_SVI
Protection
Under-Voltage Lockout
VUVLO VCC falling edge 4 4.2 4.4 V
Threshold
Under-Voltage Lockout
VUVLO -- 100 -- mV
Hysteresis
Under-Voltage Lockout VCC rising above UVLO
tUVLO -- 3 -- s
Delay threshold
Over-Voltage Protection
VOVP 275 325 375 mV
Threshold
Over-Voltage Protection
tOVP VSEN rising above threshold -- 1 -- s
Delay
Under-Voltage Protection
VUVP Respect to VID voltage 575 500 425 mV
Threshold
Under-Voltage Protection
tUVP VSEN falling below threshold -- 3 -- s
Delay
Negative-Voltage
VNV -- 0 -- mV
Protection Threshold
IISENxN per-phase OCP
Per Phase OCP Threshold IOCP_PERPHASE -- 10 -- A
threshold.
Delay of Per Phase OCP tPHOCP -- 1 -- s
IOCP_SPIKE DCR = 1.1m, RSENSE = 1.1k,

OCP_SPIKE Threshold 63 75 86 A
RIMON = 34.3k
tOCPSPIKE
OCP_SPIKE Action Delay 6 -- 12 s
_ACTION_DLY

16
RT3663BC
tOCPTDC
OCP_TDC Action Delay 12 -- 24 s
_ACTION_DLY
OCP_L, PGOOD and PGOODA

Output Low Voltage at
VOCP_L IOCP_L = 4mA 0 -- 0.2 V
OCP_L
OCP_L Assertion Time tOCP_L 2 -- -- s
Output Low Voltage at VPGOOD,
IPGOOD = 4mA, IPGOODA = 4mA 0 -- 0.2 V
PGOOD, PGOODA VPGOODA,
PGOOD and PGOODA VTH_PGOOD
Respect to VBOOT -- 300 -- mV
Threshold Voltage VTH_PGOODA
PGOOD and PGOODA tPGOOD VSEN = VBOOT to
70 100 130 s
Delay Time tPGOODA PGOOD/PGOODA high
Current Report
Maximum Reported %IDD_SP
-- 100 --
Current (FFh = OCP) IKE_OCP
Minimum Reported Current %IDD_SP
-- 0 --
(00h) IKE_OCP
IDDSpike Current Accuracy -- -- 3 %
Voltage Report
Maximum Reported
-- 3.15 -- V
Voltage (0_00h)
Minimum Reported Voltage
-- 0 -- V
(1_F8h)
Voltage Accuracy 2 -- 2 LSB
PWM Driving Capability
PWMx Source Resistance RPWM_SRC -- 20 -- 
PWMx Sink Resistance RPWM_SNK -- 10 -- 
Switching Time
UGATEx Rise Time tUGATEr 3nF load -- 8 -- ns
UGATEx Fall Time tUGATEf 3nF load -- 8 -- ns
LGATEx Rise Time tLGATEr 3nF load -- 8 -- ns
LGATEx Fall Time tLGATEf 3nF load -- 4 -- ns
UGATEx Turn-On
tPDHU Outputs unloaded -- 20 -- ns
Propagation Delay
LGATEx Turn-On
tPDHL Outputs unloaded -- 20 -- ns
Propagation Delay
Output
UGATEx Driver Source
RUGATEsr 100mA source current -- 1 -- 
Resistance
UGATEx Driver Source
IUGATEsr VUGATE VPHASE = 2.5V -- 2 -- A
Current
UGATEx Driver Sink
Resistance
RUGATEsk 100mA sink current -- 1 -- 

17
RT3663BC
UGATEx Driver Sink
IUGATEsk VUGATE VPHASE = 2.5V -- 2 -- A
Current
LGATEx Driver Source
RLGATEsr 100mA source current -- 1 -- 
Resistance
LGATEx Driver Source
ILGATEsr VLGATE = 2.5V -- 2 -- A
Current
LGATEx Driver Sink
RLGATEsk 100mA sink current -- 0.5 -- 
Resistance
LGATEx Driver Sink
ILGATEsk VLGATE = 2.5V -- 4 -- A
Current
SVI2 Bus
SVC Frequency fSVC (Note 5) 0.1 -- 30 MHz
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Min. SVC frequency defined in electrical spec. is related with different application. As min. SVC < 1MHz, VR can't support
telemetry reporting function. As min. SVC < 400kHz, VR can't support telemetry reporting function and VOTF complete
function.

18
2.2 50 VDDIO
5V PVCC
2.2µF RT3663BC 18 2.2
VCC5 VDDIO
10 28 1µF
5V VCC 4.7k 4.7k 3.3V
2.2µF OCP_L 27
20k 19
VCC5 23 OFS
PWROK 10k 10k
20k 24 OFSA
VCC5
PGOOD 39
VCC5 124k 1k 25 SET1
PGOODA 38
43k 20
124k 1k 26 SVC
VCC5 SET2 21 To CPU
470 1.47k SVD
6.32k 0.1µF 6.32k 0.1µF
22
DS3663BC-03 August 2019

SVT
0 RIBIAS
29 100k
RTON IBIAS
4.7 150k 4 TONSET
VIN GND 53 (Exposed Pad)
0.1µF RTONNB
4.7 137k 40
VIN TONSETA 0
VSEN 11
0.1µF
22pF 270pF VVDD_SENSE
Typical Application Circuit
37 EN
Enable VSS_SENSE
VCC5 16 13 65.48k 10k
V064/SET3 COMP
22nF 18.7k
RNTC RIMON FB 12 VIN
7.999k 100k 18.432k 15
IMON 10 10
2.2 0.1µF
Copyright © 2019 Richtek Technology Corporation. All rights reserved.

46
16k BOOT1 270µF
0
UGATE1 47
RNTC RIMONA 0.36µH/1.1m
10.47k 100k 11.665k 17 48 VVDD
IMONA PHASE1
0 49 0
VVDDNB_SENSE LGATE1 1 1µF LOAD
32 VSENA 165 165
270pF 22pF
3.3nF
10k 51.28k POSCAP : 330µF x 4

30 ISEN1P 8
COMPA RSENSE1 MLCC : 22µF x 15
VSS_SENSE 31 FBA 1.1k
14 RGND ISEN1N 7
VIN 0.1µF
VIN
5V
10 10 0.1µF 2 2.2 0.1µF
2.2 BOOT2
BOOT VCC 270µF
270µF 0
0 1µF UGATE2 1
UGATE PGND 0.36µH/1.1m 
VVDDNB 0.36µH/1.1m PHASE2 52
PHASE PWM
41 PWMA2
51 0 1µF
1µF 0 LGATE2 1 165 165
LOAD 165 165 1 LGATE EN 5V
RT9610 3.3nF
3.3nF
33 ISEN2P 5
POSCAP : 330µF x 2 ISENA2P
RSENSEA1 RSENSE2
1.1k ISEN2N 6 1.1k
MLCC : 22µF x 10 34
ISENA2N
0.1µF 5V 0.1µF VIN
VIN
0.1µF 2.2 0.1µF
2.2 VCC BOOT
42 BOOTA1 270µF
270µF 1µF 0
0 43 PGND UGATE
UGATEA1 0.36µH/1.1m 
0.36µH/1.1m 3 PHASE
44 PWM3 PWM
PHASEA1 0
0 5V EN LGATE 1 1µF
1µF 45 165 165
165 165 1 LGATEA1 RT9610
3.3nF
3.3nF
36 ISEN3P 9
ISENA1P RSENSE3
RSENSEA2
1.1k 1.1k
35 ISEN3N 10
ISENA1N
0.1µF
is a registered trademark of Richtek Technology Corporation.

0.1µF
19
www.richtek.com
RT3663BC
RT3663BC
Typical Operating Characteristics
CORE VR Power On from EN CORE VR Power Off from EN
VDD VDD
(500mV/Div) (500mV/Div)
EN EN
(4V/Div) (4V/Div)
PGOOD PGOOD
(2V/Div) (2V/Div)
UGATE UGATE
(30V/Div) (30V/Div)
Boot VID = 1.1V Boot VID = 1.1V
Time (500μs/Div) Time (500μs/Div)
CORE VR OCP_TDC CORE VR OCP_SPIKE
I LOAD I LOAD
(40A/Div) (40A/Div)
OCP_L OCP_L
(2V/Div) (2V/Div)
PGOOD PGOOD
(2V/Div) (2V/Div)
UGATE1 UGATE1
(30V/Div) ILOAD = 20A to 60A (30V/Div) ILOAD = 25A to 80A
Time (5ms/Div) Time (10μs/Div)
CORE VR OVP and NVP CORE VR UVP
VDD VVDD
(1V/Div) (1V/Div)
PGOOD
PGOOD (2V/Div)
(2V/Div)
UGATE UGATE1
(50V/Div) (50V/Div)
LGATE
(10V/Div) LGATE1
VID = 1.1V (10V/Div) VID = 1.1V

20
RT3663BC
CORE VR Dynamic VID Up CORE VR Dynamic VID Up
VVDD VVDD
(1V/Div) (1V/Div)
I LOAD I LOAD
(5A/Div) (18A/Div)
SVD SVD
(2V/Div) (2V/Div)
SVT SVT
(2V/Div) VID = 0.4V to 1V, ILOAD = 3.6A (2V/Div) VID = 1V to 1.06875V, ILOAD = 18A
CORE VR Dynamic VID Up CORE VR Dynamic VID Up
VVDD VVDD
(1V/Div) (1V/Div)
I LOAD I LOAD
(18A/Div) (18A/Div)
SVD SVD
(2V/Div) (2V/Div)
SVT SVT
(2V/Div) VID = 1V to 1.1V, ILOAD = 18A (2V/Div) VID = 1V to 1.2V, ILOAD = 18A
CORE VR Dynamic VID Up CORE VR Load Transient
VVDD VVDD
(1V/Div) (50mV/Div)
I LOAD
(18A/Div)
SVD
(2V/Div)
SVT I LOAD
(2V/Div) VID = 1V to 1.4V, ILOAD = 18A (25A/Div) fLOAD = 10kHz, ILOAD = 18A to 50A

21
RT3663BC
CORE VR Load Transient NB VR Power On from EN
VVDD
(50mV/Div) VDDNB
(500mV/Div)
EN
(4V/Div)
PGOODA
(2V/Div)
UGATEA
I LOAD (30V/Div)
(25A/Div) fLOAD = 10kHz, ILOAD = 50A to 18A Boot VID = 1.1V
NB VR Power Off from EN NB VR OCP_TDC
VDDNB I LOAD
(500mV/Div) (25A/Div)
OCP_L
(2V/Div)
EN
(4V/Div)
PGOODA PGOODA
(2V/Div) (2V/Div)
UGATEA
(30V/Div) UGATEA1
Boot VID = 1.1V (50V/Div) ILOAD = 10A to 45A
Time (500μs/Div) Time (5ms/Div)
NB VR OCP_SPIKE NB VR OVP and NVP
I LOAD VDDNB
(40A/Div) (1V/Div)
OCP_L
(2V/Div) PGOODA
(2V/Div)
PGOODA UGATEA
(2V/Div) (50V/Div)
UGATEA1 LGATEA
(50V/Div) (10V/Div)
ILOAD = 20A to 60A VID = 1.1V

22
RT3663BC
NB VR UVP NB VR Dynamic VID Up
V VDDNB
(1V/Div)
V VDDNB
(1V/Div)
I LOAD
PGOODA (5A/Div)
(2V/Div)
SVD
(2V/Div)
UGATEA1
(50V/Div)
LGATEA1 SVT
(10V/Div) VID = 1.1V (2V/Div) VID = 0.4V to 1V, ILOAD = 2.5A
NB VR Dynamic VID Up NB VR Dynamic VID Up
V VDDNB V VDDNB
(1V/Div) (1V/Div)
I LOAD I LOAD
(8A/Div) (8A/Div)
SVD SVD
(2V/Div) (2V/Div)
SVT SVT
(2V/Div) VID = 1V to 1.06875V, ILOAD = 12.5A (2V/Div) VID = 1V to 1.1V, ILOAD = 12.5A
NB VR Dynamic VID Up NB VR Dynamic VID Up
V VDDNB V VDDNB
(1V/Div) (1V/Div)
I LOAD I LOAD
(8A/Div) (8A/Div)
SVD SVD
(2V/Div) (2V/Div)
SVT SVT
(2V/Div) VID = 1V to 1.2V, ILOAD = 12.5A (2V/Div) VID = 1V to 1.4V, ILOAD = 12.5A

23
RT3663BC
NB VR Load Transient NB VR Load Transient
V VDDNB V VDDNB
(40mV/Div) (40mV/Div)
I LOAD I LOAD
(20A/Div) fLOAD = 10kHz, ILOAD = 13A to 33A (20A/Div) fLOAD = 10kHz, ILOAD = 33A to 13A

24
RT3663BC
Application Information
Power Ready (POR) Detection
During start-up, the RT3663BC detects the voltage at the Current
Mirror
voltage input pins : VCC, PVCC and EN. When VCC >
2V
4.2V and PVCC > 3.85V, the IC recognizes the power
+
+
-
state of system to be ready (POR = high) and wait for -
enable command at the EN pin. After POR = high and VEN IBIAS
> 2V, the IC enters start-up sequence for both VDD rail
100k
and VDDNB rail. If the voltage at the pins of VCC and EN
drop below low threshold, the IC enters power down
sequence and all the functions are disabled. Normally, Figure 2. IBIAS Setting
connecting system power to the EN pin is recommended.
The SVID is ready in 2ms (max) after the chip has been Boot VID
enabled. All the protection latches (OVP, OCP, UVP) are
When EN goes high, both VDD and VDDNB output begin
cleared only after POR = low. The condition of VEN = low
to soft-start to the boot VID in CCM. Table 8 shows the
does not clear these latches.
Boot VID setting. The Boot VID is determined by the SVC
VCC + CMP and SVD input states at EN rising edge and it is stored in
4.2V - the internal register. The digital soft-start circuit ramps up
PVCC CMP the reference voltage at a controlled slew rate to reduce
+ POR
3.85V - inrush current during start-up. When all the output voltages
EN + CMP Chip EN are above power good threshold (300mV below Boot VID)
2V - at the end of soft-start, the controller asserts power good
after a time delay.
Figure 1. Power Ready (POR) Detection
Table 8. 2-Bit Boot VID Code

Precise Reference Current Generation
Initial Startup VID (Boot VID)
The RT3663BC includes complicated analog circuits inside
SVC SVD VDD/VDDNB Output Voltage (V)
the controller. The IC needs very precise reference voltage/
0 0 1.1
current to drive these analog circuits. The IC generates a
2V voltage source at the IBIAS pin, and a 100kΩ resistor 0 1 1.0
is required to be connected between IBIAS and analog 1 0 0.9
ground, as shown in Figure 2. Through this connection, 1 1 0.8
the IC generates a 20μA current from the IBIAS pin to
analog ground, and this 20μA current is mirrored for internal
Start-Up Sequence
use. Note that other type of connection or other values of
After EN goes high, the RT3663BC starts up and operates
resistance applied at the IBIAS pin may cause functional
according to the initial settings. Figure 3 shows the
failure, such as slew rate control, OFS accuracy, etc. In
simplified sequence timing diagram. The detailed operation
other words, the IBIAS pin can only be connected with a
is described in the following.
100kΩ resistor to GND. The resistance tolerance of this
resistor is recommended to be 1% or lower.

25
RT3663BC
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
PVCC, VCC
SVID
SVID
Send
Send
SVC Byte
Byte
SVD
VOTF VOTF
Complete Complete
SVT
EN
PWROK
Boot VID Boot VID
CCM VID VID
CCM
CCM CCM CCM CCM CCM
VDD/
VDDNB
PGOOD/
PGOODA
Figure 3. Simplified Sequence Timing Diagram
Description of Figure 3 :
T0 : The RT3663BC waits for VCC and PVCC POR. T7 : The PWROK pin goes low and the SVI2 interface
T1 : The SVC pin and SVD pin set the Boot VID. Boot VID stops running. All output voltages go back to the boot VID
is latched at EN rising edge. SVT is driven high by the in CCM.
RT3663BC. T8 : The PWROK pin goes high again and the SVI2
T2 : The enable signal goes high and all output voltages interface starts running. The RT3663BC waits for SVID
ramp up to the Boot VID in CCM. The soft-start slew rate command from processor.
is 3mV/μs. T9 : A valid SVID command transaction occurs between
T3 : All output voltages are within the regulation limits and the processor and the RT3663BC.
the PGOOD and PGOODA signal goes high. T10 : The RT3663BC starts VID on-the-Fly transition
T4 : The PWROK pin goes high and the SVI2 interface according to the received SVID command and send a
starts running. The RT3663BC waits for SVID command VOTF Complete if the VID reaches target VID.
from processor. T11 : The enable signal goes low and all output voltages
T5 : A valid SVID command transaction occurs between enter soft-shutdown mode.
the processor and the RT3663BC.
T6 : The RT3663BC starts VOTF (VID on-the-Fly) transition
according to the received SVID command and send a
VOTF Complete if the VID reaches target VID.

26
RT3663BC
Power-Down Sequence SVI2 Wire Protocol
If the voltage at the EN pin falls below the enable falling The RT3663BC complies with AMD's Voltage Regulator
threshold, the controller is disabled. The voltage at the Specification, which defines the Serial VID Interface 2
PGOOD and PGOODA pins immediately go low at the (SVI2) protocol. With SVI2 protocol, the processor directly
loss of enable signal at the EN pin and the controller controls the reference voltage level of each individual
executes soft-shutdown operation. The internal digital controller channel and determines which controller
circuit ramps down the reference voltage at the same slew operates in power saving mode. The SVI2 interface is a
rate as that of in soft-start, making VDD and VDDNB output three-wire bus that connects a single master to one or
voltages gradually decrease in CCM. Each of the controller more slaves. The master initiates and terminates SVI2
channels stops switching when the voltage at the voltage transactions and drives the clock, SVC, and the data, SVD,
sense pin VSEN/VSENA, cross about 0.2V. The Boot VID during a transaction. The slave drives the telemetry, SVT
information stored in the internal register is cleared at IC during a transaction. The AMD processor is always the
POR. This event forces the RT3663BC to check the SVC master. The voltage regulator controller (RT3663BC) is
and SVD inputs for a new boot VID when the EN voltage always the slave. The RT3663BC receives the SVID code
goes high again. and acts accordingly. The SVI protocol supports 20MHz
high speed mode I2C, which is based on SVD data packet.
PGOOD and PGOODA Table 9 shows the SVD data packet. A SVD packet
The PGOOD and PGOODA are open-drain logic outputs. consists of a “Start” signal, three data bytes after each
The two pins provide the power good signal when VDD byte, and a “Stop” signal. The 8-bit serial VID codes are
and VDDNB output voltage are within the regulation limits listed in Table1. After the RT3663BC has received the stop
and no protection is triggered. These pins are typically sequence, it decodes the received serial VID code and
tied to 3.3V or 5V power source through a pull-high executes the command. The controller has the ability to
resistor. During shutdown state (EN = low) and the soft- sample and report voltage and current for the VDD and
start period, the PGOOD and PGOODA voltages are pulled VDDNB domains. The controller reports this telemetry
low. After a successful soft-start and VDD and VDDNB serially over the SVT wire which is clocked by the
output voltages are within the regulation limits, the PGOOD processor driven SVC. A bit TFN at SVD packet along
and PGOODA are released high individually. with the VDD and VDDNB domain selector bits are used
The voltages at the PGOOD and PGOODA pins are pulled by the processor to change the telemetry functionality.
low individually during normal operation when any of the The telemetry bit definition is listed in Figure 4. The detailed
following events occurs : over-voltage protection, under- SVI2 specification is outlined in the AMD Voltage Regulator
voltage protection, over-current protection, and logic low and Voltage Regulator Module (VRM) and Serial VID
EN voltage. If one rail triggers protection, another rail's Interface 2.0 (SVI2) Specification.
PGOOD is pulled low after 5μs delay.
Table 9. SVD Data Packet
Bit Time Description
1:5 Always 11000b
VDD domain selector bit, if set then the following two data bytes contain the VID for VDD, the
6
PSI state for VDD, and the load-line slope trim and offset trim state for VDD.
VDDNB domain selector bit, if set then the following two data bytes contain the VID for VDDNB,
7
the PSI state for VDDNB, and the load-line slope trim and offset trim state for VDDNB.
8 Always 0b
10 PSI0_L
11 : 17 VID Code bits [7:1]
19 VID Code bit [0]

27
RT3663BC
Bit Time Description
20 PSI1_L
21 TFN (Telemetry Functionality)
22 : 24 Load Line Slope Trim [2:0]
25 : 26 Offset Trim [1:0]
Voltage and Current VDDNB Voltage Bit in Voltage Only Mode;

VDD Voltage Bits
Mode Selection Current Bit in Voltage and Current Mode
Bit Time…… START STOP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SVC
SVT
Figure 4. Telemetry Bit Definition
PWROK and SVI2 Operation VID On-the-Fly Transition

The PWROK pin is an input pin, which is connected to After the RT3663BC has received a valid SVID code, it
the global power good signal from the platform. Logic high executes the VID on-the-Fly transition by stepping up/
at this pin enables the SVI2 interface, allowing data down the reference voltage of the required controller channel
transaction between processor and the RT3663BC. Once in a controlled slew rate, hence allowing the output voltage
the RT3663BC receives a valid SVID code, it decodes the to ramp up/down to target VID.
information from processor to determine which output During the VID on-the-Fly transition, the RT3663BC forces
plane is going to move to the target VID. The internal DAC CCM operation in high performance mode. If the controller
then steps the reference voltage in a controlled slew rate, channel operates in the power-saving mode prior to the
making the output voltage shift to the required new VID. VID on-the-Fly transition, it changes to high performance
Depending on the SVID code, more than one controller mode and implement CCM operation when the controller
channel can be targeted simultaneously in the VID implement VID up, and then remain in high performance
transition. For example, VDD and VDDNB voltages can mode; if the controller implement VID down in CCM, it
ramp up/down at the same time. slew rate is about 2.5mV/μs; if the controller implement
If the PWROK input goes low during normal operation, VID down in power-saving mode, it decays down and keep
the SVI2 protocol stops running. The RT3663BC in power-saving mode. The controller receives DACOFF
immediately drives SVT high and modifies all output in PSI=00 will change to PSI=11 multi-phase CCM down.
voltages back to the boot VID, which is stored in the internal The slew rate is 2.5mV/μs, when DACOFF finishes,
register right after the controller is enabled. The controller controller enters power saving mode;control loop is shut
does not read SVD and SVC inputs after the loss of down, only basic bias, sequence control and interface
PWROK. If the PWROK input goes high again, the SVI2 circuits are still active to achieve power saving.
protocol resumes running. The RT3663BC then waits to However DACOFF by PSI=11 CCM down, VR can enter
decode the SVID command from processor for a new VID power saving mode earlier than PSI=00 decay down.
and acts as previously described. The SVI2 protocol is
The voltage at the PGOOD pin keeps high during the VID
only runs when the PWROK input goes high after the
on-the-Fly transition. The RT3663BC sends VOTF
voltage at the EN pin goes high; otherwise, the RT3663BC
complete only at the end of VID up transition. In the event
does not soft-start due to incorrect signal sequence.
of receiving a VID off code, the RT3663BC steps the
reference voltage of required controller channel down to
zero, hence making the required output voltage decrease

28
RT3663BC
to zero, and the voltage at the PGOOD pin remains high Differential Remote Sense Setting
since the VID code is valid. The VDD and VDDNB controllers have differential, remote-
sense inputs to eliminate the effects of voltage drops along
Power State Transition
the PC board traces, processor internal power routes and
The RT3663BC supports power state transition function socket contacts. The processor contains on-die sense
in VDD and VDDNB VR for the PSI[x]_L and command pins, VDD_SENSE, VDDNB_SENSE and VSS_SENSE.
from AMD processor. The PSI[x]_L bit in the SVI2 protocol Connect RGND to VSS_SENSE. For VDD controller,
controls the operating mode of the RT3663BC controller connect FB to VDD_SENSE with a resistor to build the
channels. The default operation mode of VDD and VDDNB negative input path of the error amplifier. Connect FBA to
VR is CCM. VDDNB_SENSE with a resistor using the same way in
When the VDD VR is in N phase configuration and receives VDD controller. Connect VSS_SENSE to RGND using
PSI0_L = 0 and PSI1_L = 1, the VDD VR enters separate trace as shown in Figure 5. The precision
single-phase diode emulation mode. When the VDD VR reference voltages refer to RGND for accurate remote
receives PSI0_L = 0 and PSI1_L = 0, the VDD VR remains sensing.
in the single-phase diode emulation mode. In reverse, the Processor
VDD VR goes back to N phase operation in CCM upon VDD_SENSE VDDNB_SENSE
receiving PSI0_L = 1 and PSI1_L = 0 or 1, see Table 10. FB FBA
VDD VDD NB
When the VDDNB VR receives PSI0_L = 0 and PSI1_L = Controller
RGND
Controller
RGND
1, it enters single-phase diode emulation mode, when the VSS_SENSE
VDDNB VR receives PSI0_L = 0 and PSI1_L = 0, it
remains in the single-phase diode emulation mode. The Figure 5. Differential Remote Voltage Sense Connection
VDDNB VR goes back to full-phase CCM operation after
receiving PSI0_L = 1 and PSI1_L = 0 or 1, see Table 11. SET1 and SET2 Pin Setting
Table 10. VDD VR Power State The RT3663BC provides the SET1 pin for platform users
Full Phase to set the VDD and VDDNB controller OCP_TDC threshold,
PSI0_L : PSI1_L Mode
Number DVIDx compensation bit1 and internal ramp amplitude
11 or 10 3 phase CCM (RSET & RSETA), and the SET2 pin to set VDD and
3 01 1 phase DEM VDDNB controller OCP trigger delay (OCPTRGDELAY),
00 1 phase DEM
DVIDx compensation bit0, external offset function and quick
11 or 10 2 phase CCM
response threshold (QRTH & QRTHA). To set these pins,
2 01 1 phase DEM
platform designers should use resistive voltage divider on
00 1 phase DEM
these pins, refer to Figure 6 and Figure 7. The voltages at
the the SET1 and SET2 pins are :
1 01 1 phase DEM
RSET1,D
00 1 phase DEM VSET1  VCC  (1)
RSET1,U  RSET1,D
Table 11. VDDNB VR Power State
RSET2,D
Full Phase
PSI0_L : PSI1_L Mode VSET2  VCC  (2)
Number RSET2,U  RSET2,D
2 01 1 phase DEM
00 1 phase DEM
1 01 1 phase DEM
00 1 phase DEM

29
RT3663BC
The ADC monitors and decodes the voltage at this pin through the pin setting. When the EN pin goes high, the
only once after power up. After ADC decoding (only once), controller senses the voltage VSET3 represented as follows
a 40μA current (when VCC = 5V) is generated at the SET1 and sets VDD and VDDNB current gain ratio.
and SET2 pin for internal use. That is the voltage at SET1 RSET3,D
VSET3  VCC 
and SET2 pin is RSET3,U  RSET3,D
RSET1,U  RSET1,D After pin setting is finished, V064/SET3 pin is regulated

VSET1  40A  (3)
RSET1,U  RSET1,D at 0.64V as shown in Figure 8 (b).
RSET2,U  RSET2,D
VSET2  40A  (4) VDD Current
RSET2,U  RSET2,D Gain Ratio
VDDNB Current
Gain Ratio
From equation (1) to equation (4) and Table 2 to Table 5, VCC
platform users can set the above described pin setting
ADC 2.24V
functions. RSET3,U
SET3 VSET3 V064
Register CV064
DVIDx RSET3,D
Compensation
OCPTDCx
40µA Voltage +
RSETx Regulator 0.64V
(VCC = 5V) -
VCC
ADC 2.24V
VSET1 Figure 8 (a). V064/SET3 Pin Setting
RSET1,U
SET1 SET1
VCC
Register
 VSET1 RSET1,D
IV064 RSET3,U
V064
Figure 6. SET1 Pin Setting CV064
RSET3,D
DVIDx Compensation Voltage + 0.64V

Regulator -
OCPTR
GDELAY 40µA
QRTHx OFSx (VCC = 5V)
VCC Figure 8 (b). Illustration of 0.64V Regulation at

ADC 2.24V
V064/SET3 Pin
VSET2
RSET2,U
SET2 SET2
Register
In the application circuit as shown in Figure 9, the CV064
VSET2 RSET2,D is used to stabilize the internal voltage regulator at V064/
SET3 pin, and also related to the pin setting settling time.
Figure 7. SET2 Pin Setting Therefore, the recommended capacitance is 22nF.
V064/SET3 Pin Setting VCC
The V064/SET3 pin provides two functions: fixed 0.64V IV064 RSET3,U
reference voltage output during normal operation of VR V064/SET3
controller and programmable current gain ratio for VDD RSET3,D
CV064
and VDDNB controllers. Figure 8 (a) shows VDD and
VDDNB current gain ratio setting with the V064/SET3 pin
voltage VSET3. User can set the application of zero loadline Figure 9. Illustration of Capacitor CV064
at V064/SET3 Pin

30
RT3663BC
The accuracy and settling time of the voltage at V064/ Similar to the peak current mode control with finite
SET3 pin should be considered when the EN pin goes compensator gain, the HS_FET on-time is determined by
high. So, the equivalent RC settling time at this pin should CCRCOT on-time generator. When load current increases,
be smaller than 1ms. Therefore, the following equations VCS increases, the steady state COMP voltage also
can derive the RSET3,D and RSET3,U. increases and induces VOUT,VDD to decrease, thus achieving
AVP. A near-DC offset canceling is added to the output of
4  RSET3,EQU  CV064  1ms
EA to eliminate the inherent output offset of finite gain
RSET3,U  RSET3,D
RSET3,EQU  peak current mode controller.
RSET3,U  RSET3,D VIN
VCC   HS_FET VVDD

RSET3,U   1  0.64 
IV064 
L RSENSE
VSET3  CCRCOT
PWM3 Driver
PWM RX
CX
CMP
Logic RC
VSET3
RSET3,D  RSET3,U 
+
-
VCC  VSET3 LS_FET
COMP2
0.4 x Ai_VDD C
ISENxP
+
x1 ISENxN RCSx
VCS -
Offset IMON RIMON
VDD Controller Canceling
V064/SET3
C2 C1
Active Phase Determination R2 R1
COMP
VVDD_SENSE
The number of active phases is determined by the internal FB
-
EA RGND
+
+ VSS_SENSE
-
circuitry that monitors the ISENxN voltages during start-
VDAC,VDD
up. Normally, the VDD controller operates as a 3-phase
PWM controller. Pulling ISEN3N to VCC programs a 2- Figure 10. VDD Controller : Simplified Schematic for
phase operation, and pulling ISEN2N to VCC programs a Droop and Remote Sense in CCM
1-phase operation. At EN rising edge, VDD controller
Droop Setting
detects whether the voltages of ISEN2N and ISEN3N are
It is very easy to achieve Active Voltage Positioning (AVP)
higher than “VCC − 0.5V” respectively to decide how
by properly setting the error amplifier gain due to the native
many phases should be active. Phase selection is only
droop characteristics as shown in Figure 11. This target
active during IC POR. When POR = high, the number of
is to have
active phases is determined and latched. The unused
ISENxP pins are recommended to be connected to VCC VVDD = VDAC, VDD − ILOAD x RDROOP (5)
and unused PWM pins can be left floating. Then solving the switching condition VCOMP2 = VCS in
Figure 10 yields the desired error amplifier gain as
Loop Control
GI
The VDD controller adopts Richtek's proprietary G-NAVPTM A V  R2  (6)
R1 RDROOP
topology. The G-NAVPTM is based on the finite gain peak
RSENSE
current mode with CCRCOT (Constant Current Ripple GI   RIMON  4  Ai_VDD (7)
RCSx 10
Constant On-Time) topology. The output voltage, VVDD will
where GI is the internal current sense amplifier gain and
decrease with increasing output load current. The control
Ai_VDD is the VDD current gain ratio. RSENSE is the current
loop consists of PWM modulators with power stages,
sense resistor. If no external sense resistor present, it is
current sense amplifiers and an error amplifier as shown
the equivalent resistance of the inductor. RDROOP is the
in Figure 10.
equivalent load-line resistance as well as the desired static
output impedance.

31
RT3663BC
VVDD TON Setting
AV2 > AV1
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
AV2
switching losses. This may be acceptable in ultra portable
devices where the load currents are lower and the
AV1
controller is powered from a lower voltage supply.
0 Load Current Low frequency operation offers the best overall efficiency
Figure 11. VDD Controller : Error Amplifier gain (AV) at the expense of component size and board space.
Influence on VVDD Accuracy Figure 13 shows the On-Time setting circuit. Connect a
Loop Compensation resistor (RTON) between VIN and TONSET to set the on-
time of UGATE :
Optimized compensation of the VDD controller allows for
12
best possible load step response of the regulator's output. 24.4  10  RTON
tON (0.5V  VDAC  1.8V)  (11)
A type-I compensator with one pole and one zero is VIN  VDAC
adequate for proper compensation. Figure 12 shows the Where tON is the UGATE turn-on period, VIN is the input
compensation circuit. Previous design procedure shows voltage of the VDD controller, and VDAC is the DAC voltage.
how to select the resistive feedback components for the
When VDAC is larger than 1.8V, the equivalent switching
error amplifier gain. Next, C1 and C2 must be calculated
frequency may be over 500kHz, and this too fast switching
for compensation. The target is to achieve constant
frequency is unacceptable. Therefore, the VDD controller
resistive output impedance over the widest possible
implements a pseudo constant frequency technology to
frequency range.
avoid this disadvantage of CCRCOT topology. When VDAC
The pole frequency of the compensator must be set to is larger than 1.8V, the on-time equation is modified to :
compensate the output capacitor ESR zero :
12
fP  1
(8) 13.55  10  RTON  VDAC (12)
2   C  RC tON (VDAC  1.8V) 
VIN  VDAC
Where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as On-time translates only roughly to switching frequencies.
follows : For better efficiency of the given load range, the maximum
C  RC switching frequency is suggested to be :
C2  (9)
R2 fSW(MAX) 
VDAC(MAX)  ILOAD(MAX)  DCRL  RON_LS-FET  RDROOP 
The zero of compensator has to be placed at half of the
 VIN(MAX)  ILOAD(MAX)  RON_LS-FET  RON_HS-FET     TON  TD  TON, VAR   ILOAD(MAX)  RON_LS-FET   TD
 
switching frequency to filter the switching related noise.
Such that, (13)
1 Where fS(MAX) is the maximum switching frequency, TD is

C1  (10)
R1   fSW the driver dead time, TON,VAR is the TON variation value.
C2 C1 VDAC(MAX) is the maximum VDAC of application, VIN(MAX) is
the maximum application input voltage, ILOAD(MAX) is the
COMP R2 R1
VVDD_SENSE maximum load of application, R ON_LS-FET is the on-
FB
- resistance of low side FET RDS(ON), RON_HS-FET is the on-
EA RGND VSS_SENSE
+
+
-
resistance of high side FET RDS(ON) , DCRL is the equivalent

VDAC
resistance of the inductor, and RDROOP is the load-line
setting.
Figure 12. VDD Controller : Compensation Circuit

32
RT3663BC
RTON R1 voltage transient has only a small initial dip with a slow
CCRCOT TONSET
VIN
On-Time response time. RX is highly recommended as two 0603
Computer VDAC
C1 size resistors in series to enhance the Iout reporting
On-Time
accuracy. CX is suggested X7R type for the application.
Using current sense resistor in series with the inductor
Figure 13. VDD Controller : On-Time Setting with RC
can have better accuracy, but the efficiency is a trade-off.
Filter
Considering the equivalent inductance (LESL) of the current
Current Sense Setting sense resistor, an RC filter is recommended. The RC filter
The current sense topology of the VDD controller is calculation method is similar to the above mentioned
continuous inductor current sensing. Therefore, the inductor equivalent resistance sensing method.
controller is less sensitive to noise. Low offset amplifiers
are used for current balance, loop control and over current Per-Phase Over Current Protection
detection. The ISENxP and ISENxN pins denote the The VDD controller provides over current protection in each
positive and negative input of the current sense amplifier phase. For VDD controller in three-phase configuration,
of each phase. either phase can trigger Per-Phase Over Current Protection
(PHOCP).
Users can either use a current sense resistor or the
inductor's DCRL for current sensing. Using the inductor's The VDD controller senses each phase inductor current
DCRL allows higher efficiency as shown in Figure 14. IL, and PHOCP comparator compares sensed current with
IL VVDD PHOCP threshold current, as shown in Figure 15.
L DCRL
Current Mirror
1 I
RX CX 8 SENAxN
PHOCP trigger
ISENxN
ISENxP
+ 10µA ISENAxN
- ISENxN RCSx
Figure 14. VDD Controller : Lossless Inductor Sensing Figure 15. VDD Controller : Per-Phase OCP Setting
In order to optimize transient performance, RX and CX must
The resistor RCSx determines PHOCP threshold.
be set according to the equation below :
DCRL 1
L  R C IL,PERPHASE(MAX)   = 10A (16)
X X (14) RCSx 8
DCRL
IL,PERPHASE(MAX)  DCRL
Then the proportion between the phase current, IL, and RCSx  (17)
8  10A
the sensed current, ISENxN, is driven by the value of the
effective sense resistance, RCSx, and the DCRL of the The controller turns off all high-side/low-side MOSFETs
inductor. The resistance value of RCSx is limited by the to protect CPU if the per-phase over current protection is
internal circuitry. The recommended value is from 500Ω triggered.
to 1.2kΩ.
DCRL Current Balance
ISENxN  IL  (15)
RCSx
The VDD controller implements internal current balance
Considering the inductance tolerance, the resistor RX has
mechanism in the current loop. The VDD controller senses
to be tuned on board by examining the transient voltage.
and compares per-phase current signal with average
If the output voltage transient has an initial dip below the
current. If the sensed current of any particular phase is
minimum load-line requirement and the response time is
larger than average current, the on-time of this phase is
too fast causing a ring back, the value of resistance should
adjusted to be shorter.
be increased. Vice versa, with a high resistance, the output

33
RT3663BC
Initial Offset and External Offset (Over Clocking Dynamic VID Enhancement
Offset Function) During a dynamic VID event, the charging (dynamic VID
The VDD controller features over clocking offset function up) or discharging (dynamic VID down) current causes
which provides the possibility of wide range offset of output unwanted load-line effect which degrades the settling time
voltage. Two kinds of offset settings are available, initial performance. The RT3663BC holds the inductor current
and external. To enable/disable these offset functions to hold the load-line during a dynamic VID event. The VDD
depends on the SET2 pin setting (refer Table 5 and Table controller always enter three-phase configuration when
12). VDD controller receives dynamic VID up and VDD controller
While OFSENABLE and OFSAENABLE are “0”, initial holds the operating state when VDD controller receives
offset function is enabled and external offset function is dynamic VID down.
disabled. Initial offset function is implemented through The RT3663BC also has DVID compensation which can
OFS/OFSA pin. Initial offset function is decided by the boost up the Dynamic VID slew rate and adjust the voltage
following descriptions : on-the-fly complete timing. The DVID compensation
(1) If the voltage of OFS/OFSA < 0.3V at EN rising edge parameter can be selected by DVIDx compensation bits
then initial offset voltage is considered as 0V. using the SET1 and SET2 pins.
(2) If the voltage of OFS/OFSA > 0.3V at EN rising edge When the VID CCM down on light loading condition, the
then initial offset voltage is enabled. negative inductor current will be produced, and it may
cause the audio noise and phase ringing effect. For
VInitial_OFS = VOFS/OFSA − 1.2V (18-a)
improving the problems, the controller turns off the low
Core rail initial offset is set by OFS pin voltage, and NB side MOSFET to prevent the negative current when VID
rail initial offset is set by OFSA pin voltage. down, and return to normal CCM down operation after 4
(3) VVDD = VDAC - ILOAD x RDROOP+ VInitial_OFS (18-b) PWM pulses.
While OFSENABLE and OFSAENABLE are “1”, initial Ramp Amplitude Adjust
offset function is disabled and external offset function is
When the VDD controller takes phase shedding operation
enabled. External offset function is also implemented
and enters diode emulation mode, the internal ramp of
through OFS/OFSA pin. External offset function is decided
VDD controller is modified for the reason of stability. In
by the following descriptions :
case of smooth transition into DEM, the CCM ramp
(1) VExternal_OFS = VOFS/OFSA − 1.2V (18-c) amplitude should be designed properly. The RT3663BC
Core rail external offset is set by OFS pin voltage, and NB provides the SET1 pin for platform users to set the ramp
rail external offset is set by OFSA pin voltage. amplitude of the VDD controller in CCM.
(2) VVDD = VDAC - ILOAD x RDROOP + VExternal_OFS (18-d) Current Monitoring and Current Reporting
To add a filter capacitor between OFS/OFSA and GND is The VDD controller provides current monitoring function
recommended. via inductor current sensing. In the G-NAVPTM technology,
Table 12. Initial/External Offset Function Setting the output voltage is dependent on output current, and
for VDD and VDDNB Controller the current monitoring function is achieved by this
OFSENABLE OFSAENABLE Description characteristic of output voltage. The equivalent output
Enable Initial current is sensed from inductor current sensing and
0 0 offset, disable mirrored to the IMON pin. The resistor connected to the
external offset IMON pin determines voltage of the IMON output.
Enable external
DCRL
1 1 offset, disable VIMON = IL,SUM   RIMON  0.64 (20)
initial offset RCSx

34
RT3663BC
Where IL is the phase current, RCSx is the effective sense current based threshold. OCP-SPIKE should trip when
resistance, and RIMON is the current monitor current setting the cycle-by-cycle output current exceeds IDDSPIKE by
resistor. Note that the IMON pin cannot be monitored. some percentage. If either mechanism trips, then the VDD
The ADC circuit of the VDD controller monitors the voltage controller asserts OCP_L and delays any further action.
variation at the IMON pin from 0V to 3.19375V, and this This delay is called an action delay. Refer to action delay
voltage is decoded into digital format and stored into time. After the action delay has expired and the VDD
Output_Current register. The ADC divides 3.19375V into controller has allowed its current sense filter to settle out
511 levels, so LSB = 3.19375V / 511 = 6.25mV. and the current has not decreased below the threshold,
then the VDD controller turns off both high-side MOSFETs
Quick Response and low-side MOSFETs of all channels.
The VDD controller utilizes a quick response feature to Users can set OCP-SPIKE threshold, IL,SUM(SPIKE), by the
support heavy load current demand during instantaneous current monitor resistor RIMON of the following equation :
load transient. The VDD controller monitors the current of
IL,SUM (SPIKE) = 3.19375  0.64  CSx
R
(21)
the VVDD_SENSE, and this current is mirrored to internal DCRL RIMON
quick response circuit. At steady state, this mirrored
And set the OCP-TDC threshold, I L(TDC) , by some
current does not trigger a quick response. When the
percentage of OCP-SPIKE through Table 2.
VVDD_SENSE voltage drops abruptly due to load apply
transient, the mirrored current flowing into quick response Over-Voltage Protection (OVP)
circuit also increases instantaneously. The over-voltage protection circuit of the VDD controller
The QR threshold setting for VDD controller refers to Table monitors the output voltage via the VSEN pin after POR.
4. When VID is lower than 0.9V, once VSEN voltage exceeds
QRTH “0.9V + 325mV”, OVP is triggered and latched. When
QR Pulse
VID is larger than 0.9V, once VSEN voltage exceeds the
+
+ VVDD_SENSE
-
Generation CMP
Circuit -
internal reference by 325mV, OVP is triggered and latched.
The VDD controller tries to turn on low-side MOSFETs
Figure 16. VDD Controller : Quick Response Triggering and turn off high-side MOSFETs of all active phases of the
Circuit VDD controller to protect the CPU. When OVP is triggered
When quick response is triggered, the quick response by one rail, the other rail also enters soft shut down
circuit generates a quick response pulse. The pulse width sequence. A 1μs delay is used in OVP detection circuit
of quick response is almost the same as tON. to prevent false trigger.
After generating a quick response pulse, the pulse is then
Negative-Voltage Protection (NVP)
applied to the on-time generating circuit, and all the active
During OVP latch state, the VDD controller also monitors
phases' on-time are overridden by the quick response
the VSEN pin for negative voltage protection. Since the
pulse.
OVP latch continuously turns on all low-side MOSFETs
Over-Current Protection of the VDD controller, the VDD controller may suffer
The RT3663BC has dual OCP mechanism. The dual OCP negative output voltage. As a consequence, when the VSEN
mechanism has two types of thresholds. The first type, voltage drops below 0V after triggering OVP, the VDD
referred to as OCP-TDC, is a time and current based controller triggers NVP to turn off all low-side MOSFETs
threshold. OCP-TDC should trip when the average output of the VDD controller while the high-side MOSFETs remain
current exceeds TDC by some percentage and for a period off. After triggering NVP, if the output voltage rises above
of time. This period of time is referred to as the trigger 0V, the OVP latch restarts to turn on all low-side
delay. The second type, referred to as OCP-SPIKE, is a MOSFETs. The NVP function is active only after OVP is
triggered.

35
RT3663BC
VIN
Under-Voltage Protection (UVP)
HS_FET VVDDNB
The VDD controller implements under-voltage protection L RSENSE
CCRCOT
of VOUT,VDD. If VSEN voltage is less than the internal PWM
PWMA2 Driver RX RC
CX
CMP
Logic
reference by 500mV, the VDD controller triggers UVP
+
-
LS_FET C
0.4 x Ai_VDDNB
COMP2
latch. The UVP latch turns off both high-side and low-side ISENAxP
+
MOSFETs. When UVP is triggered by one rail, the other x2 ISENAxN RCSx
VCS -
rail also enters soft shutdown sequence. A 3μs delay is Offset IMONA RIMONA
Canceling
used in UVP detection circuit to prevent false trigger. V064/SET3
C2 C1
COMPA R2 R1
Under-Voltage Lock Out (UVLO) VVDDNB_SENSE
FBA
-
EA RGND
During normal operation, if the voltage at the VCC pin
+
+ VSS_SENSE
-
VDAC, VDDNB
drops below IC POR threshold, the VDD controller triggers
UVLO. The UVLO protection forces all high-side Figure 17. VDDNB Controller : Simplified Schematic for
MOSFETs and low-side MOSFETs off by shutting down Droop and Remote Sense in CCM
internal PWM logic drivers. A 3μs delay is used in UVLO
detection circuit to prevent false trigger. Droop Setting
It is very easy to achieve Active Voltage Positioning (AVP)
VDDNB Controller by properly setting the error amplifier gain due to the native
droop characteristics as shown in Figure 18. This target
VDDNB Controller Disable
is to have
The VDDNB controller can be disabled by connecting
ISENA1N to a voltage higher than VCC. If not in use, VVDDNB = VDAC,VDDNB − ILOAD x RDROOP (22)
ISENAxP is recommended to be connected to VCC, while Then solving the switching condition VCOMP2 = VCS in
PWMAx is left floating. When VDDNB controller is disabled, Figure 17 yields the desired error amplifier gain as
all SVID commands related to VDDNB controller are GI
A V  R2  (23)
rejected. R1 RDROOP
RSENSE
Loop Control where GI   RIMON  8  Ai_VDDNB (24)
RCSx 10
The VDDNB controller adopts Richtek's proprietary G-
where GI is the internal current sense amplifier gain and
NAVPTM topology. The G-NAVPTM is based on the finite
Ai_VDDNB is the VDDNB current gain ratio. RSENSE is the
gain peak current mode with CCRCOT (Constant Current
current sense resistor. If no external sense resistor present,
Ripple Constant On-Time) topology. The output voltage,
it is the equivalent resistance of the inductor. RDROOP is
VVDDNB decreases with increasing output load current. The
the equivalent load-line resistance as well as the desired
control loop consists of PWM modulators with power
static output impedance.
stages, current sense amplifiers and an error amplifier as
VVDDNB
shown in Figure 17. AV2 > AV1
Similar to the peak current mode control with finite

compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases, AV2
VCS increases, the steady state COMPA voltage also
AV1
increases and induces VVDDNB to decrease, thus achieving
0
AVP. A near-DC offset canceling is added to the output of Load Current
EA to eliminate the inherent output offset of finite gain Figure 18. VDDNB Controller : Error Amplifier gain (AV)
peak current mode controller. Influence on VVDDNB Accuracy

36
RT3663BC
Loop Compensation 24.4  1012  RTON
tON (0.5V  VDAC  1.8V)  (28)
Optimized compensation of the VDDNB controller allows VIN  VDAC,VDDNB
for best possible load step response of the regulator’s
output. A type-I compensator with one pole and one zero
Where tON is the UGATE turn-on period, VIN is input voltage
is adequate for proper compensation. Figure 19 shows
of the VDDNB controller, and VDAC,VDDNB is the DAC
the compensation circuit. Previous design procedure
voltage.
shows how to select the resistive feedback components
When VDAC,VDDNB is larger than 1.8V, the equivalent
for the error amplifier gain. Next, C1 and C2 must be
switching frequency may be over 500kHz, and this too
calculated for compensation. The target is to achieve
fast switching frequency is unacceptable. Therefore, the
constant resistive output impedance over the widest
VDDNB controller implements a pseudo constant
possible frequency range.
frequency technology to avoid this disadvantage of
The pole frequency of the compensator must be set to
CCRCOT topology. When VDAC,VDDNB is larger than 1.8V,
compensate the output capacitor ESR zero :
the on-time equation is modified to :
fP  1 (25)
2   C  RC tON (VDAC  1.8V)
12
Where C is the capacitance of output capacitor, and RC is 13.55  10  RTON  VDAC,VDDNB

the ESR of output capacitor. C2 can be calculated as VIN  VDAC,VDDNB (29)
follows :
On-time translates only roughly to switching frequencies.
C x RC
C2  (26)
R2 For better efficiency of the given load range, the maximum
The zero of compensator has to be placed at half of the switching frequency is suggested to be :
switching frequency to filter the switching related noise. fSW(MAX) 
VDAC(MAX)  ILOAD(MAX)  DCRL  RON_LS-FET  RDROOP 
Such that,
 VIN(MAX)  ILOAD(MAX)  RON_LS-FET  RON_HS-FET     TON  TD  TON, VAR   ILOAD(MAX)  RON_LS-FET   TD
 
C1  1
(27)
R1   fSW (30)
C2 C1
Where fS(MAX) is the maximum switching frequency,
COMPA R2 R1 TD is the driver dead time, TON,VAR is the TON variation
VVDDNB_SENSE
FBA value. VDAC(MAX) is the maximum VDAC,VDDNB of application,
-
EA RGND V IN(MAX) is the maximum application input voltage,
VSS_SENSE
+
+
-
VDAC,VDDNB ILOAD(MAX) is the maximum load of application, RON_LS-FET

is the on-resistance of low side FET RDS(ON) , RON_HS-FET
Figure 19. VDDNB Controller : Compensation Circuit
is the on-resistance of high side FET RDS(ON), DCRL is the
inductor equivalent resistance of the inductor, and RDROOP
TON Setting
is the load-line setting.
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher RTON
CCRCOT TONSETA R1
switching losses. This may be acceptable in ultra portable VIN
On-Time
devices where the load currents are lower and the Computer C1
VDAC,VDDNB
controller is powered from a lower voltage supply. Low
On-Time
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure Figure 20. VDDNB Controller : On-Time Setting with RC
20 shows the On-Time setting circuit. Connect a resistor Filter
(RTON) between VIN and TONSETA to set the on-time of
UGATE :

37
RT3663BC
Current Sense Setting Using current sense resistor in series with the inductor
The current sense topology of the VDDNB controller is can have better accuracy, but the efficiency is a trade-off.
continuous inductor current sensing. Therefore, the Considering the equivalent inductance (LESL) of the current
controller is less sensitive to noise. Low offset amplifiers sense resistor, an RC filter is recommended. The RC filter
are used for current balance, loop control and over current calculation method is similar to the above mentioned
detection. The ISENAxP and ISENAxN pins denote the inductor equivalent resistance sensing method.
positive and negative input of the current sense amplifier
Per-Phase Over Current Protection
of each phase.
The VDDNB controller provides over current protection in
Users can either use a current sense resistor or the
each phase. For VDDNB controller in two-phase
inductor's DCRL for current sensing. Using the inductor's
configuration, either phase can trigger Per-Phase Over
DCRL allows higher efficiency as shown in Figure 21.
Current Protection (PHOCP).
IL VVDDNB
The VDDNB controller senses each phase inductor current
L DCRL
IL, and PHOCP comparator compares sensed current with
RX CX PHOCP threshold current, as shown in Figure 22.
ISENAxN
ISENAxP
+
Current Mirror
- ISENAxN RCSx 1 I
8 SENAxN
PHOCP trigger
Figure 21. VDDNB Controller : Lossless Inductor 10µA ISENAxN
Sensing
In order to optimize transient performance, RX and CX must

Figure 22. VDDNB Controller : Per-Phase OCP Setting
be set according to the equation below :
L  R C (31) The resistor RCSx determines PHOCP threshold.
X X
DCRL DCRL 1
IL,PERPHASE(MAX)   = 10A (33)
Then the proportion between the phase current, IL, and RCSx 8
the sensed current, ISENAxN, is driven by the value of the IL,PERPHASE(MAX)  DCRL
RCSx  (34)
effective sense resistance, RCSx, and the DCRL of the 8  10A
inductor. The resistance value of RCSx is limited by the
The controller will turns all high-side/low-side MOSFETs
internal circuitry. The recommended value is from 500Ω
to protect CPU if the per-phase over current protection is
to 1.2kΩ.
triggered.
DCRL
ISENAxN  IL  (32)
RCSx Initial Offset and External Offset (Over Clocking
Considering the inductance tolerance, the resistor RX has Offset Function)
to be tuned on board by examining the transient voltage. The VDDNB controller features over clocking offset function
If the output voltage transient has an initial dip below the which provides the possibility of wide range offset of output
minimum load-line requirement and the response time is voltage. The initial offset function can be implemented
too fast causing a ring back, the value of resistance should through the SVI interface. When the OFSA pin voltage
be increased. Vice versa, with a high resistance, the output < 0.3V at EN rising edge, the initial offset is disabled.
voltage transient has only a small initial dip with a slow
response time. RX is highly recommended as two 0603
size resistors in series to enhance the Iout reporting
accuracy. CX is suggested X7R type for the application.

38
RT3663BC
The external offset function can be implemented by the Ramp Amplitude Adjust
SET2 pin setting. For example, referring to Table 12, when When the VDDNB controller takes phase shedding
the both rail external offset functions are enabled, the operation and enters diode emulation mode, the internal
output voltage is : ramp of VDDNB controller is modified for the reason of
VVDDNB  VDAC,VDDNB  ILOAD  RDROOP stability. In case of smooth transition into DEM, the CCM
+ VExternal _ OFSA + VInitial _ OFSA (35) ramp amplitude should be designed properly. The
RT3663BC provides the SET1 pin for platform users to
VInitial_OFSA is the initial offset voltage set by SVI interface,
set the ramp amplitude of the VDDNB controller in CCM.
and the external offset voltage, VExternal_OFSA is set by
supplying a voltage into the OFSA pin. Current Monitoring and Current Reporting
It can be calculated as below : The VDDNB controller provides current monitoring function
VExternal _ OFSA = VOFSA  1.2V (36) via inductor current sensing. In the G-NAVPTM technology,
the output voltage is dependent on output current, and
If supplying 1.3V at OFSA pin, it achieves 100mV offset the current monitoring function is achieved by this
at the output. Connecting a filter capacitor between the characteristic of output voltage. The equivalent output
OFSA and GND pins is necessary. Designers can design current is sensed from inductor current sensing and
the offset slew rate by properly setting the filter bandwidth. mirrored to the IMONA pin. The resistor connected to the
IMONA pin determines voltage of the IMONA output.
Dynamic VID Enhancement DCRL
VIMONA = IL,SUM  2   RIMONA  0.64 (37)
During a dynamic VID event, the charging (dynamic VID RCSx
up) or discharging (dynamic VID down) current causes Where IL is the phase current, RCSx is the effective sense
unwanted load-line effect which degrades the settling time resistance, and RIMONA is the current monitor current setting
performance. The RT3663BC holds the inductor current resistor. Note that the IMONA pin cannot be monitored.
to hold the load-line during a dynamic VID event. The
The ADC circuit of the VDDNB controller monitors the
VDDNB controller always enters two-phase configuration
voltage variation at the IMONA pin from 0V to 3.19375V,
when VDDNB controller receives dynamic VID up and
and this voltage is decoded into digital format and stored
VDDNB controller holds the operating state when VDDNB
into Output_Current register. The ADC divides 3.19375V
controller receives dynamic VID down.
into 511 levels, so LSB = 3.19375V / 511 = 6.25mV.
The RT3663BC also has DVID compensation which can
boost up the Dynamic VID slew rate and adjust the voltage Quick Response
on-the-fly complete timing. The DVID compensation The VDDNB controller utilizes a quick response feature
parameter can be selected by DVIDx compensation bits to support heavy load current demand during instantaneous
using the SET1 and SET2 pins. load transient. The VDDNB controller monitors the current
When the VID CCM down on light loading condition, the of the VVDDNB_SENSE, and this current is mirrored to internal
negative inductor current will be produced, and it may quick response circuit. At steady state, this mirrored
cause the audio noise and phase ringing effect. For current does not trigger a quick response. When the
improving the problems, the controller turns off the low VVDDNB_SENSE voltage drops abruptly due to load transient,
side MOSFET to prevent the negative current when VID the mirrored current flowing into quick response circuit
down, and return to normal CCM down operation after 4 increases instantaneously.
PWM pulses. The QR threshold setting for VDDNB controller refers to
Table 5.

39
RT3663BC
QRTHA Over-Voltage Protection (OVP)
QR Pulse
+
+ VVDDNB_SENSE The over-voltage protection circuit of the VDDNB controller
-
Generation CMP
Circuit - monitors the output voltage via the VSENA pin after POR.
When VID is lower than 0.9V, once VSENA voltage
exceeds “0.9V + 325mV”, OVP is triggered and latched.
Figure 23. VDDNB Controller : Quick Response When VID is larger than 0.9V, once VSENA voltage
Triggering Circuit exceeds the internal reference by 325mV, OVP is
triggered and latched. The VDDNB controller tries to turn
When quick response is triggered, the quick response on low-side MOSFETs and turn off high-side MOSFETs of
circuit generates a quick response pulse. The pulse width all active phases of the VDDNB controller to protect the
of quick response is almost the same as tON. CPU. When OVP is triggered by one rail, the other rail
After generating a quick response pulse, the pulse is then also enters soft shut down sequence. A 1μs delay is used
applied to the on-time generation circuit, and all the active in OVP detection circuit to prevent false trigger.
phases' on-times are overridden by the quick response
Negative-Voltage Protection (NVP)
pulse.
During OVP latch state, the VDDNB controller also
Over-Current Protection monitors the VSENA pin for negative voltage protection.
The RT3663BC has dual OCP mechanism. The dual OCP Since the OVP latch continuously turns on all low-side
mechanism has two types of thresholds. The first type, MOSFETs of the VDDNB controller, the VDDNB controller
referred to as OCP-TDCA, is a time and current based may suffer negative output voltage. As a consequence,
threshold. OCP-TDCA should trip when the average output when the VSENA voltage drops below 0V after triggering
current exceeds TDCA by some percentage and for a OVP, the VDDNB controller triggers NVP to turn off all
period of time. This period of time is referred to as the low-side MOSFETs of the VDDNB controller while the high-
trigger delay. The second type, referred to as OCP- side MOSFETs remain off. After triggering NVP, if the output
SPIKEA, is a current based threshold. OCP-SPIKEA voltage rises above 0V, the OVP latch restarts to turn on
should trip when the cycle-by-cycle output current all low-side MOSFETs. The NVP function is active only
exceeds IDDSPIKEA by some percentage. If either after OVP is triggered.
mechanism trips, then the VDDNB controller asserts
Under-Voltage Protection (UVP)
OCP_L and delays any further action. This delay is called
an action delay. Refer to action delay time. After the action The VDDNB controller implements under-voltage protection
delay has expired and the VDDNB controller has allowed of VOUT,VDDNB. If VSENA voltage is less than the internal
its current sense filter to settle out and the current has reference by 500mV, the VDDNB controller triggers UVP
not decreased below the threshold, then the VDDNB latch. The UVP latch turns off both high-side and low-side
controller turns off both high-side MOSFETs and low-side MOSFETs. When UVP is triggered by one rail, the other
MOSFETs of all channels. rail also enters soft shutdown sequence. A 3μs delay is
used in UVP detection circuit to prevent false trigger.
Users can set OCP-SPIKEA threshold, IL,SUM(SPIKEA), by
the current monitor resistor RIMONA of the following equation : Under-Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC pin
IL,SUM (SPIKE) = 3.19375  0.64  CSx
R
(38)
2  DCR RIMONA drops below IC POR threshold, the VDDNB controller
triggers UVLO. The UVLO protection forces all high-side
And set the OCP-TDCA threshold, IL(TDCA), by some
MOSFETs and low-side MOSFETs off by shutting down
percentage of OCP-SPIKEA through Table 3.
internal PWM logic drivers. A 3μs delay is used in UVLO
detection circuit to prevent false trigger.

40
RT3663BC
Thermal Considerations 4.0
Four-Layer PCB
Maximum Power Dissipation (W)1

The junction temperature should never exceed the 3.6
absolute maximum junction temperature TJ(MAX), listed 3.2

under Absolute Maximum Ratings, to avoid permanent 2.8
damage to the device. The maximum allowable power 2.4
dissipation depends on the thermal resistance of the IC 2.0
package, the PCB layout, the rate of surrounding airflow, 1.6
and the difference between the junction and ambient 1.2

temperatures. The maximum power dissipation can be 0.8
calculated using the following formula : 0.4

0.0
PD(MAX) = (TJ(MAX) − TA) / θJA
0 25 50 75 100 125
where TJ(MAX) is the maximum junction temperature, TA is Ambient Temperature (°C)
the ambient temperature, and θJA is the junction-to-ambient Figure 24. Derating Curve of Maximum Power
thermal resistance. Dissipation
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WQFN-52L 6x6 package, the thermal resistance, θJA, is
26.5°C/W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
PD(MAX) = (125°C − 25°C) / (26.5°C/W) = 3.77W for a
WQFN-52L 6x6 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 24 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.

41
RT3663BC
Outline Dimension
1 1
2 2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.
Dimensions In Millimeters Dimensions In Inches

Symbol
Min. Max. Min. Max.
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 5.950 6.050 0.234 0.238
D2 4.650 4.750 0.183 0.187
E 5.950 6.050 0.234 0.238
E2 4.650 4.750 0.183 0.187
e 0.400 0.016
L 0.350 0.450 0.014 0.018
L1 0.300 0.400 0.012 0.016
W-Type 52L QFN 6x6 Package

42
RT3663BC
Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.

43

RT3663BC RichTek

Uploaded by

Copyright:

Available Formats

RT3663BC RichTek

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

RT3663BC RichTek

Uploaded by

Copyright:

Available Formats

®

Dual-Output PWM Controller with 3 Integrated Drivers for

Simplified Application Circuit

SVT PWMA2 RT9610 MOSFET

DS3663BC-03 August 2019 www.richtek.com

Note : UGATE2 1 39 PGOOD

www.richtek.com DS3663BC-03 August 2019

DS3663BC-03 August 2019 www.richtek.com

www.richtek.com DS3663BC-03 August 2019

SVI2 Interface OFS/OFSA

DS3663BC-03 August 2019 www.richtek.com

Loop Control Protection Logic Current Balance

www.richtek.com DS3663BC-03 August 2019

DS3663BC-03 August 2019 www.richtek.com

www.richtek.com DS3663BC-03 August 2019

DS3663BC-03 August 2019 www.richtek.com

www.richtek.com DS3663BC-03 August 2019

DS3663BC-03 August 2019 www.richtek.com

www.richtek.com DS3663BC-03 August 2019

DS3663BC-03 August 2019 www.richtek.com

Recommended Operating Conditions (Note 4)

www.richtek.com DS3663BC-03 August 2019

DS3663BC-03 August 2019 www.richtek.com

IOCP_SPIKE DCR = 1.1m, RSENSE = 1.1k,

www.richtek.com DS3663BC-03 August 2019

OCP_L, PGOOD and PGOODA

DS3663BC-03 August 2019 www.richtek.com

www.richtek.com DS3663BC-03 August 2019

DS3663BC-03 August 2019

Copyright © 2019 Richtek Technology Corporation. All rights reserved.

10k 51.28k POSCAP : 330µF x 4

is a registered trademark of Richtek Technology Corporation.

Time (500μs/Div) Time (500μs/Div)

CORE VR OCP_TDC CORE VR OCP_SPIKE

Time (5ms/Div) Time (10μs/Div)

CORE VR OVP and NVP CORE VR UVP

Time (20μs/Div) Time (10μs/Div)

www.richtek.com DS3663BC-03 August 2019

CORE VR Dynamic VID Up CORE VR Dynamic VID Up

Time (20μs/Div) Time (20μs/Div)

CORE VR Dynamic VID Up CORE VR Dynamic VID Up

Time (20μs/Div) Time (20μs/Div)

CORE VR Dynamic VID Up CORE VR Load Transient

Time (20μs/Div) Time (5μs/Div)

DS3663BC-03 August 2019 www.richtek.com

CORE VR Load Transient NB VR Power On from EN

Time (5μs/Div) Time (500μs/Div)

NB VR Power Off from EN NB VR OCP_TDC

Time (500μs/Div) Time (5ms/Div)

NB VR OCP_SPIKE NB VR OVP and NVP

Time (10μs/Div) Time (20μs/Div)

www.richtek.com DS3663BC-03 August 2019

NB VR UVP NB VR Dynamic VID Up

Time (10μs/Div) Time (20μs/Div)

NB VR Dynamic VID Up NB VR Dynamic VID Up

Time (20μs/Div) Time (20μs/Div)

NB VR Dynamic VID Up NB VR Dynamic VID Up

Time (20μs/Div) Time (20μs/Div)

DS3663BC-03 August 2019 www.richtek.com