SDAS198B − APRIL 1982 − REVISED AUGUST 1995

• Package Options Include Plastic SN54ALS109A, SN54AS109A . . . J PACKAGE

Small-Outline (D) Packages, Ceramic Chip SN74ALS109A, SN74AS109A . . . D OR N PACKAGE
(TOP VIEW)
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
1CLR 1 16 VCC
1J 2 15 2CLR
TYPICAL MAXIMUM TYPICAL POWER
CLOCK DISSIPATION 1K 3 14 2J
TYPE
FREQUENCY PER FLIP-FLOP 1CLK 4 13 2K
(MHz) (mW) 1PRE 5 12 2CLK
′ALS109A 50 6 1Q 6 11 2PRE
′AS109A 129 29 1Q 7 10 2Q
GND 8 9 2Q
description
These devices contain two independent J-K SN54ALS109A, SN54AS109A . . . FK PACKAGE
positive-edge-triggered flip-flops. A low level at (TOP VIEW)
the preset (PRE) or clear (CLR) inputs sets or

1CLR

2CLR
VCC
resets the outputs regardless of the levels of the

NC
1J
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the 3 2 1 20 19
setup-time requirements are transferred to the 1K 4 18 2J
outputs on the positive-going edge of the clock 1CLK 5 17 2K
(CLK) pulse. Clock triggering occurs at a voltage NC 6 16 NC
level and is not directly related to the rise time of 1PRE 7 15 2CLK
the clock pulse. Following the hold-time interval, 1Q 8 14 2PRE
9 10 11 12 13
data at the J and K inputs can be changed without
affecting the levels at the outputs. These versatile

GND
NC

2Q
1Q

2Q
flip-flops can perform as toggle flip-flops by
grounding K and tying J high. They also can
NC − No internal connection
perform as D-type flip-flops if J and K are tied
together.
The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range
of −55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.

FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK J K Q Q
L H X X X H L
H L X X X L H
L L X X X H† H†
H H ↑ L L L H
H H ↑ H L Toggle
H H ↑ L H Q0 Q0
H H ↑ H H H L
H H L X X Q0 Q0
† The output levels in this configuration are not specified to
meet the minimum levels for VOH if the lows at PRE and
CLR are near VIL maximum. Furthermore, this
configuration is nonstable; that is, it does not persist when
either PRE or CLR returns to its inactive (high) level.

   !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/ Copyright  1995, Texas Instruments Incorporated
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443


 

 
 
 
 
 
  
  

   

SDAS198B − APRIL 1982 − REVISED AUGUST 1995

logic symbol†

5
1PRE S
2 6
1J 1J 1Q
4
1CLK C1
3 7
1K 1K 1Q
1
1CLR R
11
2PRE
14 10
2J 2Q
12
2CLK
13 9
2K 2Q
15
2CLR

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA: SN54ALS109A . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74ALS109A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54ALS109A SN74ALS109A
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 4 8 mA
fclock Clock frequency 0 30 0 34 MHz
PRE or CLR low 15 15
tw Pulse duration CLK high 16.5 14.5 ns
CLK low 16.5 14.5
Data 15 15
tsu Setup time before CLK↑ ns
PRE or CLR inactive 10 10
th Hold time after CLK↑ Data 0 0 ns
TA Operating free-air temperature −55 125 0 70 °C

2 •
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SDAS198B − APRIL 1982 − REVISED AUGUST 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54ALS109A SN74ALS109A
PARAMETER TEST CONDITIONS UNIT
MIN TYP† MAX MIN TYP† MAX
VIK VCC = 4.5 V, II = −18 mA −1.5 −1.5 V
VOH VCC = 4.5 V to 5.5 V, IOH = − 0.4 mA VCC −2 VCC −2 V
IOL = 4 mA 0.25 0.4 0.25 0.4
VOL VCC = 4.5 V V
IOL = 8 mA 0.35 0.5
CLK, J, or K 0.1 0.1
II VCC = 5.5 V, VI = 7 V mA
PRE or CLR 0.2 0.2
CLK, J, or K 20 20
IIH VCC = 5.5 V, VI = 2.7 V µA
A
PRE or CLR 40 40
CLK, J, or K −0.2 −0.2
IIL VCC = 5.5 V, VI = 0.4 V mA
PRE or CLR −0.4 −0.4
IO‡ VCC = 5.5 V, VO = 2.25 V −20 −112 −30 −112 mA
ICC VCC = 5.5 V, See Note 1 2.4 4 2.4 4 mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.

switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
FROM TO
PARAMETER TA = MIN to MAX§ UNIT
(INPUT) (OUTPUT)
SN54ALS109A SN74ALS109A
MIN MAX MIN MAX
fmax 30 34 MHz
tPLH 3 17 3 13
PRE or CLR Q or Q ns
tPHL 5 17 5 15
tPLH 5 21 5 16
CLK Q or Q ns
tPHL 5 20 5 18
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

•
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SDAS198B − APRIL 1982 − REVISED AUGUST 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA: SN54AS109A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74AS109A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54AS109A SN74AS109A
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −2 −2 mA
IOL Low-level output current 20 20 mA
fclock* Clock frequency 0 90 0 105 MHz
PRE or CLR low 4 4
tw* Pulse duration CLK high 4 4 ns
CLK low 5.5 5.5
Data 5.5 5.5
tsu* Setup time before CLK↑ ns
PRE or CLR inactive 2 2
th* Hold time after CLK↑ Data 0 0 ns
TA Operating free-air temperature −55 125 0 70 °C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54AS109A SN74AS109A
PARAMETER TEST CONDITIONS UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V
VOH VCC = 4.5 V to 5.5 V, IOH = − 2 mA VCC −2 VCC −2 V
VOL VCC = 4.5 V, IOL = 20 mA 0.25 0.5 0.25 0.5 V
II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
CLK, J, or K 20 20
IIH VCC = 5.5 V, VI = 2.7 V µA
A
PRE or CLR 40 40
CLK, J, or K −0.5 −0.5
IIL VCC = 5.5 V, VI = 0.4 V mA
PRE or CLR −1.8 −1.8
IO§ VCC = 5.5 V, VO = 2.25 V −30 −112 −30 −112 mA
ICC VCC = 5.5 V, See Note 1 11.5 17 11.5 17 mA
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.

4 •
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•
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SDAS198B − APRIL 1982 − REVISED AUGUST 1995

switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
FROM TO
PARAMETER TA = MIN to MAX† UNIT
(INPUT) (OUTPUT)
SN54AS109A SN74AS109A
MIN MAX MIN MAX
fmax* 90 105 MHz
tPLH 2 9 2 8
PRE or CLR Q or Q ns
tPHL 3.5 11.5 3.5 10.5
tPLH 2.5 10 2.5 9
CLK Q or Q ns
tPHL 3.5 10.5 3.5 9
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

•
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SDAS198B − APRIL 1982 − REVISED AUGUST 1995

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
VCC RL = R1 = R2

S1
RL
R1
From Output Test From Output Test From Output Test
Under Test Point Under Test Point Under Test Point
CL RL CL
CL R2
(see Note A) (see Note A)
(see Note A)

LOAD CIRCUIT FOR

BI-STATE LOAD CIRCUIT LOAD CIRCUIT
TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS

Timing 3.5 V High-Level 3.5 V

Input 1.3 V Pulse 1.3 V 1.3 V
0.3 V 0.3 V
th tw
tsu
3.5 V 3.5 V
Data Low-Level
Input 1.3 V 1.3 V 1.3 V 1.3 V
Pulse
0.3 V 0.3 V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3.5 V
Output
Control 1.3 V 1.3 V
(low-level
enabling) 0.3 V 3.5 V
tPZL Input 1.3 V 1.3 V
tPLZ
0.3 V
[3.5 V
Waveform 1 tPLH tPHL
S1 Closed 1.3 V
In-Phase VOH
(see Note B) 1.3 V 1.3 V
VOL Output
tPHZ 0.3 V VOL
tPZH tPLH
VOH tPHL
Waveform 2 VOH
Out-of-Phase
S1 Open 1.3 V 0.3 V 1.3 V 1.3 V
Output
(see Note B) (see Note C) VOL
[0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

6 •
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•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

84000012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84000012A Samples
& Green SNJ54ALS
109AFK
8400001EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8400001EA Samples
& Green SNJ54ALS109AJ
JM38510/37102B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 37102B2A
JM38510/37102BEA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 37102BEA
M38510/37102B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 37102B2A
M38510/37102BEA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 37102BEA
SN54ALS109AJ ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54ALS109AJ Samples
& Green
SN74ALS109AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS109A Samples

SN74ALS109AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74ALS109AN Samples

SN74ALS109ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS109A Samples

SN74AS109AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AS109A Samples

SN74AS109AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74AS109AN Samples

SN74AS109ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74AS109A Samples

SNJ54ALS109AFK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84000012A Samples
& Green SNJ54ALS
109AFK
SNJ54ALS109AJ ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8400001EA Samples
& Green SNJ54ALS109AJ

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Apr-2024

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ALS109A, SN74ALS109A :

• Catalog : SN74ALS109A
• Military : SN54ALS109A

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Apr-2024

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Nov-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALS109ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AS109ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Nov-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS109ANSR SO NS 16 2000 356.0 356.0 35.0
SN74AS109ANSR SO NS 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Nov-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
84000012A FK LCCC 20 55 506.98 12.06 2030 NA
JM38510/37102B2A FK LCCC 20 55 506.98 12.06 2030 NA
M38510/37102B2A FK LCCC 20 55 506.98 12.06 2030 NA
SN74ALS109AD D SOIC 16 40 507 8 3940 4.32
SN74ALS109AN N PDIP 16 25 506 13.97 11230 4.32
SN74ALS109AN N PDIP 16 25 506 13.97 11230 4.32
SN74AS109AD D SOIC 16 40 507 8 3940 4.32
SN74AS109AN N PDIP 16 25 506 13.97 11230 4.32
SN74AS109AN N PDIP 16 25 506 13.97 11230 4.32
SNJ54ALS109AFK FK LCCC 20 55 506.98 12.06 2030 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

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