4-Channel, I2C, Ultra Low Power,

12-Bit ADC in 20-Lead LFCSP/TSSOP

Data Sheet AD7091R-5
FEATURES FUNCTIONAL BLOCK DIAGRAM
REFIN/
I2C-compatible serial interface supports standard and MUXOUT ADCIN VDD REFOUT REGCAP
fast modes
Ultra low power: 90 µW typical at 3 V in fast mode
2.5V
Specified for VDD of 2.7 V to 5.25 V VREF
VIN0
On-chip accurate 2.5 V reference, 5 ppm/°C typical drift 12-BIT
VIN1 SUCCESSIVE
INPUT T/H
4 single-ended analog input channels VIN2 MUX
APPROXIMATION
ADC
ALERT function VIN3
BUSY function ON-CHIP
OSC RESET
Autocycle mode CONVST/GPO1
CHANNEL
Wide input bandwidth SEQUENCER
CONTROL SDA
LOGIC
68 dB signal-to-noise ratio (SNR) typical at input I2C INTERFACE
SCL
AS0
frequency of 1 kHz
AS1
Flexible power/throughput rate management AD7091R-5
VDRIVE
No pipeline delays
Power-down mode

12093-001
GND ALERT/BUSY/ GPO2 GND
550 nA typical at VDD = 5.25 V GPO0

435 nA typical at VDD = 3 V Figure 1.

20-lead LFCSP and TSSOP packages
Temperature range: −40°C to +125°C

APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions

GENERAL DESCRIPTION
The AD7091R-5 is a 12-bit, multichannel, ultra low power, succes- The AD7091R-5 offers four single-ended analog input channels
sive approximation analog-to-digital converter (ADC). The with a channel sequencer that allows a preprogrammed
AD7091R-5 operates from a single 2.7 V to 5.25 V power supply selection of channels to be converted sequentially.
and typically consumes only 24 µA at a 3 V supply in fast mode.
The AD7091R-5 uses advanced design techniques to achieve
The AD7091R-5 provides a 2-wire serial interface compatible ultra low power dissipation without compromising performance. It
with I2C interfaces. The conversion process can be controlled by also features flexible power management options. An on-chip
a sample mode via the CONVST/GPO1 pin, an autocycle mode configuration register allows the user to set up different operating
selected through software control, or a command mode in conditions. These include power management, alert functionality,
which conversions occur across I2C write operations. busy indication, channel sequencing, and general-purpose output
The device contains a wide bandwidth track-and-hold amplifier pins. The MUXOUT and ADCIN pins allow signal conditioning of the
that can handle input frequencies up to 1.5 MHz. The AD7091R-5 multiplexer output before acquisition by the ADC.
also features an on-chip conversion clock, an on-chip accurate
2.5 V reference, and a programmable out of bounds user alert
function.

Rev. A Document Feedback

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AD7091R-5 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 I2C Register Access ..................................................................... 19
Applications ....................................................................................... 1 Conversion Result Register ....................................................... 20
Functional Block Diagram .............................................................. 1 Channel Register ........................................................................ 21
General Description ......................................................................... 1 Configuration Register .............................................................. 22
Revision History ............................................................................... 2 Alert Indication Register ........................................................... 24
Specifications..................................................................................... 3 Channel x Low Limit Register .................................................. 26
I C Timing Specifications ............................................................ 5
2
Channel x High Limit Register ................................................. 26
Absolute Maximum Ratings............................................................ 6 Channel x Hysteresis Register .................................................. 26
Thermal Resistance ...................................................................... 6 I C Interface .................................................................................... 27
2

ESD Caution .................................................................................. 6 Serial Bus Address Byte ............................................................. 27

Pin Configurations and Function Descriptions ........................... 7 General I2C Timing .................................................................... 27
Typical Performance Characteristics ............................................. 9 Writing to the AD7091R-5 ............................................................ 28
Terminology .................................................................................... 14 Writing Two Bytes of Data to a 16-Bit Register ..................... 28
Theory of Operation ...................................................................... 15 Writing to Multiple Registers.................................................... 28
Circuit Information .................................................................... 15 Reading Data from the AD7091R-5............................................. 29
Converter Operation .................................................................. 15 Reading Two Bytes of Data from a 16-Bit Register ............... 29
ADC Transfer Function ............................................................. 15 Modes of Operation ....................................................................... 30
Reference ..................................................................................... 15 Sample Mode .............................................................................. 30
Power Supply ............................................................................... 16 Command Mode ........................................................................ 30
Device Reset ................................................................................ 16 Autocycle Mode .......................................................................... 32
Analog Input ............................................................................... 16 Power-Down Mode .................................................................... 32
Driver Amplifier Choice ............................................................ 17 Alert ............................................................................................. 33
Typical Connection Diagram ................................................... 17 Busy .............................................................................................. 33
I C Registers .................................................................................... 19
2
Channel Sequencer .................................................................... 33
Addressing Registers .................................................................. 19 Outline Dimensions ....................................................................... 34
Slave Address............................................................................... 19 Ordering Guide .......................................................................... 34

REVISION HISTORY
2/2018—Rev. 0 to Rev. A
Changes to Command Mode Section and Figure 43 ................. 31
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 34

7/2015—Revision 0: Initial Version

Rev. A | Page 2 of 34
Data Sheet AD7091R-5

SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, fSCL = 400 kHz, fast SCL mode, VREF = 2.5 V internal/external, TA = −40°C to +125°C,
unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE fIN = 1 kHz sine wave
Signal-to-Noise Ratio (SNR) 68 dB
Signal-to-Noise-and-Distortion Ratio 67 dB
(SINAD)
Total Harmonic Distortion (THD) −80 dB
Spurious-Free Dynamic Range (SFDR) −81 dB
Channel to Channel Isolation −105 dB
Aperture Delay 5 ns
Aperture Jitter 40 ps
Full Power Bandwidth At −3 dB 1.5 MHz
At −0.1 dB 1.2 MHz
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (INL) −1.25 ±0.8 +1.25 LSB
Differential Nonlinearity (DNL) Guaranteed no missing codes to 12 bits −0.9 ±0.3 +0.9 LSB
Offset Error TA = 25°C −1.5 ±0.3 +1.5 mV
Offset Error Matching TA = 25°C −1.5 ±0.3 +1.5 mV
Offset Error Drift 2 ppm/°C
Gain Error TA = 25°C −0.1 0.0 +0.1 % FS
Gain Error Matching TA = 25°C −0.1 0.0 +0.1 % FS
Gain Error Drift 1 ppm/°C
ANALOG INPUT
Input Voltage Range 1 At ADCIN 0 VREF V
DC Leakage Current −1 +1 µA
Input Capacitance 2 During acquisition phase 10 pF
Outside acquisition phase 1.5 pF
Multiplexer On Resistance VDD = 5.0 V 50 Ω
VDD = 2.5 V 100 Ω
VOLTAGE REFERENCE INPUT/OUTPUT
REFOUT 3 Internal reference output, TA = 25°C 2.49 2.5 2.51 V
REFIN3 External reference input 1.0 VDD V
Drift 5 ppm/°C
Power-On Time CREF = 2.2 µF 50 ms
LOGIC INPUTS
Input Voltage
High (VIH) 0.7 × VDRIVE V
Low (VIL) 0.3 × VDRIVE V
Input Current (IIN) VIN = 0 V or VDRIVE −1 0.01 +1 µA
LOGIC OUTPUTS
Output Voltage
High (VOH) ISOURCE = 200 µA VDRIVE − 0.2 V
Low (VOL) ISINK = 200 µA 0.4 V
Floating State Leakage Current −1 +1 µA
Output Coding Straight (natural) binary

Rev. A | Page 3 of 34
AD7091R-5 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
CONVERSION RATE
Conversion Time 550 ns
Update Rate
Autocycle Setting 00 90 100 110 μs
Autocycle Setting 01 180 200 220 μs
Autocycle Setting 10 360 400 440 μs
Autocycle Setting 11 720 800 880 μs
Throughput Rate fSCL = 400 kHz, command mode 22.22 kSPS
POWER REQUIREMENTS
VDD 2.7 5.25 V
VDRIVE Range 1.8 5.25 V
IDD VIN = 0 V
Normal Mode—Static VDD = 5.25 V 22 50 µA
VDD = 3 V 21.6 46 µA
Normal Mode—Operational VDD = 5.25 V, fSCL = 400 kHz 26 55 µA
VDD = 3 V, fSCL = 400 kHz 24 52 µA
VDD = 5.25 V, fSCL = 100 kHz 25 54 µA
VDD = 3 V, fSCL = 100 kHz 23 51 µA
VDD = 3 V, autocycle mode 70 105 µA
Power-Down Mode VDD = 5.25 V 0.550 17 µA
VDD = 5.25 V, TA = −40°C to +85°C 0.550 8 µA
VDD = 3 V 0.435 15 µA
IDRIVE VIN = 0 V
Normal Mode—Static VDRIVE = 5.25 V 2 4 µA
VDRIVE = 3 V 1 3.5 µA
Normal Mode—Operational VDRIVE = 5.25 V, fSCL = 400 kHz 6 15 µA
VDRIVE = 3 V, fSCL = 400 kHz 5 14 µA
VDRIVE = 5.25 V, fSCL = 100 kHz 5 14 µA
VDRIVE = 3 V, fSCL = 100 kHz 4 13 µA
Total Power Dissipation 4 VIN = 0 V
Normal Mode—Static VDD = VDRIVE = 5.25 V 130 290 µW
VDD = VDRIVE = 3 V 70 150 µW
Normal Mode—Operational VDD = VDRIVE = 5.25 V, fSCL = 400 kHz 170 370 µW
VDD = VDRIVE = 3 V, fSCL = 400 kHz 90 200 µW
VDD = VDRIVE = 5.25 V, fSCL = 100 kHz 160 360 µW
VDD = VDRIVE = 3 V, fSCL = 100 kHz 85 195 µW
VDD = VDRIVE = 3 V, autocycle mode 210 315 µW
Power-Down Mode VDD = 5.25 V 3 95 µW
VDD = 5.25 V, TA = −40°C to +85°C 3 33 µW
VDD = VDRIVE = 3 V 1.4 50 µW
1
The multiplexer input voltage must not exceed VDD.
2
Sample tested during initial release to ensure compliance.
3
When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, see the Pin Configurations and Function Descriptions section.
4
Total power dissipation includes contributions from VDD, VDRIVE, and REFIN (see Note 3).

Rev. A | Page 4 of 34
Data Sheet AD7091R-5
I2C TIMING SPECIFICATIONS
All values measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with rise time and fall time measured
between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, VREF = 2.5 V internal/external, TA =
TMIN to TMAX, unless otherwise noted.

Table 2.
Limit at TMIN, TMAX
Parameter Min Typ Max Unit Description
fSCL 100 kHz Serial clock frequency, standard mode
400 kHz Fast mode
t1 4 µs SCL high time, standard mode
0.6 µs Fast mode
t2 4.7 µs SCL low time, standard mode
1.3 µs Fast mode
t3 250 ns Data setup time, standard mode
100 ns Fast mode
t4 1 0 3.45 µs Data hold time, standard mode
0 0.9 µs Fast mode
t5 4.7 µs Setup time for a repeated start condition, standard mode
0.6 µs Fast mode
t6 4 µs Hold time for a repeated start condition, standard mode
0.6 µs Fast mode
t7 4.7 µs Bus-free time between a stop and a start condition, standard mode
1.3 µs Fast mode
t8 4 µs Setup time for a stop condition, standard mode
0.6 µs Fast mode
t9 1000 ns Rise time of the SDA signal, standard mode
20 + 0.1CB 300 ns Fast mode
t10 300 ns Fall time of the SDA signal, standard mode
20 + 0.1CB 300 ns Fast mode
t11 1000 ns Rise time of the SCL signal, standard mode
20 + 0.1CB 300 ns Fast mode
t11A 1000 ns Rise time of the SCL signal after a repeated; not shown in Figure 2, standard mode
20 + 0.1CB 300 ns Start condition and after an acknowledge bit, fast mode
t12 300 ns Fall time of the SCL signal, standard mode
20 + 0.1CB 300 ns Fast mode
tSP 0 50 ns Pulse width of the suppressed spike; not shown in Figure 2, fast mode
tRESETPW 10 ns RESET pulse width (see Figure 35)
tRESET_DELAY 50 ns RESET pulse delay upon power-up (see Figure 35)
1
A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
t11 t12
t2 t6

SCL

t6 t4 t3 t5 t8
t1
t10 t9

SDA
t7
P S S P
12093-002

S = START CONDITION
P = STOP CONDITION

Figure 2. 2-Wire Serial Interface Timing Diagram

Rev. A | Page 5 of 34
AD7091R-5 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device
Table 3. soldered in a circuit board for surface-mount packages.
Parameter Rating
VDD to GND −0.3 V to +7 V Table 4. Thermal Resistance
VDRIVE to GND −0.3 V to +7 V Package Type θJA θJC Unit
Analog Input Voltage to GND −0.3 V to VREF + 0.3 V 20-Lead LFCSP_WQ 52 6.5 °C/W
Digital Input1 Voltage to GND −0.3 V to VDRIVE + 0.3 V 20-Lead TSSOP 84.3 18.4 °C/W
Digital Output2 Voltage to GND −0.3 V to VDRIVE + 0.3 V
Input Current to Any Pin Except
Supplies3 ±10 mA ESD CAUTION
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
ESD
Human Body Model (HBM) 1.5 kV
Field Induced Charged Device 500 V
Model (FICDM)
1
The digital input pins include the following: AS0, RESET, AS1, SCL, SDA,
and CONVST/GPO1.
2
The digital output pins include: ALERT/BUSY/GPO0, GPO2, and SDA.
3
Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 6 of 34
Data Sheet AD7091R-5

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

17 CONVST/GPO1
20 RESET

18 VDRIVE

16 SCL
19 AS0
AS0 1 20 VDRIVE
RESET 2 19 CONVST/GPO1 VDD 1 15 SDA

VDD 3 18 SCL REGCAP 2 14 AS1

AD7091R-5
REGCAP 4 AD7091R-5 17 SDA REFIN/REFOUT 3 TOP VIEW 13 GND
TOP VIEW (Not to Scale)
REFIN/REFOUT 5 (Not to Scale) 16 AS1 GND 4 12 ADCIN
MUXOUT 5 11 VIN1
GND 6 15 GND
MUXOUT 7 14 ADCIN

VIN0 6
VIN2 7
ALERT/BUSY/GPO0 8

GPO2 9
VIN3 10
VIN0 8 13 VIN1
VIN2 9 12 VIN3
12093-004
ALERT/BUSY/GPO0 10 11 GPO2

NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS NOT CONNECTED

12093-003
INTERNALLY. IT IS RECOMMENDED THAT THE PAD BE
SOLDERED TO GND.
Figure 3. Pin Configuration, 20-Lead TSSOP Figure 4. Pin Configuration, 20-Lead LFCSP

Table 5. Pin Function Descriptions

Pin No.
TSSOP LFCSP Mnemonic Description
1 19 AS0 I2C Address Bit 0. Together with AS1, the logic state of these two inputs selects a unique I2C
address for the AD7091R-5. The device address depends on the logic state of these pins.
2 20 RESET Reset. Logic input. This pin resets the device when pulled low.
3 1 VDD Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
4 2 REGCAP Decoupling Capacitor Pin for Voltage Output from the Internal Regulator. Decouple this output
pin separately to GND using a 2.2 µF capacitor.
5 3 REFIN/REFOUT Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended
decoupling capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or
overdrive the internal reference with the voltage applied to this pin. The reference voltage range for
an externally applied reference is 1.0 V to VDD.
6, 15 4, 13 GND Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-5.
7 5 MUXOUT Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
8 6 VIN0 Analog Input for Channel 0. Single-ended analog input. The analog input range is 0 V to VREF.
9 7 VIN2 Analog Input for Channel 2. Single-ended analog input. The analog input range is 0 V to VREF.
10 8 ALERT/BUSY/GPO0 This is a multifunction pin determined by the configuration register.
Alert Output Pin (ALERT). When functioning as ALERT, this pin is a logic output indicating that a
conversion result has fallen outside the limit of the register settings.
Busy Output (BUSY). The BUSY pin indicates when a conversion is taking place.
General-Purpose Digital Output 0 (GPO0).
11 9 GPO2 General-Purpose Digital Output 2.
12 10 VIN3 Analog Input for Channel 3. Single-ended analog input. The analog input range is 0 V to VREF.
13 11 VIN1 Analog Input for Channel 1. Single-ended analog input. The analog input range is 0 V to VREF.
14 12 ADCIN ADC Input. This pin allows direct access to the ADC. If no external filtering or buffering is
required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the conditioning
network to the MUXOUT pin.

Rev. A | Page 7 of 34
AD7091R-5 Data Sheet
Pin No.
TSSOP LFCSP Mnemonic Description
16 14 AS1 I2C Address Bit 1. Together with AS0, the logic state of these two inputs selects a unique I2C
address for the AD7091R-5. The device address depends on the logic state of these pins.
17 15 SDA Serial Data Input/Output. This open-drain output requires a pull-up resistor. The output coding is
straight binary for the voltage channels.
18 16 SCL Digital Input Serial I2C Bus Clock. This input requires a pull-up resistor. The data transfer rate in I2C
mode is compatible with both 100 kHz (standard mode) and 400 kHz (fast mode) operating
modes.
19 17 CONVST/GPO1 This is a multifunction pin determined by the configuration register and mode of conversion.
Convert Start Input Signal (CONVST). Edge triggered logic input. The falling edge of CONVST
places the ADC into hold mode and initiates a conversion. The logic level of CONVST at EOC
controls the power modes of the AD7091R-5.
General-Purpose Digital Output 1 (GPO1). When in command or autocycle mode, this pin can
function as a general-purpose digital output.
20 18 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the
interface operates. Connect decoupling capacitors between VDRIVE and GND. The typical
recommended values are 10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and
may differ from the voltage range at VDD, but must never exceed it by more than 0.3 V.
N/A 1 21 EPAD Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to GND.
1
N/A means not applicable.

Rev. A | Page 8 of 34
Data Sheet AD7091R-5

TYPICAL PERFORMANCE CHARACTERISTICS

1.0 1.0

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

DNL (LSB)
INL (LSB)

0 0

–0.2 –0.2

–0.4 VDD = 3.0V –0.4 VDD = 3.0V

VREF = 2.5V VREF = 2.5V
–0.6 fSCL = 400kHz –0.6 fSCL = 400kHz
TA = 25°C TA = 25°C
–0.8 POSITIVE INL = +0.43 LSB –0.8 POSITIVE DNL = +0.41 LSB
NEGATIVE INL = –0.66 LSB NEGATIVE DNL = –0.41 LSB
–1.0 –1.0

12093-208
12093-205
0 512 1024 1536 2048 2560 3072 3584 4095 0 512 1024 1536 2048 2560 3072 3584 4095
CODE CODE

Figure 5. INL vs. Code Figure 8. DNL vs. Code

1.0 1.0
VDD = 5.25V VDD = 5.25V
0.8 VREF = EXTERNAL 0.8 VREF = EXTERNAL
fSCL = 400kHz fSCL = 400kHz
0.6 TA = 25°C 0.6 TA = 25°C
MAX DNL (LSB)
0.4 MAX INL (LSB) 0.4

0.2 0.2
DNL (LSB)
INL (LSB)

0 0

–0.2 –0.2

–0.4 –0.4
MIN INL (LSB) MIN DNL (LSB)
–0.6 –0.6

–0.8 –0.8

–1.0 –1.0

12093-234
12093-231

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
REFERENCE INPUT VOLTAGE (V) REFERENCE INPUT VOLTAGE (V)

Figure 6. Minimum/Maximum INL vs. External Reference Input Voltage Figure 9. Minimum/Maximum DNL vs. External Reference Input Voltage

8000 5000
VDD = VDRIVE = 3.3V VDD = VDRIVE = 3.3V
7218 VREF = 2.5V
VREF = 2.5V 4500 4353
7000 8192 SAMPLES 8192 SAMPLES
TA = 25°C 4000 TA = 25°C
3762
NUMBER OF OCCURRENCES
NUMBER OF OCCURRENCES

6000
3500
5000 3000

4000 2500

2000
3000
1500
2000
1000
1000 684 500
290 50
27
0 0
12093-209
12093-206

2028 2029 2030 2042 2043 2044 2045

CODE CODE

Figure 7. Histogram of a DC Input at Code Center Figure 10. Histogram of a DC Input at Code Transition

Rev. A | Page 9 of 34
AD7091R-5 Data Sheet
0 71 11.7
VDD = VDRIVE = 3.3V SNR
VREF = 2.5V EXTERNAL SINAD
–20 70 ENOB 11.5
TA = 25°C
fIN = 1kHz
69 11.3
ADC OUTPUT SPECTRUM (dB)

–40 fSAMPLE = 22.2kSPS

fSCL = 400kHz
SNR = 68.3dB 68 11.1

SNR, SINAD (dB)

–60 SINAD = 68.2dB

ENOB (Bits)
THD = –85.3dB 67 10.9
–80 SFDR = –88.2dB
66 10.7
–100
65 10.5
VDD = 3.0V
–120 VREF = EXTERNAL
64 10.3
fSCL = 400kHz
–140 fIN = 1kHz
63 SIGNAL AMPLITUDE = –0.5dB 10.1
TA = 25°C
–160 62 9.9

12093-207

12093-213
0 2000 4000 6000 8000 10000 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (Hz) REFERENCE INPUT VOLTAGE (V)

Figure 11. 10 kHz FFT, VDD = 3.0 V, VREF = 2.5 V External Figure 14. SNR, SINAD, and ENOB vs. Reference Input Voltage

0 –70
VDD = VDRIVE = 3.3V VDD = 3.3V
VREF = 2.5V INTERNAL –72 VREF = 2.5V
–20 fIN = 1kHz SIGNAL AMPLITUDE = –0.5dB
fSAMPLE = 22.2kSPS –74 fSCL = 400kHz
ADC OUTPUT SPECTRUM (dB)

–40 fSCL = 400kHz TA = 25°C

SNR = 68.4dB –76
SINAD = 68.2dB
–60 THD = –83.3dB –78
SFDR = –87.9dB
THD (dB)

–80 –80

–82
–100
–84
–120
–86
–140
–88

–160 –90
12093-210

12093-109
0 2000 4000 6000 8000 10000 1 10 100
FREQUENCY (Hz) ANALOG INPUT FREQUENCY (kHz)

Figure 12. 10 kHz FFT, VDD = 3.0 V, VREF = 2.5 V Internal Figure 15. THD vs. Analog Input Frequency

70 70.0
SNR
SINAD
69.5
69
69.0

68
SNR, SINAD (dB)

68.5
SNR (dB)

67 68.0

67.5
66

VDD = 3.3V 67.0 VDD = 3.0V

VREF = 2.5V VREF = 2.5V
65 SIGNAL AMPLITUDE = –0.5dB
66.5 fSCL = 400kHz
fSCL = 400kHz fIN = 1kHz
TA = 25°C TA = 25°C
64 66.0
12093-215
12093-108

1 10 100 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0
INPUT FREQUENCY (kHz) INPUT LEVEL (dB)

Figure 13. SNR, SINAD vs. Input Frequency Figure 16. SNR vs. Input Level

Rev. A | Page 10 of 34
Data Sheet AD7091R-5
–75 50
THD VDD = 3.0V VDD = 3.0V 2.70V
SFDR VREF = EXTERNAL

OPERATIONAL IDD SUPPLY CURRENT (µA)

–77 VREF = INTERNAL 2.5V 3.00V
fSCL = 400kHz 45 fSCL = 400kHz 5.25V
–79 fIN = 1kHz
SIGNAL AMPLITUDE = –0.5dB 40
–81 TA = 25°C
THD, SFDR (dB)

35
–83

–85 30

–87
25
–89
20
–91
15
–93

–95 10

12093-216

12093-220
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –55 25 85 125
REFERENCE INPUT VOLTAGE (V) TEMPERATURE (°C)

Figure 17. THD, SFDR vs. Reference Input Voltage Figure 20. Operational IDD Supply Current vs. Temperature
for Various VDD Supply Voltages
–80 8

–81
7

TOTAL POWER-DOWN CURRENT (µA)

–82
6 5.25V
–83 5.0V
3.3V
5 2.7V
–84
THD (dB)

–85 4
VDD = 5.0V
–86
fSCL = 400kHz 3
–87 fIN = 1kHz
2
–88
1
–89

–90 0
12093-129

12093-127
–55 –35 –15 5 25 45 65 85 105 125 –40 25 85 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 18. THD vs. Temperature Figure 21. Total Power-Down Current vs. Temperature for Various Supply
Voltages
68.8 2.510
VDD = VDRIVE = 3.0V –55°C
68.6 –40°C
+25°C
68.4 VDD = 3.0V +85°C
VREF = 2.5V 2.505 +125°C
fSCL = 400kHz
68.2 fIN = 1kHz
SNR (dB)

68.0
VREF (V)

2.500
67.8

67.6

2.495
67.4

67.2

67.0 2.490
12093-122

12093-223

–55 –35 –15 5 25 45 65 85 105 125 0 10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C) CURRENT LOAD (µA)

Figure 19. SNR vs. Temperature Figure 22. Reference Voltage Output (VREF) vs. Current Load
for Various Temperatures

Rev. A | Page 11 of 34
AD7091R-5 Data Sheet
1.5 0.10
VDD = 3.0V OFFSET ERROR CH 0 VDD = 3.0V GAIN ERROR CH 0
VREF = 2.5V OFFSET ERROR CH 1 0.08 VREF = 2.5V GAIN ERROR CH 1
fSCL = 400kHz OFFSET ERROR CH 2 fSCL = 400kHz GAIN ERROR CH 2
1.0 OFFSET ERROR CH 3 GAIN ERROR CH 3
0.06

0.04
OFFSET ERROR (mV)

GAIN ERROR (% FS)

0.5
0.02

0 0

–0.02
–0.5
–0.04

–0.06
–1.0
–0.08

–1.5 –0.10

12093-224

12093-227
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 23. Offset Error vs. Temperature Figure 26. Gain Error vs. Temperature

1.5 0.10
VDD = 3.0V VDD = 3.0V
VREF = 2.5V 0.08 VREF = 2.5V
fSCL = 400kHz fSCL = 400kHz
1.0
0.06
OFFSET ERROR MATCH (mV)

GAIN ERROR MATCH (% FS) 0.04

0.5
0.02

0 0

–0.02
–0.5
–0.04

–0.06
–1.0
–0.08

–1.5 –0.10

12093-328
12093-325

–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 24. Offset Error Match vs. Temperature Figure 27. Gain Error Match vs. Temperature

105 –80
VDD = 3.0V
fSAMPLE = 22.22kSPS
EXTERNAL REFERENCE
CHANNEL TO CHANNEL ISOLATION (dB)

f = 400kHz
100 –85 SCL
TA = 25°C

95 –90
INTERNAL REFERENCE
PSRR (dB)

90 –95

85 –100

VDD = 3.0V –105

80
VREF = 2.5V
fSCL = 400kHz
TA = 25°C
75 –110
12093-229
12093-326

1k 10k 100k 1M 1 10 100

RIPPLE FREQUENCY (Hz) INPUT FREQUENCY (kHz)

Figure 25. PSRR vs. Ripple Frequency Figure 28. Channel to Channel Isolation vs. Input Frequency

Rev. A | Page 12 of 34
Data Sheet AD7091R-5
–85 2.510
VDD = 3.0V
–87 fSAMPLE = 22.22kSPS
CHANNEL TO CHANNEL ISOLATION (dB)

INTERNAL REFERENCE VOLTAGE (V)

fSCL = 400kHz
–89 fIN = 1kHz
2.505
–91

–93

–95 2.500

–97

–99
2.495
–101

–103

–105 2.490

12093-230

12093-135
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 29. Channel to Channel Isolation vs. Temperature Figure 31. Internal Reference Voltage vs. Temperature

–50
TA = 25°C
VDD = 3V
–55 fIN = 10kHz
fSCL = 400kHz
–60

–65
THD (dB)

–70

–75

–80

–85
12093-110

10 100 1k 10k
SOURCE IMPEDANCE (Ω)

Figure 30. THD vs. Source Impedance

Rev. A | Page 13 of 34
AD7091R-5 Data Sheet

TERMINOLOGY
Integral Nonlinearity (INL) Channel to Channel Isolation
INL is the maximum deviation from a straight line passing Channel to channel isolation is a measure of the level of crosstalk
through the endpoints of the ADC transfer function. For the between the selected channel and all the other channels. It is
AD7091R-5, the endpoints of the transfer function are zero measured by applying a full-scale, 10 kHz sine wave signal to all
scale, a point ½ LSB below the first code transition, and full unselected input channels and determining the degree to which
scale, a point ½ LSB above the last code transition. the signal attenuates in the selected channel that has a dc signal
applied to it. Figure 28 shows the worst case across all channels
Differential Nonlinearity (DNL) for the AD7091R-5.
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC. Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
Offset Error For the AD7091R-5, it is defined as
The offset error is the deviation of the first code transition
(00 … 000 to 00 … 001) from the ideal (such as GND + 0.5 LSB). V2 2 + V3 2 + V4 2 + V5 2 + V6 2
THD (dB ) = 20 log
Offset Error Match V1
Offset error match is the difference in offset error between any where:
two input channels. V1 is the rms amplitude of the fundamental.
Gain Error V2, V3, V4, V5, and V6 are the rms amplitudes of the second
For the AD7091R-5, the gain error is the deviation of the last through the sixth harmonics.
code transition (111 … 110 to 111 … 111) from the ideal (such Peak Harmonic or Spurious Noise
as VREF − 1.5 LSB) after the offset error has been adjusted out. Peak harmonic or spurious noise is defined as the ratio of the
Gain Error Match rms value of the next largest component in the ADC output
Gain error match is the difference in gain error between any spectrum (up to fS/2 and excluding dc) to the rms value of the
two input channels. fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however,
Transient Response Time
for ADCs where the harmonics are buried in the noise floor, it
The track-and-hold amplifier returns to track mode after the
is a noise peak.
end of conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±0.5 LSB, after the end of conversion.
See the I2C Interface section for more details.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of the signal-to-noise-and-distortion
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical SINAD for an ideal N-bit converter with
a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) (dB)
Thus, for a 12-bit converter, the SINAD ratio is 74 dB.

Rev. A | Page 14 of 34
Data Sheet AD7091R-5

THEORY OF OPERATION
CIRCUIT INFORMATION When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced (see
The AD7091R-5 is a 12-bit, ultra low power single-supply ADC. Figure 33). Using the control logic, the charge redistribution DAC
The device operates from a 2.7 V to 5.25 V supply. The AD7091R-5 adds and subtracts fixed amounts of charge from the sampling
can function in both standard and fast I2C operating modes. capacitor to bring the comparator back into a balanced condition.
The AD7091R-5 provides a 4:1 multiplexer and an on-chip, When the SAR decisions are made, the comparator inputs are
track-and-hold amplifier, and is housed in either a 20-lead rebalanced. From these SAR decisions, the control logic
LFCSP or 20-lead TSSOP package. These packages offer con- generates the ADC output code.
siderable space-saving advantages over alternative solutions.
ADC TRANSFER FUNCTION
The serial clock input accesses data from the device. An inter-
nally generated clock is implemented to control the successive The output coding of the AD7091R-5 is straight binary. The
approximation ADC. The reference voltage for the AD7091R-5 designed code transitions occur midway between successive
is provided externally or is generated internally by an accurate integer LSB values, such as ½ LSB and 1½ LSB. The LSB size for the
on-chip reference source. The analog input range for the AD7091R-5 is VREF/4096. The ideal transfer characteristic for
AD7091R-5 is 0 V to VREF. the AD7091R-5 is shown in Figure 34.

The AD7091R-5 also features a power-down option to save

111...111
power between conversions. The power-down feature is 111...110
accessed through the standard serial interface as described in

ADC CODE
the Modes of Operation section. 111...000
1LSB = VREF /4096
CONVERTER OPERATION 011...111

The AD7091R-5 is a successive approximation ADC based on a 000...010

charge redistribution digital-to-analog converter (DAC). Figure 32 000...001
000...000

12093-017
and Figure 33 show simplified schematics of the ADC. Figure 32 0V 1LSB +VREF – 1LSB
ANALOG INPUT
shows the ADC during its acquisition phase. When Switch 2 (SW2)
Figure 34. Transfer Characteristic
is closed and Switch 1 (SW1) is in Position A, the comparator is
held in a balanced condition, and the sampling capacitor REFERENCE
acquires the signal on ADCIN. The AD7091R-5 can operate with either the internal 2.5 V on-chip
CHARGE reference or an externally applied reference. The logic state of
REDISTRIBUTION
DAC the P_DOWN LSB bit in the configuration register determines
SAMPLING whether the internal reference is used. The internal reference is
CAPACITOR
ADCIN
A selected for the ADCs when the P_DOWN LSB bit is set to 1.
SW1 CONTROL
B ACQUISITION
LOGIC When the P_DOWN LSB bit is set to 0, supply an external
PHASE SW2
COMPARATOR reference in the range of 2.5 V to VDD through the REFIN/
12093-015

GND
VDD/2 REFOUT pin. At power-up, the internal reference disables by
default.
Figure 32. ADC Acquisition Phase
The internal reference circuitry consists of a 2.5 V band gap
CHARGE
REDISTRIBUTION
reference and a reference buffer. When operating the AD7091R-5
DAC in internal reference mode, the 2.5 V internal reference is available
SAMPLING
CAPACITOR
at the REFIN/REFOUT pin, which is typically decoupled to GND
A
ADCIN
CONTROL
using a 2.2 µF capacitor. It is recommended to buffer the internal
SW1
B CONVERSION SW2 LOGIC reference before applying it elsewhere in the system.
PHASE
COMPARATOR The reference buffer requires 50 ms to power up and charge the
12093-016

GND
VDD/2 2.2 µF decoupling capacitor.
Figure 33. ADC Conversion Phase

Rev. A | Page 15 of 34
AD7091R-5 Data Sheet
POWER SUPPLY ANALOG INPUT
The AD7091R-5 uses two power supply pins: a core supply (VDD) Figure 36 shows an equivalent circuit of the analog input structure
and a digital input/output interface supply (VDRIVE). VDRIVE allows of the AD7091R-5. The two diodes, D1 and D2, provide ESD
direct interfacing with any logic between 1.8 V and 5.25 V. To protection for the analog input. Ensure that the analog input
reduce the number of supplies needed, VDRIVE and VDD can be signal never exceeds the supply rails by more than 300 mV
tied together depending upon the logic levels of the system. The because this causes these diodes to become forward-biased and
AD7091R-5 is independent of power supply sequencing between start conducting current into the substrate. These diodes can
VDRIVE and VDD. Additionally, the AD7091R-5 is insensitive to conduct a maximum of 10 mA without causing irreversible
power supply variations over a wide frequency range, as shown damage to the device.
in Figure 25. REFIN/
VDD REFOUT
The AD7091R-5 powers down automatically at the end of each
conversion phase; therefore, the power scales linearly with the D1 D3
C2
R1 3.6pF
sampling rate. The automatic power-down feature makes the VINx
500Ω

AD7091R-5 device ideal for low sampling rates (of even a few
C1 D2
hertz) and battery-powered applications. 400fF

Table 6. Recommended Power Management Devices1

12093-019
CONVERSION PHASE SWITCH OPEN
Product Description TRACK PHASE SWITCH CLOSED
ADP7102 20 V, 300 mA, low noise, CMOS LDO Figure 36. Equivalent Analog Input Circuit
ADM7160 Ultralow noise, 200 mA linear regulator
ADP162 Ultralow quiescent current, CMOS linear regulator
The C1 capacitor in Figure 36 is typically approximately 400 fF
and can primarily be attributed to pin capacitance. The R1 resistor
1
For the latest recommended power management devices, see the AD7091R-5 is a lumped component made up of the on resistance of a switch.
product page.
This resistor is typically approximately 500 Ω. The C2 capacitor
DEVICE RESET is the ADC sampling capacitor and typically has a capacitance of
Upon power-up, a reset pulse of at least 10 ns in width must be 3.6 pF.
provided on the RESET pin to ensure proper initialization of In applications where harmonic distortion and SNR are critical,
the device. Failure to apply the reset pulse may result in a device drive the analog inputs from low impedance sources. Large source
malfunction. See Figure 35 for reset pulse timing relative to impedances significantly affect the ac performance of the ADC,
power supply establishment. which can necessitate using input buffer amplifiers, as shown in
Figure 37. The choice of the op amp is a function of the
At any time, the RESET pin can reset the device and the
particular application.
contents of all internal registers, including the command register,
to their default state. To activate the reset operation, bring When no amplifiers are driving the analog input, limit the source
the RESET pin low for a minimum of 10 ns while it is impedance to low values. The maximum source impedance depends
asynchronous to the SCL signal. It is imperative that the RESET on the amount of THD that can be tolerated. The THD increases
pin be held at a stable logic level at all times to ensure normal as the source impedance increases and performance degrades.
operation. Use an external filter on the analog input signal paths to the
tRESET_DELAY AD7091R-5 VINx pins to achieve the specified performance.
This filter can be a one-pole, low-pass RC filter or similar.
VDD
Connect the MUXOUT pin directly to the ADCIN pin. Insert a buffer
amplifier in the path, if desired. When sequencing channels, do
VDRIVE
not place a filter between MUXOUT and the input to any buffer
tRESETPW
because doing so leads to crosstalk. If a buffer is not implemented,
12093-141

RESET do not place a filter between MUXOUT and ADCIN when sequencing
Figure 35. RESET Pin Power Up Timing
channels because doing so leads to crosstalk.

Rev. A | Page 16 of 34
Data Sheet AD7091R-5
DRIVER AMPLIFIER CHOICE TYPICAL CONNECTION DIAGRAM
Although the AD7091R-5 is easy to drive, a driver amplifier Figure 37 and Figure 38 show typical connection diagrams for the
must meet the following requirements: AD7091R-5.
• Keep the noise generated by the driver amplifier as low as Connect a positive power supply in the 2.7 V to 5.25 V range to
possible to preserve the SNR and transition noise performance the VDD pin. The typical values for the VDD decoupling capacitors
of the AD7091R-5. The noise from the driver is filtered by are 100 nF and 10 µF. Place these capacitors as close as possible
the one-pole, low-pass filter of the AD7091R-5 analog input to the device pins. Take care to decouple the REFIN/REFOUT pin
circuit, made by R1 and C2, or by the external filter, if one to achieve specified performance. The typical value for the
is used. Because the typical noise of the AD7091R-5 is 350 µV REFIN/REFOUT capacitor is 2.2 µF, which provides an analog input
rms, the SNR degradation due to the amplifier is range of 0 V to VREF. The typical value for the regulator bypass
(REGCAP) decoupling capacitor is 1 µF. The voltage applied to the
  VDRIVE input controls the voltage of the serial interface; therefore,
 
350
SNR LOSS = 20 log   connect this pin to the supply voltage of the microprocessor. Set
 π  VDRIVE in the 1.8 V to 5.25 V range. The typical values for the
 350 2 + f −3dB ( Ne N ) 2 
 2  VDRIVE decoupling capacitors are 100 nF and 10 µF. The 16-bit
conversion result (3 address bits, 1 alert bit, and 12 data bits) is
where:
output in 2 bytes with the most significant byte (MSBs)
f−3dB is the input bandwidth, in megahertz, of the AD7091R-5
presented first.
(1.5 MHz), or the cutoff frequency of the input filter, if one
is used. When an externally applied reference is required, disable the
N is the noise gain of the amplifier (for example, gain = 1 internal reference using the configuration register. Choose an
in a buffered configuration; see Figure 37). externally applied reference voltage in the range of 1.0 V to VDD
eN is the equivalent input noise voltage of the op amp, in and connect it to the REFIN/REFOUT pin.
nV/√Hz. For applications where power consumption is a concern, use the
• For ac applications, the driver must have a THD power-down mode of the ADC to improve power performance.
performance that is commensurate with the AD7091R-5. See the Modes of Operation section for additional details.
• If a buffer is placed between MUXOUT and ADCIN, the driver
amplifier and the AD7091R-5 analog input circuit must
settle for a full-scale step onto the capacitor array at a 12-bit
level (0.0244%, 244 ppm). In an amplifier data sheet,
settling at 0.1% to 0.01% is more commonly specified and
may differ significantly from the settling time at a 12-bit
level. Be sure to verify the amplifier settling time before
driver selection.

Table 7. Recommended Driver Amplifiers

Product Description1
ADA4805-1 Low noise, low power, wide bandwidth amplifier
AD8031 Low voltage, low power, single channel amplifier
AD8032 Low voltage, low power, dual channel amplifier
AD8615 Low frequency, low voltage amplifier
1
For the latest recommended ADC driver products, see the AD7091R-5
product page.

Rev. A | Page 17 of 34
AD7091R-5 Data Sheet
VDRIVE

47kΩ

10µF 100nF 10µF 100nF

VDD VDRIVE SDA MICROCONTROLLER/

MICROPROCESSOR/
REGCAP DSP
SCL
1µF
AS1
AD7091R-5
AS0
ANALOG VIN0
INPUT
CONVST/GPO1

ALERT/BUSY/GPO0

ADCIN
ANALOG VIN3
INPUT REFIN/
GND REFOUT MUXOUT

2.2µF

33Ω

12093-018
560pF
OPTIONAL
BUFFER

Figure 37. Typical Connection Diagram with Optional Buffer

VDRIVE

47kΩ

10µF 100nF 10µF 100nF

VDD VDRIVE SDA MICROCONTROLLER/

MICROPROCESSOR/
REGCAP DSP
SCL
1µF
AS1
AD7091R-5
33Ω AS0
VIN0
ANALOG CONVST/GPO1
INPUT 560pF
ALERT/BUSY/GPO0

33Ω ADCIN
VIN3 REFIN/
ANALOG REFOUT MUXOUT
INPUT GND
560pF
12093-140

2.2µF

Figure 38. Typical Connection Diagram Without Optional Buffer

Rev. A | Page 18 of 34
Data Sheet AD7091R-5

I2C REGISTERS
The AD7091R-5 has several user-programmable registers. Table 9 When the transaction is complete, the master can maintain
contains the complete list of registers. control of the bus, initiating a new transaction by generating
another start bit (high to low transition on SDA while SCL is
The registers are either read/write (R/W) or read only (R). Data high). This is known as a repeated start. Alternatively, the bus
can be written to or read back from the read/write registers. can be relinquished by releasing the SCL line followed by the
Read only registers can only be read. Any write to a read only SDA line. This low to high transition on SDA while SCL is high
register or unimplemented register address is considered no is known as a stop bit (P), and it leaves the I2C bus in its idle
operation (NOP) command, which is an I2C command that the state (no current is consumed by the bus).
AD7091R-5 ignores. After a write to a read only register, the
output on the subsequent I2C frame is all zeros provided that SLAVE ADDRESS
there was no conversion before the next I2C frame. Similarly, any The first byte that the user writes to the device is the slave
read of an unimplemented register outputs zeros. address byte. The AD7091R-5 has a 7-bit slave address. On the
ADDRESSING REGISTERS AD7091R-5, the three MSBs of the 7-bit slave address are fixed
to 3’b010. The four LSBs are set by the user via external pins.
A serial transfer on the AD7091R-5 consists of nine SCL cycles. Two address select pins are on each device, and high, low, or no
Data is sent over the serial bus in groups of nine bits—eight bits connect can be detected on each pin, giving nine combinations.
of data from the transmitter followed by an acknowledge bit from
the receiver. Data transitions on the SDA line must occur during Table 8 shows the four LSBs of the slave address for the AD7091R-5
the low period of the clock signal and remain stable during the for different configurations of the address select pins.
high period. The receiver pulls the SDA line low during the Table 8. Slave Addresses
acknowledge bit to signal that the preceding byte has been received
AS11 AS01 A3 A2 A1 A0
correctly. If this is not the case, cancel the transaction. The first
VDD VDD 0 0 0 0
byte that the master sends must consist of a 7-bit slave address,
VDD NC 0 0 1 0
followed by a data direction bit. Each device on the bus has a
VDD GND 0 0 1 1
unique slave address; therefore, the first byte sets up communication
NC VDD 1 0 0 0
with a single slave device for the duration of the transaction.
NC NC 1 0 1 0
The transaction can be used either to write to a slave device (data NC GND 1 0 1 1
direction bit = 0) or to read data from it (data direction bit = 1). In GND VDD 1 1 0 0
the case of a read transaction, it is often necessary to first write GND NC 1 1 1 0
to the slave device (in a separate write transaction) to tell it GND GND 1 1 1 1
from which register to read. Reading and writing cannot be
combined in one transaction.
1
NC means leave the ASx pins floating, VDD means pulled high, and GND
means pulled low.
I2C REGISTER ACCESS
Table 9. Register Descriptions
Address Register Name Default Access
0x00 Conversion result 0x0000 R
0x01 Channel 0x0000 R/W
0x02 Configuration 0x00C0 R/W
0x03 Alert indication 0x0000 R
0x04 Channel 0 low limit 0x0000 R/W
0x05 Channel 0 high limit 0x01FF R/W
0x06 Channel 0 hysteresis 0x01FF R/W
0x07 Channel 1 low limit 0x0000 R/W
0x08 Channel 1 high limit 0x01FF R/W
0x09 Channel 1 hysteresis 0x01FF R/W
0x0A Channel 2 low limit 0x0000 R/W
0x0B Channel 2 high limit 0x01FF R/W
0x0C Channel 2 hysteresis 0x01FF R/W
0x0D Channel 3 low limit 0x0000 R/W
0x0E Channel 3 high limit 0x01FF R/W
0x0F Channel 3 hysteresis 0x01FF R/W

Rev. A | Page 19 of 34
AD7091R-5 Data Sheet
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit, read only register that stores the results from the most recent ADC conversion in straight binary
format. The channel ID of the converted channel and the alert status are also included in this register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[ 1 5 ] RSV ( R) [ 1 1 :0 ] CO N V_RESULT ( R)
Re se rve d 12 -b it Co nve rsio n re sult
[ 1 4 :1 3 ] CH _ID ( R) [ 1 2 ] ALERT ( R)
2 -b it Channe l ID Ale rt flag
0 : No Ale rt.
1: Ale rt has o ccure d .

Table 10. Conversion Result Bit Map

MSB LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
RSV CH_ID ALERT CONV_RESULT

Table 11. Bit Descriptions for the Conversion Result Register

Bit(s) Name Description Reset Access
15 RSV Reserved 0x0 R
[14:13] CH_ID 2-bit channel ID of the channel converted 0x0 R
B14 B13 Analog Input Channel
0 0 Channel 0
0 1 Channel 1
1 0 Channel 2
1 1 Channel 3
12 ALERT Alert flag 0x0 R
0: no alert occurred
1: alert has occurred
[11:0] CONV_RESULT 12-bit conversion result 0x000 R

Rev. A | Page 20 of 34
Data Sheet AD7091R-5
CHANNEL REGISTER
The channel register on the AD7091R-5 is an 8-bit, read/write register. Each of the four analog input channels has one corresponding bit in
the channel register. To select a channel for inclusion in the channel conversion sequence, set the corresponding channel bit to 1 in the
channel register. There is a latency of one conversion before the channel conversion sequence is updated. If the channel register is
programmed with a new value, the conversion sequence is reset to the lowest numbered channel in the new value.
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[ 7 :4 ] RS V ( R) [ 0 ] CH 0 ( R/W )
Re se rve d Co nve rt o n Channe l 0
0 : Disab le Channe l 0 .
[ 3 ] CH 3 ( R/W ) 1: Enab le Channe l 0 .
Co nve rt o n Channe l 3
0 : Disab le Channe l 3 . [ 1 ] CH 1 ( R/W )
1: Enab le Channe l 3 . Co nve rt o n Channe l 1
0 : Disab le Channe l 1.
[ 2 ] CH 2 ( R/W ) 1: Enab le Channe l 1.
Co nve rt o n Channe l 2
0 : Disab le Channe l 2 .
1: Enab le Channe l 2 .

Table 12. Channel Bit Map

MSB LSB
B7 B6 B5 B4 B3 B2 B1 B0
RSV CH3 CH2 CH1 CH0

Table 13. Bit Descriptions for the Channel Register

Bit(s) Name Description Reset Access
[7:4] RSV Reserved 0x00 R
3 CH3 Convert on Channel 3 0x0 R/W
0: disable Channel 3
1: enable Channel 3
2 CH2 Convert on Channel 2 0x0 R/W
0: disable Channel 2
1: enable Channel 2
1 CH1 Convert on Channel 1 0x0 R/W
0: disable Channel 1
1: enable Channel 1
0 CH0 Convert on Channel 0 0x0 R/W
0: disable Channel 0
1: enable Channel 0

Rev. A | Page 21 of 34
AD7091R-5 Data Sheet
CONFIGURATION REGISTER
The configuration register is a 16-bit, read/write register that sets the operating modes of the AD7091R-5.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

[ 1 5 ] A L ER T _D R IV E_T YP E ( R /W ) [ 1 : 0 ] P _D O W N ( R /W )
D r iv e Ty p e o f ALERT/BU SY/GPO 0 p in Po w e r D o w n m o d e
0 : ALERT/BU SY/GPO 0 p in is o f o p e n - d r a in 0 0 : Mo d e 0 .
d r iv e ty p e . 0 1: Mo d e 1.
1 : ALERT/BU SY/GPO 0 p in is o f CM O S d r iv e 10 : Mo d e 2 .
ty p e . 11: Mo d e 3 .
[ 1 4 ] G P O 2 ( R /W ) [ 2 ] G P O 1 ( R /W )
Va lu e a t GPO 2 Va lu e a t GPO 1
0 : D r iv e '0 ' o n GPO 2 p in . 0 : D r iv e '0 ' o n GPO 1 p in .
1 : D r iv e '1 ' o n GPO 2 p in . 1 : D r iv e '1 ' o n GPO 1 p in .
[ 1 3 ] RS V ( R) [ 3 ] A L ER T _P O L _o r _G P O 0 ( R /W )
Re s e r v e d Po la r ity o f ALERT/BU SY/GPO 0 p in ( if ALERT_EN
is 1 ) o r v a lu e a t GPO 0
[ 1 2 ] RS V ( R) 0 : Ac tiv e LO W ALERT Po la r ity ( if ALERT_EN
Re s e r v e d is 1 ) o r GPO 0 = 0 .
[ 1 1 ] F L T R ( R /W ) 1 : Ac tiv e H IGH ALERT Po la r ity ( if ALERT_EN
En a b le Glitc h Filte r o n SD A/SCL is 1 ) o r GPO 0 = 1 .
0 : En a b le '5 0 n s ' Glitc h - filte r in g o n SD A/SCL [ 4 ] A L ER T _EN _o r _G P O 0 ( R /W )
lin e s . En a b le ALERT o r GPO 0
1 : By p a s s th e Glitc h - Filte r . 1 : ALERT/BU SY/GPO 0 p in is u s e d fo r ALERT/BU SY
[ 1 0 ] C M D ( R /W ) s ta tu s .
Co m m a n d M o d e 0 : ALERT/BU SY/GPO 0 p in w ill b e u s e d a s
0 : Sa m p le m o d e ( if AU TO = 0 ) o r Au to c y c le a GPO .
m o d e ( if AU TO = 1) [ 5 ] B U S Y ( R /W )
1 : Co m m a n d m o d e ( if AU TO = 0 ) o r Sa m p le ALERT/BU SY/GPO 0 p in in d ic a te s if th e
m o d e ( if AU TO = 1) p a r t is b u s y c o n v e r tin g
[ 9 ] S R S T ( R /W ) 0 : ALERT/BU SY/GPO 0 p in is n o t u s e d fo r
So ftw a r e Re s e t b it BU SY s ta tu s .
0 : So ft- Re s e t n o t a c tiv e . 1 : ALERT/BU SY/GPO 0 p in is u s e d fo r BU SY
1 : Ac t iv a t e So ft- Re s e t. s ta tu s p r o v id e d ALERT_EN is 1 . Els e ,
th is w ill a lw a y s b e r e a d - b a c k a s 0 .
[ 7 : 6 ] C y c le _t im e r ( R /W )
Tim e r v a lu e fo r Au to c y c le m o d e
0 0 : 1 0 0 u S.
0 1 : 2 0 0 u S.
1 0 : 4 0 0 u S.
1 1 : 8 0 0 u S.
[ 8 ] A U T O ( R /W )
Au to c y c le M o d e
0 : Sa m p le m o d e ( if CM D = 0 ) o r Co m m a n d
m o d e ( if CM D = 1 )
1 : Au to - c y c le m o d e ( if CM D = 0 ) o r Sa m p le
m o d e ( if CM D = 1 )

Table 14. Configuration Bit Map

MSB LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
ALERT_ GPO2 RSV RSV FLTR CMD SRST AUTO CYCLE_ BUSY ALERT_ ALERT_ GPO1 P_DOWN
DRIVE_ TIMER EN_OR_ POL_OR_
TYPE GPO0 GPO0

Table 15. Bit Descriptions for the Configuration Register1

Bit(s) Name Description Reset Access
15 ALERT_DRIVE_TYPE Drive the type of the ALERT/BUSY/GPO0 pin. 0x0 RW
0: the ALERT/BUSY/GPO0 pin is open-drain drive type.
1: the ALERT/BUSY/GPO0 pin is CMOS drive type.
14 GPO2 Value at GPO2. 0x0 RW
0: drive 0 on GPO2 pin.
1: drive 1 on GPO2 pin.
13 RSV Reserved. 0x00 R
12 RSV Reserved. 0x00 R
Rev. A | Page 22 of 34
Data Sheet AD7091R-5
Bit(s) Name Description Reset Access
11 FLTR Enable the glitch filter on SDA/SCL. 0x0 RW
0: enable 50 ns glitch filtering on the SDA/SCL lines.
1: bypass the glitch filter.
10 CMD Command mode. 0x0 RW
0: sample mode (if AUTO = 0) or autocycle mode (if AUTO = 1).
1: command mode (if AUTO = 0) or sample mode (if AUTO = 1).
9 SRST Software reset bit. Setting this bit resets the internal digital control logic, the conversion 0x0 RWAC
result and alert indication registers, but not the other memory-mapped registers.
This bit is automatically cleared in the next clock cycle.
0: soft reset not active.
1: activate soft reset.
8 AUTO Autocycle mode. 0x0 RW
0: sample mode (if CMD = 0) or command mode (if CMD = 1).
1: autocycle mode (if CMD = 0) or sample mode (if CMD = 1).
[7:6] CYCLE_TIMER Timer value for autocycle mode. 0x3 RW
00: 100 μs.
01: 200 μs.
10: 400 μs.
11: 800 μs.
5 BUSY ALERT/BUSY/GPO0 pin indicates if the device is busy converting. 0x0 RW
0: the ALERT/BUSY/GPO0 pin is not used for the busy status.
1: the ALERT/BUSY/GPO0 pin is used for the busy status provided
ALERT_EN_OR_GPO0 is 1. Otherwise, this bit is always read back as 0.
4 ALERT_EN_OR_GPO0 Enable the ALERT/BUSY/GPO0 pin or GPO0. 0x0 RW
1: the ALERT/BUSY/GPO0 pin is used for the ALERT/BUSY status.
0: the ALERT/BUSY/GPO0 pin is used as a GPO.
3 ALERT_POL_OR_GPO0 Polarity of the ALERT/BUSY/GPO0 pin (if ALERT_EN_OR_GPO0 is 1) or value at GPO0. 0x0 RW
0: active low ALERT/BUSY/GPO0 polarity (if ALERT_EN_OR_GPO0 is 1) or GPO0 = 0.
1: active high ALERT/BUSY/GPO0 polarity (if ALERT_EN_OR_GPO0 is 1) or GPO0 = 1.
2 GPO1 Value at GPO1. 0x0 RW
0: drive 0 on the CONVST/GPO1 pin.
1: drive 1 on the CONVST/GPO1 pin.
[1:0] P_DOWN Power-down modes. 0x0 R/W
Setting Mode Sleep Mode/Bias Generator Internal Reference
00 Mode 0 Off Off
01 Mode 1 Off On
10 Mode 2 On Off
11 Mode 3 On On
1
The AD7091R-5 supports the I2C standard glitch filter, but does not support clock stretching or general call addressing.

Rev. A | Page 23 of 34
AD7091R-5 Data Sheet
ALERT INDICATION REGISTER
The 8-bit alert indication register is a read only register that provides information on an alert event. If a conversion result activates the
ALERT/BUSY/GPO0 pin, as described in the Channel x Low Limit Register section and the Channel x High Limit Register section, read
the alert register to determine the source of the alert. The register contains two status bits per channel, one corresponding to the high
limit, and the other to the low limit. The bit with a status equal to 1 shows where the violation occurred, that is, on which channel, and
whether the violation occurred on the upper or lower limit. If a second alert event occurs on another channel between receiving the first
alert and interrogating the alert register, the corresponding bit for that alert event is also set.
The contents of the alert indication register are reset by reading it. When the AD7091R-5 uses the I2C interface to read the alert indication
register, the register is reset at the fourth SCL clock of the byte. By this time, the data from the register has moved to the I2C shift register.
The alert bits for any unimplemented channels always return zeros.
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0

[ 7 ] Lo _3 ( R) [ 0 ] H i_0 ( R)
Lo w ale rt Channe l 3 Hig h ale rt Channe l 0
0 : No ale rt o n Channe l 3 . 0 : No ale rt o n Channe l 0 .
1: Lo w ale rt o ccurre d o n Channe l 3 . 1: Hig h ale rt o ccurre d o n Channe l 0 .
[ 6 ] H i_3 ( R) [ 1 ] Lo _0 ( R)
Hig h ale rt Channe l 3 Lo w ale rt Channe l 0
0 : No ale rt o n Channe l 3 . 0 : No ale rt o n Channe l 0 .
1: Hig h ale rt o ccurre d o n Channe l 3 . 1: Lo w ale rt o ccurre d o n Channe l 0 .
[ 5 ] Lo _2 ( R) [ 2 ] H i_1 ( R)
Lo w ale rt Channe l 2 Hig h ale rt Channe l 1
0 : No ale rt o n Channe l 2 . 0 : No ale rt o n Channe l 1.
1: Lo w ale rt o ccurre d o n Channe l 2 . 1: Hig h ale rt o ccurre d o n Channe l 1.
[ 4 ] H i_2 ( R) [ 3 ] Lo _1 ( R)
Hig h ale rt Channe l 2 Lo w ale rt Channe l 1
0 : No ale rt o n Channe l 2 . 0 : No ale rt o n Channe l 1.
1: Hig h ale rt o ccurre d o n Channe l 2 . 1: Lo w ale rt o ccurre d o n Channe l 1.

Table 16. Alert Indication Bit Map

MSB LSB
B7 B6 B5 B4 B3 B2 B1 B0
LO_3 HI_3 LO_2 HI_2 LO_1 HI_1 LO_0 HI_0

Table 17. Bit Descriptions for the Alert Indication Register

Bit(s) Bit Name Description Reset Access
7 LO_3 Channel 3 low alert status 0x0 R
0: no alert on Channel 3
1: low alert occurred on Channel 3
6 HI_3 Channel 3 high alert status 0x0 R
0: no alert on Channel 3
1: high alert occurred on Channel 3
5 LO_2 Channel 2 low alert status 0x0 R
0: no alert on Channel 2
1: low alert occurred on Channel 2
4 HI_2 Channel 2 high alert status 0x0 R
0: no alert on Channel 2
1: high alert occurred on Channel 2
3 LO_1 Channel 1 low alert status 0x0 R
0: no alert on Channel 1
1: low alert occurred on Channel 1

Rev. A | Page 24 of 34
Data Sheet AD7091R-5
Bit(s) Bit Name Description Reset Access
2 HI_1 Channel 1 high alert status 0x0 R
0: no alert on Channel 1
1: high alert occurred on Channel 1
1 LO_0 Channel 0 low alert status 0x0 R
0: no alert on Channel 0
1: low alert occurred on Channel 0
0 HI_0 Channel 0 high alert status 0x0 R
0: no alert on Channel 0
1: high alert occurred on Channel 0

Rev. A | Page 25 of 34
AD7091R-5 Data Sheet
CHANNEL x LOW LIMIT REGISTER Of the 16 bits, only the twelve least significant bits (LSBs) are
Each analog input channel of the AD7091R-5 has its own low used, Bit B11 to Bit B0. Bit B15 to Bit B12 are not used.
limit register. The low limit registers are 16-bit read/write CHANNEL x HYSTERESIS REGISTER
registers. See Table 9 for the register addresses. The low limit Each analog input channel of the AD7091R-5 has its own
registers store the lower limit of the conversion value that hysteresis register, which are 16-bit read/write registers. See
activates the ALERT output. Table 9 for the register addresses. The hysteresis register stores
Of the 16 bits, only the twelve least significant bits (LSBs) are the hysteresis value (N) when using the limit registers. The
used, Bit B11 to Bit B0. Bit B15 to Bit B12 are not used. hysteresis value determines the reset point for the ALERT/
BUSY/GPO0 pin if a violation of the limits has occurred.
CHANNEL x HIGH LIMIT REGISTER
Each analog input channel of the AD7091R-5 has its own high Of the 16 bits, only the twelve least significant bits (LSBs) are
limit register. The high limit registers are 16-bit read/write used, Bit B11 to Bit B0. Bit B15 to Bit B12 are not used.
registers. See Table 9 for the register addresses. The high limit
registers store the upper limit of the conversion value that
activates the ALERT output.

Table 18. Channel x Low Limit Bit Map

MSB LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
RSV CHx LOW LIMIT

Table 19. Bit Descriptions for Channel x Low Limit Register

Bits Bit Name Description Reset Access
[15:12] RSV Reserved 0x00 R
[11:0] CHx LOW LIMIT Low limit value for Channel x 0x000 R/W

Table 20. Channel x High Limit Bit Map

MSB LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
RSV CHx HIGH LIMIT

Table 21. Bit Descriptions for Channel x High Limit Register

Bits Bit Name Description Reset Access
[15:12] RSV 0x00 R
[11:0] CHx HIGH LIMIT High limit value for Channel x 0xFFF R/W

Table 22. Channel x Hysteresis Bit Map

MSB LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
RSV CHx HYSTERISIS

Table 23. Bit Descriptions for the Channel x Hysteresis Register

Bits Bit Name Description Reset Access
[15:12] RSV 0x00 R
[11:0] CHx HYSTERISIS Hysteresis value for Channel x 0xFFF R/W

Rev. A | Page 26 of 34
Data Sheet AD7091R-5

I2C INTERFACE
Control of the AD7091R-5 is carried out via the I2C-compatible as a high to low transition on the serial data line (SDA) while
serial bus. The AD7091R-5 is connected to this bus as a slave the serial clock line (SCL) remains high. This indicates that a
device under the control of a master device such as the processor. data stream follows. The master device must generate the clock.
SERIAL BUS ADDRESS BYTE Data is sent over the serial bus in groups of nine bits—eight bits
The first byte that the user writes to the device is the slave of data from the transmitter are followed by an acknowledge bit
address byte. Similar to all I2C-compatible devices, the (ACK) from the receiver. Data transitions on the SDA line must
AD7091R-5 has a 7-bit serial address. The three MSBs of this occur during the low period of the clock signal and remain
address are set to 010. The four LSBs are user programmable by stable during the high period. The receiver must pull the SDA
the three-state input pins, AS0 and AS1, as shown in Table 24. line low during the acknowledge bit to signal that the preceding
byte has been received correctly. If this is not the case, cancel
In Table 24, high means tie the pin to VDRIVE, low means tie the the transaction.
pin to GND, and NC refers to a pin left floating. Note that in
NC cases, the stray capacitance on the pin must be less than The first byte that the master sends must consist of a 7-bit slave
30 pF to allow correct detection of the floating state; therefore, address, followed by a data direction bit. Each device on the
any printed circuit board trace must be kept as short as possible. bus has a unique slave address; therefore, the first byte sets up
communication with a single slave device for the duration of the
Table 24. Slave Address Control Using Three-State Input Pins transaction.
Slave Address (A6 to A0) The transaction can be used either to write to a slave device
AS1 AS0 Binary Hex (data direction bit = 0) or to read data from it (data direction
High High 010 0000 0x20 bit = 1). In the case of a read transaction, it is often necessary
High NC 010 0010 0x22 first to write to the slave device (in a separate write transaction)
High Low 010 0011 0x23 to tell it from which register to read. Reading and writing
NC H 010 1000 0x28 cannot be combined in one transaction.
NC NC 010 1010 0x2A
When the transaction is complete, the master can maintain
NC Low 010 1011 0x2B
control of the bus, initiating a new transaction by generating
Low High 010 1100 0x2C
another start bit (high to low transition on SDA while SCL is
Low NC 010 1110 0x2E
high). This is known as a repeated start (SR). Alternatively, the
Low Low 010 1111 0x2F
bus can be relinquished by releasing the SCL line followed by
the SDA line. This low to high transition on SDA while SCL is
GENERAL I2C TIMING high is known as a stop bit (P), and it leaves the I2C bus in its
Figure 39 shows the timing diagram for general read and write idle state (no current is consumed by the bus).
operations using an I2C compliant interface.
The example in Figure 39 shows a simple write transaction
When no device is driving the bus, both SCL and SDA are high. with an AD7091R-5 as the slave device. In this example, the
This is known as the idle state. When the bus is idle, the master AD7091R-5 register pointer is being set up for a future read
initiates a data transfer by establishing a start condition, defined transaction.

SCL

SDA A6 A5 A4 A3 A2 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0

START COND SLAVE ADDRESS BYTE ACK. BY ACK. BY STOP BY

BY MASTER AD7091R-5 REGISTER ADDRESS AD7091R-5 MASTER
12093-040

USER PROGRAMMABLE
4 LSBs

Figure 39. General I2C Timing

Rev. A | Page 27 of 34
AD7091R-5 Data Sheet

WRITING TO THE AD7091R-5

WRITING TWO BYTES OF DATA TO A 16-BIT WRITING TO MULTIPLE REGISTERS
REGISTER Writing to multiple address registers consists of the following
With the exception of the channel register, all registers on the steps (see Figure 41):
AD7091R-5 are 16-bit registers; therefore, two bytes of data are 1. The master device asserts a start condition on SDA.
required to write a value to any one of these registers. Writing 2. The master sends the 7-bit slave address followed by
two bytes of data to a register consists of the following sequence the write bit (low).
(see Figure 40): 3. The addressed slave device (AD7091R-5) asserts an
1. The master device asserts a start condition on SDA. acknowledge on SDA.
2. The master sends the 7-bit slave address followed by the 4. The master sends a register address, for example, the
write bit (low). configuration register address.
3. The addressed slave device asserts an acknowledge on SDA. 5. The slave asserts an acknowledge on SDA.
4. The master sends a register address. The slave asserts an 6. The master sends the first data byte.
acknowledge on SDA. 7. The slave asserts an acknowledge on SDA.
5. The master sends the first data byte (most significant). 8. The master sends the second data byte.
6. The slave asserts an acknowledge on SDA. 9. The slave asserts an acknowledge on SDA.
7. The master sends the second data byte (least significant). 10. The master sends a second register address, for example,
8. The slave asserts an acknowledge on SDA. the Channel 0 high limit register.
9. The master asserts a stop condition on SDA to end the 11. The slave asserts an acknowledge on SDA.
transaction. 12. The master sends the first data byte.
13. The slave asserts an acknowledge on SDA.
14. The master sends the second data byte.
15. The slave asserts an acknowledge on SDA.
16. The master asserts a stop condition on SDA to end the
transaction.

S SLAVE ADDRESS 0 SA REG POINTER SA DATA[15:8] SA DATA[7:0] SA P

FROM MASTER TO SLAVE S = START CONDITION

SR = REPEATED START
P = STOP CONDITION

12093-059
FROM SLAVE TO MASTER
SA = SLAVE ACKNOWLEDGE
A = NOT ACKNOWLEDGE

Figure 40. Writing Two Bytes of Data to a 16-Bit Register

S SLAVE ADDRESS 0 SA POINT TO CONFIG REG (0x02) SA DATA[15:8] SA DATA[7:0] SA ...

... POINT TO CH0 HIGH LIMIT (0x05) SA DATA[15:8] SA DATA[7:0] SA P

FROM MASTER TO SLAVE S = START CONDITION

SR = REPEATED START
P = STOP CONDITION
12093-060

FROM SLAVE TO MASTER

SA = SLAVE ACKNOWLEDGE
A = NOT ACKNOWLEDGE

Figure 41. Writing to Multiple Registers

Rev. A | Page 28 of 34
Data Sheet AD7091R-5

READING DATA FROM THE AD7091R-5

READING TWO BYTES OF DATA FROM A 16-BIT Reading two bytes of data from a 16-bit register consists of the
REGISTER following sequence (see Figure 42):
Reading the contents from any of the 16-bit registers is a 2-byte 1. The master device asserts a start condition on SDA.
read operation. In this protocol, the first part of the transaction 2. The master sends the 7-bit slave address followed by the
writes to the register pointer. When the register address has read bit (high).
been set up, any number of reads can be performed from that 3. The addressed slave device asserts an acknowledge on SDA.
particular register without writing to the address pointer register 4. The master receives the data byte.
again. When the required number of reads is complete, the 5. The master asserts an acknowledge on SDA.
master must not acknowledge the final byte. This tells the slave 6. The master receives the second data byte.
to stop transmitting, allowing a stop condition to be asserted by 7. The master asserts an acknowledge on SDA.
the master. Further reads from this register can be performed in 8. The master receives the data byte.
a future transaction without rewriting to the register pointer. 9. The master asserts an acknowledge on SDA.
10. The master receives the second data byte.
If a read from a different address is required, the relevant
11. The master asserts an acknowledge on SDA.
register address must be written to the address pointer register
12. The master receives the data byte.
and, again, any number of reads from this register can then be
13. The master asserts an acknowledge on SDA.
performed. In the following example, the master device reads
14. The master receives the second data byte.
three lots of 2-byte data from a slave device, but as many lots
15. The master asserts a not acknowledge on SDA to notify the
consisting of two bytes can be read as required. This protocol
slave that the data transfer is complete.
assumes that the particular register address has been set up by
16. The master asserts a stop condition on SDA to end the
a single-byte write operation to the address pointer register.
transaction.

S SLAVE ADDRESS 1 A DATA[15:8] A DATA[7:0] A DATA[15:8] A DATA[7:0] A ...

... DATA[15:8] A DATA[7:0] A P

FROM MASTER TO SLAVE S = START CONDITION

SR = REPEATED START
P = STOP CONDITION

12093-061
FROM SLAVE TO MASTER
A = ACKNOWLEDGE
A = NOT ACKNOWLEDGE

Figure 42. Reading Three Lots of Two Bytes of Data from the Conversion Result Register (Conversion Register Pointer Already Set)

Rev. A | Page 29 of 34
AD7091R-5 Data Sheet

MODES OF OPERATION
There are three methods of initiating a conversion on the COMMAND MODE
AD7091R-5 with the I2C interface: sample mode using In command mode, the AD7091R-5 converts on demand on
the CONVST/GPO1 pin, command mode, and autocycle mode. either a single channel or a sequence of channels. This mode of
In the CONVST/GPO1 pin mode, conversions are done on operation allows a conversion to be selected automatically any
demand. Whenever the CONVST/GPO1 pin is toggled, an ADC time a write operation occurs to the command register. In
conversion happens. In command mode, the read of the command mode, the AD7091R-5 converts the next programmed
conversion result register starts the conversion. In autocycle channel when the conversion result register is read. To enter this
mode, conversions occur on the selected channels in the mode, the required combination of channels is written into the
background periodically. This mode monitors whether signals channel register. Select command mode operation by writing
cross certain threshold levels, the absolute value being relatively CMD = 1 and auto = 0 in the configuration register. Following
unimportant. the write operation, the AD7091R-5 must be addressed again to
SAMPLE MODE indicate that a read operation is required from the conversion
result register.
At power-up, the device wakes up in sample mode and selects
Channel 0 for conversion. Sample mode can be selected subse- The conversion starts on the first positive edge of SCL after the
quently by writing a value of 0 to both the CMD and auto bits of ACK for the previous byte is sent to avoid starting a conversion
the configuration register or by writing a value of 1 to both the during the ACK cycle. This does not create an issue with the exact
CMD and auto bits. In sample mode, conversions are controlled time that the conversion data must be sent on the I2C bus because
by toggling the active low CONVST/GPO1 pin. the first three bits sent on the I2C bus correspond to the channel
for which the conversion data belongs. After the conversion is
To perform conversion on a channel other than Channel 0 or on completed, the ADC powers down. The next conversion in the
a sequence of channels, before initiating any conversion, write sequence starts after a subsequent read from the conversion
to the channel register to select the channels for conversion. On result register is initiated. The device cycles through the selected
each CONVST pulse, the next channel in the selected sequence channels from the lowest selected channel number in the sequence
is converted starting from the lowest numbered channel to the next until all channels in the sequence are converted.
selected (0, 1 … 7). After all channels in the sequence are converted, the sequence
A high to low transition on the CONVST/GPO1 pin puts the rolls back to the lowest numbered channel enabled so that the
track-and-hold circuit into hold mode and samples the analog sequence can be repeated indefinitely.
input. The conversion is initiated and requires approximately To stop converting in the command mode, the master does not
550 ns to complete. When the conversion process is finished, acknowledge the final byte of data. This NACK stops the
the track-and-hold circuit goes back into track. AD7091R-5 transmission, allowing the master to assert a stop
To read back data stored in the conversion result register, first condition on the bus. On the receipt of an I2C NACK condition,
wait until the conversion is finished. If the address pointer is the AD7091R-5 stops converting, but the content of the
pointing to the conversion result register, the conversion data configuration register is preserved. After the device is
can be read using the protocol described in Figure 42. readdressed and a read initiated from the conversion result
Otherwise, the address pointer must be set to point at the register, the AD7091R-5 begins converting on the previously
conversion result register before conversion data can be read. selected sequence of channels.
When the conversion result read is completed, the user may The conversion sequence starts at the first selected channel in
pull the CONVST pin low again to start another conversion. the sequence. That is, if Channel 1, Channel 2, and Channel 3
Do not toggle the CONVST pin when activity is occurring on are selected and a stop condition occurs after the result for
the I2C bus. Channel 1 is read, on the resumption of conversions, Channel 2
is converted and the conversion sequence continues. This
happens provided the channel register is not written in between
conversions. However, if the channel register is written, this
results in the conversion starting from Channel 1.

Rev. A | Page 30 of 34
Data Sheet AD7091R-5
The example in Figure 43 shows command mode converting on 17. The slave (AD7091R-5) asserts an acknowledge on SDA.
a sequence of channels including Channel 0, Channel 1, and 18. The master receives a data byte, which contains the
Channel 2. channel address bits, the alert bit, and the four MSBs of the
1. The master device asserts a start condition on SDA. converted result for Channel 0.
2. The master sends the 7-bit slave address followed by the 19. The master then asserts an acknowledge on SDA.
write bit (low). 20. The master receives the second data byte, which contains
3. The addressed slave device (AD7091R-5) asserts an the eight LSBs of the converted result for Channel 0. The
acknowledge on SDA. master then asserts on acknowledge on SDA.
4. The master sends the configuration register address (0x02). 21. Step 18 to Step 20 repeat for Channel 1 and Channel 2.
5. The slave asserts an acknowledge on SDA. 22. After the master has received the results from all the
6. The master sends the first data byte (0x06) to the selected channels, the slave again converts and outputs
configuration register, which selects the command mode. the result for the first channel in the selected sequence.
7. The slave asserts an acknowledge on SDA. Step 18 to Step 21 are repeated.
8. The master sends the second data byte (0x00) to the 23. The master asserts a not acknowledge on SDA and a stop
configuration register. condition on SDA to end the conversion and exit
9. The slave asserts an acknowledge on SDA. command mode.
10. The master sends the channel register address (0x01). To change the conversion sequence, rewrite a new sequence to
11. The slave asserts an acknowledge on SDA. the command mode. If a new write to the channel register is
12. The master sends the data byte (0x07) to the channel register, performed while an existing conversion sequence is underway,
which selects Channel 0, Channel 1, and Channel 2. the existing conversion sequence is terminated and the next
13. The slave asserts an acknowledge on SDA. conversion performed is the first selected channel from the new
14. The master sends the conversion result register address (0x00). sequence. The maximum throughput that can be achieved using
15. The slave asserts an acknowledge on SDA. this mode with a 400 kHz I2C clock is (400 kHz/18) = 22.22 kSPS.
16. The master sends a repeated start and the 7-bit slave
address followed by the read bit (high).

S SLAVE ADDRESS 0 SA POINT TO CONFIG REG (0x02) SA COMMAND = 0x06 SA COMMAND = 0x00 SA

... POINT TO CHANNEL REG (0x01) SA COMMAND = 0x07 SA ...

*
... POINT TO RESULT REG (0x00) SA SR SLAVE ADDRESS 1 SA CH AD (0000) CH0[11:8] A ...
*
... CH0[7:0] A CH AD (0001) CH1[11:8] A CH1[7:0] A ...
... * CH AD (0010) CH2[11:8] A CH2[7:0] A
*
CH ID (0000) CH0[11:8] A ...
... CH0[7:0] A ........ CH2[7:0] A P
FROM MASTER TO SLAVE S = START CONDITION
SR = REPEATED START
FROM SLAVE TO MASTER P = STOP CONDITION
12093-062

* = POSITION OF SAMPLING START SA = SLAVE ACKNOWLEDGE

A = NOT ACKNOWLEDGE

Figure 43. Command Mode Operation

Rev. A | Page 31 of 34
AD7091R-5 Data Sheet
AUTOCYCLE MODE Table 25. Autocycle Interval Time
The AD7091R-5 can be configured to convert continuously on a Command Interval Time Approximate Interval
programmable sequence of channels, making it the ideal mode of 00 1 × BASE_TIME 100 μs (10 kSPS)
operation for system monitoring. These conversions occur 01 2 × BASE_TIME 200 μs (5 kSPS)
automatically at intervals chosen by the CYCLE_TIMER bits in 10 4 × BASE_TIME 400 μs (2.5 kSPS)
the configuration register. Typically, this mode is used to 11 8 × BASE_TIME 800 μs (1.25 kSPS)
monitor a selection of channels automatically with the limit Do not write to the limit and hysteresis registers when the
registers programmed to signal an out of bounds condition via AD7091R-5 is in autocycle mode. If these registers are written
the alert function. Reads and writes can be performed at any by chance, the design stalls the internal cycle timer counters for
time (the conversion result register contains the most recent one SCL period when the registers are being updated. A write to
conversion result). the channel register and the configuration register in autocycle
To enter this mode, the required combination of channels that mode restarts the cycle timer counters.
must be monitored is written into the channel register. The Because the alert indication register is read to clear, read the
required interval between conversions is selected by writing register only when an alert is indicated. Otherwise, there is a
into the CYCLE_TIMER bits in the configuration register. risk of inadvertently clearing the alert register and the alert bit
Autocycle mode operation can then be selected by writing in the conversion result register.
CMD = 0 and auto = 1 in the configuration register. If more
POWER-DOWN MODE
than one channel bit is set in the channel register, the ADC
automatically cycles through the channel sequence, starting Power-down mode is intended for use in applications where slower
with the lowest channel and working its way up through the throughput rates and lower power consumption are required;
sequence. After the sequence is complete, the ADC starts either the ADC is powered down between each conversion, or a
converting on the lowest channel again, continuing to loop burst of conversions can be performed at a higher throughput rate,
through the sequence until this mode is exited. and the ADC is then powered down for a relatively long duration
between these bursts of several conversions. When the AD7091R-5
As soon as a conversion is complete, the conversion result is
is in power-down mode, all analog circuitry is powered down;
compared with the content of the limit registers. The alert register
however, the serial interface is active.
is updated automatically with the result of the comparison.
If a violation of the limit registers is found, the alert bit in the The serial interface of the AD7091R-5 is functional in power-
conversion result register is set and, if the ALERT/BUSY/GPO0 down; therefore, the user may read back the last conversion result
pin functionality is selected in the configuration register, the even after the device enters power-down mode.
ALERT/BUSY/GPO0 pin is asserted with the polarity To enter power-down, write to the power-down configuration
determined by ALERT_POL_OR_GPO0 bit in the bits in the configuration register, as seen in Table 15. To enter
configuration register. full power-down mode, set the sleep mode/bias generator bit to 1,
If an out-of-cycle conversion is required while autocycle mode and set the internal reference bit to 0, which ensures that all analog
is active, it is necessary to disable autocycle mode before circuitry and the internal reference powers down. When the
proceeding to the command or sample mode. When the internal reference is enabled, it consumes power any time Bit 0 of
conversion is complete, the user can reenable autocycle mode. the configuration register is set to 1.
In autocycle mode, the AD7091R-5 does not enter power-down To exit this mode of operation and power up the AD7091R-5,
on receipt of a stop condition; therefore, conversions and alert set the MSB of the P_DOWN word to 1. If a power-up of the
monitoring continues to function. internal reference is desired, the P_DOWN LSB must also be set
The CYCLE_TIMER value in the configuration register controls to 1. When using the internal reference, and the device is in full
the time of conversion in autocycle mode. Four separate time power-down mode, wait to perform conversions until the internal
intervals are available, and each is a multiple of the BASE_TIME. reference has had time to power up and settle. The reference buffer
The reset value used is 8 × BASE_TIME. The base time for the requires 50 ms to power up and charge the 2.2 µF decoupling
AD7091R-5 is approximately 100 μs. capacitor during the power-up time. After power-up is complete,
the ADC is fully powered up, and the input signal is properly
Writing to the channel register or the configuration register
acquired. To start the next conversion, operate the interface as
when in autocycle mode results in a reset of the cycle timer.
described in the Modes of Operation section.
This process ensures that the latest information is used for cycle
timer calculation.

Rev. A | Page 32 of 34
Data Sheet AD7091R-5
ALERT BUSY
The alert functionality is used as an out of bounds indicator. An When the ALERT/BUSY/GPO0 pin is configured as a BUSY
alert event is triggered when the value in the conversion result output, the pin indicates when a conversion is taking place. The
register exceeds the CHx high limit value in the Channel x high ALERT/BUSY/GPO0 pin is configured as BUSY by configuring
limit register or falls below the CHx low limit value in the the following bits in the configuration register:
Channel x low limit register for a selected channel.
• Set the ALERT_EN_OR_GPO0 bit, Bit 4, to 1.
Detailed alert information is accessible in the alert register. The • Set the busy bit, Bit 5, to 1.
register contains two status bits per channel, one corresponding • Set the ALERT_POL_OR_GPO0 bit, Bit 3, to 0 for the
to the high limit, and the other to the low limit. A logical OR of ALERT/BUSY/GPO0 pin to be active low, and set it to 1 for
alert signals for all channels creates a common alert value. This the ALERT/BUSY/GPO0 pin to be active high.
value can be accessed by the alert bit in the conversion result
register and configured to drive out on the ALERT/BUSY/GPO0 When using the ALERT/BUSY/GPO0 output pin, an external
pin. The ALERT/BUSY/GPO0 pin is configured as an ALERT pull-up resistor is required because the output is an open-drain
output by configuring the following bits in the configuration configuration. Connect the external pull-up resistor to VDRIVE. The
register: resistor value is application dependent; however, it must be large
enough to avoid excessive sink currents at the
• Set the ALERT_EN_OR_GPO0 bit (Bit 4) to 1. ALERT/BUSY/GPO0 output pin.
• Set the busy bit (Bit 5) to 0.
• Set the ALERT_POL_OR_GPO0 bit (Bit 3) to 0 for the
CHANNEL SEQUENCER
ALERT/BUSY/GPO0 pin to be active low and set it to 1 for The AD7091R-5 includes a channel sequencer useful for scanning
the ALERT/BUSY/GPO0 pin to be active high. channels in a repeated fashion. Channels included in the sequence
are configured in the channel register. If all the bits in the
The alert register, alert bit, and ALERT/BUSY/GPO0 pin are channel register are 0, Channel 0 is selected by default, and all
cleared by reading the alert register contents. Additionally, if the conversions occur on this channel. If the channel register is
conversion result goes beyond the hysteresis value for a selected nonzero, the conversion sequence starts from the lowest
channel, the alert bit corresponding to that channel is reset numbered channel enabled in the channel register. The sequence
automatically. Issuing a software reset also clears the alert status. cycles through all the enabled channels in ascending order.
The ALERT/BUSY/GPO0 pin has an open-drain configuration After all the channels in the sequence are converted, the
that allows the alert outputs of several AD7091R-5 devices to be sequence starts again.
wired together when the ALERT/BUSY/GPO0 pin is active low. There is a latency of one conversion before the channel conversion
The ALERT/BUSY/GPO0 pin configuration can be controlled sequence is updated. If the channel register is programmed with
by the ALERT_DRIVE_TYPE bit, Bit 15 of the configuration a new value, the conversion sequence is reset to the lowest
register. numbered channel in the new value.
The ALERT_POL_OR_GPO0 bit (Bit 3 of the configuration
register) sets the active polarity of the alert output. The power-
up default is active low.
When using the ALERT/BUSY/GPO0 output pin, an external
pull-up resistor is required because the output is an open-drain
configuration. Connect the external pull-up resistor to VDRIVE.
The resistor value is application dependent; however, it must be
large enough to avoid excessive sink currents at the
ALERT/BUSY/GPO0 output pin.

Rev. A | Page 33 of 34
AD7091R-5 Data Sheet

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)

4.10 0.30
4.00 SQ 0.25
PIN 1 3.90 0.20
INDICATOR PIN 1
INDIC ATOR AREA OPTIONS
16 20 (SEE DETAIL A)
0.50 1
BSC 15

2.65
EXPOSED
PAD 2.50 SQ
2.35
5
11

0.50 10 6
0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.30
0.80 FOR PROPER CONNECTION OF
0.75 SIDE VIEW THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70 FUNCTION DESCRIPTIONS
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING 0.08
PLANE 0.20 REF

10-12-2017-C
PKG-003578

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11.

Figure 44. 20-Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-10)
Dimensions shown in millimeters

6.60
6.50
6.40

20 11

4.50
4.40
4.30
6.40 BSC
1 10

PIN 1
0.65
BSC
0.15 1.20 MAX 0.20
0.05 0.09 0.75
8° 0.60
0.30
0° 0.45
COPLANARITY 0.19 SEATING
0.10 PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 45. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Channels Temperature Range Package Description Package Option
AD7091R-5BCPZ 4 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-10
AD7091R-5BCPZ-RL7 4 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-10
AD7091R-5BRUZ 4 −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD7091R-5BRUZ-RL7 4 −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
EVAL-AD7091R-5SDZ Evaluation Board
EVAL-SDP-CB1Z Evaluation Controller Board
1
Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D12093-0-2/18(A)

Rev. A | Page 34 of 34