Data Sheet

AD5259
Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer

FEATURES FUNCTIONAL BLOCK DIAGRAMS

► Nonvolatile memory maintains wiper settings
► 256-position
► Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package
► Compact MSOP-10 (3 mm × 4.9 mm × 1.1 mm) package
► I2C-compatible interface
► VLOGIC pin provides increased interface flexibility
► End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
► Resistance tolerance stored in EEPROM (0.1% accuracy)
► Power-on EEPROM refresh time < 1ms
Figure 1. Block Diagram
► Software write protect command
► Address Decode Pin AD0 and Pin AD1 allow 4 packages per bus
► 100-year typical data retention at 55°C
► Wide operating temperature −40°C to +125°C
► 3 V to 5 V single supply
APPLICATIONS
► LCD panel VCOM adjustment
► LCD panel brightness and contrast control
► Mechanical potentiometer replacement in new designs
► Programmable power supplies Figure 2. Block Diagram Showing Level Shifters
► RF amplifier biasing
CONNECTION DIAGRAM
► Automotive electronics adjustment
► Gain control and offset adjustment
► Fiber to the home systems
► Electronics level settings

Figure 3. Pinout
GENERAL DESCRIPTION
The AD5259 provides a compact, nonvolatile LFCSP-10 (3 mm × A separate VLOGIC pin delivers increased interface flexibility. For
3 mm) or MSOP-10 (3 mm × 4.9 mm) packaged solution for users who need multiple parts on one bus, Address Bit AD0 and
256-position adjustment applications. These devices perform the Address Bit AD1 allow up to four devices on the same bus.
same electronic adjustment function as mechanical potentiometers
or variable resistors, but with enhanced resolution and solid-state
reliability. The terms digital potentiometer, VR (variable resistor),
and RDAC are used interchangeably.
The wiper settings are controllable through an I2C‑compatible dig-
ital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.

Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
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Data Sheet AD5259
TABLE OF CONTENTS

Features................................................................ 1 Reading............................................................ 15
Applications........................................................... 1 I2C-Compatible Format........................................16
Functional Block Diagrams....................................1 Generic Interface..............................................16
Connection Diagram..............................................1 Write Modes..................................................... 16
General Description...............................................1 Read Modes..................................................... 17
Specifications........................................................ 3 Store/Restore Modes....................................... 17
Electrical Characteristics.................................... 3 Tolerance Readback Modes.............................17
Timing Characteristics........................................4 ESD Protection of Digital Pins and Resistor
Absolute Maximum Ratings...................................6 Terminals........................................................ 18
ESD Caution.......................................................6 Power-Up Sequence........................................ 18
Pin Configuration and Function Descriptions........ 7 Layout and Power Supply Bypassing ..............19
Typical Performance Characteristics..................... 8 Multiple Devices on One Bus........................... 19
Test Circuits......................................................... 13 Evaluation Board.............................................. 19
Theory of Operation.............................................14 Display Applications............................................ 20
Programming the Variable Resistor..................14 Circuitry............................................................ 20
Programming the Potentiometer Divider.......... 14 Outline Dimensions............................................. 21
2
I C-Compatible Interface..................................... 15 Ordering Guide.................................................21
Writing.............................................................. 15 RAB (Ω) Options................................................22
Storing/Restoring..............................................15 Evaluation Boards............................................ 22

REVISION HISTORY

5/2022—Rev. C to Rev. D
Updated Outline Dimensions......................................................................................................................... 21

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Data Sheet AD5259
SPECIFICATIONS

ELECTRICAL CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.

Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS: RHEOSTAT MODE
Resistor Differential Nonlinearity R-DNL RWB, VA = no connect LSB
5 kΩ –1 ±0.2 +1
10 kΩ −1 ±0.1 +1
50 kΩ/100 kΩ −0.5 ±0.1 +0.5
Resistor Integral Nonlinearity R-INL RWB, VA = no connect LSB
5 kΩ –4 ±0.3 +4
10 kΩ −2 ±0.2 +2
50 kΩ/100 kΩ −1 ±0.4 +1
Nominal Resistor Tolerance ΔRAB TA = 25°C, VDD = 5.5 V –30 +30 %
Resistance Temperature Coefficient (ΔRAB × 106)/(RAB Code = 0x00/0x80 500/15 ppm/°C
× ΔT)
Total Wiper Resistance RWB Code = 0x00 75 350 Ω
DC CHARACTERISTICS: POTENTIOMETER
DIVIDER MODE
Differential Nonlinearity DNL LSB
5 kΩ –1 ±0.2 +1
10 kΩ −0.5 ±0.1 +0.5
50 kΩ/100 kΩ −0.5 ±0.2 +0.5
Integral Nonlinearity INL LSB
5 kΩ –1 ±0.2 +1
10 kΩ −0.5 ±0.1 +0.5
50 kΩ/100 kΩ −0.5 ±0.1 +0.5
Full-Scale Error VWFSE Code = 0xFF LSB
5 kΩ −7 −3 0
10 kΩ −4 −1.5 0
50 kΩ/100 kΩ −1 −0.4 0
Zero-Scale Error VWZSE Code = 0x00
5 kΩ −40°C < TA < +85°C 0 2.5 4 LSB
+85°C < TA < +125°C 6 LSB
10 kΩ −40°C < TA < +85°C 0 1 3 LSB
+85°C < TA < +125°C 4 LSB
50 kΩ/100 kΩ 0 0.2 0.5 LSB
Voltage Divider Temperature Coefficient (∆VW × 106)/(VW × Code = 0x00/0x80 60/5 ppm/°C
∆T)
RESISTOR TERMINALS
Voltage Range VA, B, W GND VDD V
Capacitance A, B CA, B f = 1 MHz, measured to GND, code = 45 pF
0x80
Capacitance W CW f = 1 MHz, measured to GND, code = 60 pF
0x80
Common-Mode Leakage ICM VA = VB = VDD/2 10 nA

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Data Sheet AD5259
SPECIFICATIONS

Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 0.7 × VL VL + 0.5 V
Input Logic Low VIL −0.5 0.3 × VL V
Leakage Current IIL µA
SDA, AD0, AD1 VIN = 0 V or 5 V 0.01 ±1
SCL – Logic High VIN = 0 V −2.5 −1.3 +1
SCL – Logic Low VIN = 5 V 0.01 ±1
Input Capacitance CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD 2.7 5.5 V
Positive Supply Current IDD 0.1 2 µA
Logic Supply VLOGIC 2.7 5.5 V
Logic Supply Current ILOGIC VIH = 5 V or VIL = 0 V
−40°C < TA < +85°C 3 6 µA
+85°C < TA < +125°C 9 µA
Programming Mode Current (EEPROM) ILOGIC(PROG) VIH = 5 V or VIL = 0 V 35 mA
Power Dissipation PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 15 40 µW
Power Supply Rejection Ratio PSRR VDD = +5 V ± 10%, code = 0x80 ±0.005 ±0.06 %/%
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB BW Code = 0x80
RAB = 5 kΩ 2000 kHz
RAB = 10 kΩ 800 kHz
RAB = 50 kΩ 160 kHz
RAB = 100 kΩ 80 kHz
Total Harmonic Distortion THDW RAB = 10 kΩ, VA = 1 V rms, VB = 0, 0.01 %
f = 1 kHz
VW Settling Time tS RAB = 10 kΩ, VAB = 5 V, ±1 LSB error 500 ns
band
Resistor Noise Voltage Density eN_WB RWB = 5 kΩ, f = 1 kHz 9 nV/√Hz
1 Typical values represent average readings at 25°C and VDD = 5 V.

TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C, unless otherwise noted.

Table 2.
Parameter Symbol Conditions Min Typ Max Unit
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency fSCL 0 400 kHz
tBUF Bus Free Time Between Stop and Start t1 1.3 µs
tHD;STA Hold Time (Repeated Start) t2 After this period, the first clock pulse is generated. 0.6 µs
tLOW Low Period of SCL Clock t3 1.3 µs
tHIGH High Period of SCL Clock t4 0.6 µs
t5 0.6 µs
tSU;STA Setup Time for Repeated

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Data Sheet AD5259
SPECIFICATIONS

Table 2.
Parameter Symbol Conditions Min Typ Max Unit
Start Condition
tHD;DAT Data Hold Time t6 0 0.9 µs
tSU;DAT Data Setup Time t7 100 ns
tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
tSU;STO Setup Time for Stop Condition t10 0.6 µs
EEPROM Data Storing Time tEEMEM_STORE 26 ms
EEPROM Data Restoring Time at Power-On2 tEEMEM_RESTORE1 VDD rise time dependent. Measure without decoupling 300 µs
capacitors at VDD and GND.
EEPROM Data Restoring Time upon Restore tEEMEM_RESTORE2 VDD = 5 V. 300 µs
Command2
EEPROM Data Rewritable Time3 tEEMEM_REWRITE 540 µs
FLASH/EE MEMORY RELIABILITY
Endurance4 100 700 kCycles
Data Retention5 100 Years
1 Standard I2C mode operation guaranteed by design.
2 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3 Delay time after power-on PRESET prior to writing new EEPROM data.
4 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +125°C; typical endurance at +25°C is 700,000 cycles.
5 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with
junction temperature.

Figure 4. I2C Interface Timing Diagram

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Data Sheet AD5259
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.
Parameter Value
VDD, VLOGIC to GND −0.3 V to +7 V
VA, VB, VW to GND GND − 0.3 V, VDD + 0.3 V
IMAX
Pulsed1 ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2 θJA: MSOP-10 200°C/W
1 Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.

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Data Sheet AD5259
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin Mnemonic Description
1 W W Terminal, GND ≤ VW ≤ VDD.
2 ADO Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up.
3 AD1 Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up.
4 SDA Serial Data Input/Output.
5 SCL Serial Clock Input. Positive edge triggered.
6 VLOGIC Logic Power Supply.
7 GND Digital Ground.
8 VDD Positive Power Supply.
9 B B Terminal, GND ≤ VB ≤ VDD.
10 A A Terminal, GND ≤ VA ≤ VDD.
11 EPAD Exposed Pad. The exposed pad should be connected to GND or left floating.

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Data Sheet AD5259
TYPICAL PERFORMANCE CHARACTERISTICS

VDD = VLOGIC = 5.5 V, RAB = 10 kΩ, TA = +25°C; unless otherwise noted.

Figure 6. R-INL vs. Code vs. Supply Voltage Figure 9. DNL vs. Code vs. Temperature

Figure 7. R-DNL vs. Code vs. Supply Voltage Figure 10. INL vs. Supply Voltages

Figure 8. INL vs. Code vs. Temperature Figure 11. DNL vs. Code vs. Supply Voltage

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Data Sheet AD5259
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 12. R-INL vs. Code vs. Temperature Figure 15. Zero-Scale Error vs. Temperature

Figure 13. R-DNL vs. Code vs. Temperature Figure 16. Supply Current vs. Temperature

Figure 14. Full-Scale Error vs. Temperature Figure 17. Logic Supply Current vs. Temperature vs. VDD

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Data Sheet AD5259
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 18. Rheostat Mode Tempco (ΔRAB × 106)/(RAB × ΔT) vs. Code Figure 21. Total Resistance vs. Temperature

Figure 19. Potentiometer Mode Tempco (ΔVW × 106)/(VW × ΔT) vs. Code Figure 22. Gain vs. Frequency vs. Code, RAB = 5 kΩ

Figure 20. RWB vs. Temperature Figure 23. Gain vs. Frequency vs. Code, RAB = 10 kΩ

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Data Sheet AD5259
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 24. Gain vs. Frequency vs. Code, RAB = 50 kΩ Figure 27. Logic Supply Current vs. Input Voltage

Figure 25. Gain vs. Frequency vs. Code, RAB = 100 kΩ Figure 28. PSRR vs. Frequency

Figure 26. −3 dB Bandwidth @ Code = 0x80 Figure 29. Digital Feedthrough

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Data Sheet AD5259
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 30. Midscale Glitch, Code 0x7F to 0x80

Figure 31. Large Signal Settling Time

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Data Sheet AD5259
TEST CIRCUITS

Figure 32 through Figure 37 illustrate the test circuits that define the test conditions used in the product Specifications tables.

Figure 32. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 35. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

Figure 33. Test Circuit for Resistor Position Nonlinearity Error (Rheostat
Figure 36. Test Circuit for Gain vs. Frequency
Operation; R-INL, R-DNL)

Figure 34. Test Circuit for Wiper Resistance

Figure 37. Test Circuit for Common-Mode Leakage Current

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Data Sheet AD5259
THEORY OF OPERATION

The AD5259 is a 256-position digitally-controlled variable resistor decreases as the data loaded in the latch increases in value.
(VR) device. EEPROM is pre-loaded at midscale from the factory, The general equation for this operation is
and initial power-up is, accordingly, at midscale. 256 − D
RWA(D) = 256 × RAB + 2 × RW (2)
PROGRAMMING THE VARIABLE RESISTOR
Typical device-to-device matching is process lot dependent and
Rheostat Operation may vary by up to ±30%. For this reason, resistance tolerance is
stored in the EEPROM, enabling the user to know the actual RAB
The nominal resistance (RAB) of the RDAC between Terminal A and within 0.1%.
Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The
nominal resistance of the VR has 256 contact points accessed by PROGRAMMING THE POTENTIOMETER
the wiper terminal. The 8-bit data in the RDAC latch is decoded to DIVIDER
select one of 256 possible settings.
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
Wiper W to Terminal B and Wiper W to Terminal A proportional to
the input voltage at Terminal A to Terminal B. Unlike the polarity of
Figure 38. Rheostat Mode Configuration VDD to GND, which must be positive, voltage across Terminal A to
Terminal B, Wiper W to Terminal A, and Wiper W to Terminal B can
The general equation determining the digitally programmed output be at either polarity.
resistance between Wiper W and Terminal B is
D
RWB(D) = 256 × RAB + 2 × RW (1)

where:
D is the decimal equivalent of the binary code loaded in the 8‑bit
RDAC register. Figure 40. Potentiometer Mode Configuration
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the ON resistance of each If ignoring the effect of the wiper resistance for approximation,
internal switch. connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at Wiper W to Terminal B starting at 0 V
up to 1 LSB less than 5 V. The general equation defining the output
voltage at VW with respect to ground for any valid input voltage
applied to Terminal A and Terminal B is
D 256 − D
VW(D) = 256 VA + 256 VB (3)

A more accurate calculation, which includes the effect of wiper

resistance, VW, is
RWB(D) RWA(D)
VW(D) = RAB VA + RAB VB (4)

Operation of the digital potentiometer in the divider mode results

Figure 39. AD5259 Equivalent RDAC Circuit in a more accurate operation over temperature. Unlike the rheostat
mode, the output voltage is dependent mainly on the ratio of the
In the zero-scale condition, there is a relatively low value finite Internal Resistors RWA and RWB and not the absolute values.
wiper resistance. Care should be taken to limit the current flow
between Wiper W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation or
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A produces a digitally
controlled complementary resistance, RWA. The resistance value
setting for RWA starts at a maximum value of resistance and

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Data Sheet AD5259
I2C-COMPATIBLE INTERFACE

The master initiates data transfer by establishing a start condition, (see Table 13 to Table 14). In addition, users should issue an NOP
which is when a high-to-low transition on the SDA line occurs while command immediately after restoring the EEMEM setting to RDAC,
SCL is high (see Figure 4). The next byte is the slave address byte, thereby minimizing supply current dissipation.
which consists of the slave address (first 7 bits) followed by an R/W
bit (see Table 6). When the R/W bit is high, the master reads from READING
the slave device. When the R/W bit is low, the master writes to the Assuming the register of interest was not just written to, it is neces-
slave device. sary to write a dummy address and instruction byte. The instruction
The slave address of the part is determined by two configurable byte will vary depending on whether the data that is wanted is the
address pins, Pin AD0 and Pin AD1. The state of these two pins RDAC register, EEPROM register, or tolerance register (see Table
is registered upon power-up and decoded into a corresponding I2C 11 and Table 17).
7-bit address (see Table 5). The slave address corresponding to After the dummy address and instruction bytes are sent, a repeat
the transmitted address bits responds by pulling the SDA line low start is necessary. After the repeat start, another address byte
during the ninth clock pulse (this is termed the slave acknowledge is needed, except this time the R/W bit is logic high. Following
bit). At this stage, all other devices on the bus remain idle while this address byte is the readback byte containing the information
the selected device waits for data to be written to, or read from, its requested in the instruction byte. Read bits appear on the negative
serial register. edges of the clock.
WRITING The tolerance register can be read back individually (see Table 15)
In the write mode, the last bit (R/W) of the slave address byte is or consecutively (see Table 17). Refer to the Read Modes section
logic low. The second byte is the instruction byte. The first three for detailed information on the interpretation of the tolerance bytes.
bits of the instruction byte are the command bits (see Table 6). The After all data bits have been read or written, a stop condition
user must choose whether to write to the RDAC register, EEPROM is established by the master. A stop condition is defined as a
register, or activate the software write protect (see Table 7 to Table low-to-high transition on the SDA line while SCL is high. In write
10). The final five bits are all zeros (see Table 13 to Table 14). The mode, the master pulls the SDA line high during the tenth clock
slave again responds by pulling the SDA line low during the ninth pulse to establish a stop condition (see Figure 46). In read mode,
clock pulse. the master issues a no acknowledge for the ninth clock pulse (that
The final byte is the data byte MSB first. With the write protect is, the SDA line remains high). The master then brings the SDA
mode, data is not stored; rather, a logic high in the LSB enables line low before the tenth clock pulse, and then raises SDA high to
write protect. Likewise, a logic low disables write protect. The slave establish a stop condition (see Figure 47).
again responds by pulling the SDA line low during the ninth clock A repeated write function gives the user flexibility to update the
pulse. RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
STORING/RESTORING
its slave address and instruction bytes in the write mode, the RDAC
In this mode, only the address and instruction bytes are necessary. output is updated on each successive byte until a stop condition is
The last bit (R/W) of the address byte is logic low. The first three received. If different instructions are needed, the write/read mode
bits of the instruction byte are the command bits (see Table 6). The has to start again with a new slave address, instruction, and data
two choices are transfer data from RDAC to EEPROM (store), or byte. Similarly, a repeated read function of the RDAC is also
from EEPROM to RDAC (restore). The final five bits are all zeros allowed.

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Data Sheet AD5259
I2C-COMPATIBLE FORMAT

The following generic, write, read, and store/restore control regis- R = Read
ters for the AD5259 all refer to the device addresses listed in Table
5; the mode/condition reference key (S, P, SA, MA, NA, W, R, and X = Don’t Care
X) is listed below. AD1 and AD0 are two-state address pins.
S = Start Condition Table 5. Device Address Lookup

P = Stop Condition AD1 Address Pin AD0 Address Pin I2C Device Address
0 0 0011000
SA = Slave Acknowledge
1 0 0011010
MA = Master Acknowledge 0 1 1001100
NA = No Acknowledge 1 1 1001110

W = Write
GENERIC INTERFACE
Table 6. Generic Interface Format
7-Bit Device Address
S (See Table 5) R/W SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte Instruction Byte Data Byte

Table 7. RDAC-to-EEPROM Interface Command Descriptions

C2 C1 C0 Command Description
0 0 0 Operation Between Interface and RDAC.
0 0 1 Operation Between Interface and EEPROM.
0 1 0 Operation Between Interface and Write Protection Register. See Table 10.
1 0 0 NOP.
1 0 1 Restore EEPROM to RDAC.1
1 1 0 Store RDAC to EEPROM.
1 This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.

WRITE MODES
Table 8. Writing to RDAC Register
7-Bit Device Address
S (See Table 5) 0 SA 0 0 0 0 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte Instruction Byte Data Byte

Table 9. Writing to EEPROM Register

7-Bit Device Address
S (See Table 5) 0 SA 0 0 1 0 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte Instruction Byte Data Byte

Table 10. Activating/Deactivating Software Write Protect

7-Bit Device Address
S (See Table 5) 0 SA 0 1 0 0 0 0 0 0 SA 0 0 0 0 0 0 0 WP SA P
Slave Address Byte Instruction Byte Data Byte

In order to activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the command must
be sent again, except with the WP in logic zero state. WP is reset to the deactivated mode if power is cycled off and on.

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Data Sheet AD5259
I2C-COMPATIBLE FORMAT

READ MODES reads a register previously written to. For example, if the EEPROM
was just written to, the user can then skip the two dummy bytes
Read modes are referred to as traditional because the first two and proceed directly to the slave address byte, followed by the
bytes for all three cases are dummy bytes, which function to place EEPROM readback data.
the pointer towards the correct register; this is the reason for the
repeat start. Theoretically, this step can be avoided if the user
Table 11. Traditional Readback of RDAC Register Value
7-Bit Device Address 7-Bit Device Address
S (See Table 5) 0 SA 0 0 0 0 0 0 0 0 SA S1 (See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte Instruction Byte Slave Address Byte Read Back Data
1 Repeated start.

Table 12. Traditional Readback of Stored EEPROM Value

7-Bit Device Address 7-Bit Device Address
S (See Table 5) 0 SA 0 0 1 0 0 0 0 0 SA S1 (See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte Instruction Byte Slave Address Byte Read Back Data
1 Repeated start.

STORE/RESTORE MODES
Table 13. Storing RDAC Value to EEPROM
S 7-Bit Device Address (See Table 5) 0 SA 1 1 0 0 0 0 0 0 SA P
Slave Address Byte Instruction Byte

Table 14. Restoring EEPROM to RDAC1

S 7-Bit Device Address (See Table 5) 0 SA 1 0 1 0 0 0 0 0 SA P
Slave Address Byte Instruction Byte
1 User should issue an NOP command immediately after this command to conserve power.

TOLERANCE READBACK MODES

Table 15. Traditional Readback of Tolerance (Individually)
7-Bit Device Address 7-Bit Device Address
S (See Table 5) 0 SA 0 0 1 1 1 1 1 0 SA S1 (See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte Instruction Byte Slave Address Byte Sign + Integer Byte
1 Repeated start.

Table 16.
7-Bit Device Address 7-Bit Device Address
S (See Table 5) 0 SA 0 0 1 1 1 1 1 1 SA S1 (See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte Instruction Byte Slave Address Byte Decimal Byte
1 Repeated start.

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Data Sheet AD5259
I2C-COMPATIBLE FORMAT

Table 17. Traditional Readback of Tolerance (Consecutively)

7-Bit Device 7-Bit Device
Address (See S S Address (See S D D D D D D D D M D D D D D D D D N
S Table 5) 0 A 0 0 1 1 1 1 1 0 A S1 Table 5) 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A P
Slave Address Sign + Integer Byte Decimal Byte
Slave Address Byte Instruction Byte Byte
1 Repeated start.

Calculating RAB Tolerance Stored in Read-Only

Memory

Figure 41. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is Percent. Only Data Bytes are Shown.)

The AD5259 features a patented RAB tolerance storage in the ESD PROTECTION OF DIGITAL PINS AND
nonvolatile memory. The tolerance is stored in the memory during RESISTOR TERMINALS
factory production and can be read by users at any time. The
knowledge of stored tolerance allows users to accurately calculate The AD5259 VDD, VLOGIC, and GND power supplies define the
RAB. This feature is valuable for precision, rheostat mode, and boundary conditions for proper 3-terminal and digital input opera-
open-loop applications where knowledge of absolute resistance is tion. Supply signals present on Terminal A, Terminal B, and Termi-
critical. nal W that exceed VDD or GND are clamped by the internal forward
biased ESD protection diodes (see Figure 42). Digital Input SCL
The stored tolerance resides in the read-only memory and is ex- and Digital Input SDA are clamped by ESD protection diodes with
pressed as a percentage. The tolerance is stored in two memory respect to VLOGIC and GND as shown in Figure 43.
location bytes in sign magnitude binary form (see Figure 41).
The two EEPROM address bytes are 11110 (sign + integer)
and 11111 (decimal number). The two bytes can be individually ac-
cessed with two separate commands (see Table 15). Alternatively,
readback of the first byte followed by the second byte can be
done in one command (see Table 17). In the latter case, the
memory pointer will automatically increment from the first to the Figure 42. Maximum Terminal Voltages Set by VDD and GND
second EEPROM location (increments from 11110 to 11111) if read
consecutively. In the first memory location, the MSB is designated
for the sign (0 = + and 1= −) and the seven LSBs are designated
for the integer portion of the tolerance. In the second memory
location, all eight data bits are designated for the decimal portion of
tolerance. Note the decimal portion has a limited accuracy of only
0.1%. For example, if the rated RAB = 10 kΩ and the data readback
from Address 11110 shows 0001 1100, and Address 11111 shows Figure 43. Maximum Terminal Voltages Set by VLOGIC and GND
0000 1111, then the tolerance can be calculated as
POWER-UP SEQUENCE
MSB: 0 = +
Next 7 MSB: 001 1100 = 28 Because the ESD protection diodes limit the voltage compliance
8 LSB: 0000 1111 = 15 × 2–8 = 0.06 at Terminal A, Terminal B, and Terminal W (see Figure 42), it
Tolerance = +28.06% is important to power GND/VDD/VLOGIC before applying any voltage
Rounded Tolerance = +28.1% and therefore, to Terminal A, Terminal B, and Terminal W; otherwise, the diode is
RAB_ACTUAL = 12.810 kΩ forward biased, so the VDD and VLOGIC are powered unintentionally
and may affect the user’s circuit. The ideal power-up sequence is
in the following order: GND, VDD, VLOGIC, digital inputs, and then
VA, VB, VW. The relative order of powering VA, VB, VW, and the

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Data Sheet AD5259
I2C-COMPATIBLE FORMAT

digital inputs is not important as long as they are powered after

GND/VDD/VLOGIC.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to use compact, minimum lead length layout
design. The leads to the inputs should be as direct as possible
with minimum conductor length. Ground paths should have low
resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with disc or chip ceramic capacitors of 0.01 µF
to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors
should also be applied at the supplies to minimize any transient
disturbance and low frequency ripple (see Figure 44). The digital
ground should also be joined remotely to the analog ground at one
point to minimize the ground bounce.

Figure 44. Power Supply Bypassing

MULTIPLE DEVICES ON ONE BUS

The AD5259 has two configurable address pins, Pin AD0 and Pin
AD1. The state of these two pins is registered upon power-up and
decoded into a corresponding I2C-compatible 7-bit address (see
Table 5). This allows up to four devices on the bus to be written to
or read from independently.
EVALUATION BOARD
An evaluation board, with all necessary software, is available
to program the AD5259 from any PC running Windows® 98/ 2000/
XP. The graphical user interface, as shown in Figure 45, is straight-
forward and easy to use. More detailed information is available in
the board’s user manual.

Figure 45. AD5259 Evaluation Board Software

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Data Sheet AD5259
DISPLAY APPLICATIONS

CIRCUITRY draw of VDD will not affect that node’s bias because it is only on the
order of microamps. VLOGIC is tied to the MCU’s 3.3 V digital supply
A special feature of the AD5259 is its unique separation of the VLO- because VLOGIC will draw the 35 mA that is needed when writing
GIC and VDD supply pins. The separation provides greater flexibility to the EEPROM. It would be impractical to try and source 35 mA
in applications that do not always provide needed supply voltages. through the 70 kΩ resistor. Therefore, VLOGIC is not connected to
In particular, LCD panels often require a VCOM voltage in the range the same node as VDD.
of 3 V to 5 V. The circuit in Figure 46 is the rare exception in which For this reason, VLOGIC and VDD are provided as two separate sup-
a 5 V supply is available to power the digital potentiometer. ply pins that can either be tied together or treated independently;
VLOGIC supplying the logic/EEPROM with power, and VDD biasing
up the A, B, and W terminals for added flexibility.

Figure 46. VCOM Adjustment Application

In the more common case shown in Figure 47, only analog 14.4 V
Figure 47. Circuitry When a Separate Supply is Not Available for VDD
and digital logic 3.3 V supplies are available. By placing discrete
resistors above and below the digital potentiometer, VDD can now For a more detailed look at this application, refer to the article,
be tapped off the resistor string itself. Based on the chosen resistor “Simple VCOM Adjustment uses any Logic Supply Voltage” in the
values, the voltage at VDD in this case equals 4.8 V, allowing the September 30, 2004 issue of EDN magazine.
wiper to be safely operated all the way up to 4.8 V. The current

analog.com Rev. D | 20 of 22
Data Sheet AD5259
OUTLINE DIMENSIONS

Figure 48. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)
Dimensions shown in millimeters

Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters

Updated: April 22, 2022

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Packing Quantity Option Marking Code
AD5259BCPZ100-R7 -40°C to +125°C 10-Lead LFCSP (3mm x 3mm) Reel, 1500 CP-10-9 D4S
AD5259BCPZ10-R7 -40°C to +125°C 10-Lead LFCSP (3mm x 3mm) Reel, 1500 CP-10-9 D4Q
AD5259BCPZ50-R7 -40°C to +125°C 10-Lead LFCSP (3mm x 3mm) Reel, 1500 CP-10-9 D4R
AD5259BCPZ5-R7 -40°C to +125°C 10-Lead LFCSP (3mm x 3mm) Reel, 1500 CP-10-9 D4P
AD5259BRMZ10 -40°C to +125°C 10-Lead MSOP Tube RM-10 D4Q
AD5259BRMZ100 -40°C to +125°C 10-Lead MSOP Tube RM-10 D4S
AD5259BRMZ100-R7 -40°C to +125°C 10-Lead MSOP Reel, 1000 RM-10 D4S
AD5259BRMZ10-R7 -40°C to +125°C 10-Lead MSOP Reel, 1000 RM-10 D4Q
AD5259BRMZ5 -40°C to +125°C 10-Lead MSOP Tube RM-10 D4P
AD5259BRMZ50 -40°C to +125°C 10-Lead MSOP Tube RM-10 D4R
AD5259BRMZ50-R7 -40°C to +125°C 10-Lead MSOP Reel, 1000 RM-10 D4R
AD5259BRMZ5-R7 -40°C to +125°C 10-Lead MSOP Reel, 1000 RM-10 D4P
1 Z = RoHS Compliant Part.

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Data Sheet AD5259
OUTLINE DIMENSIONS

RAB (Ω) OPTIONS

Model1 RAB (Ω)
AD5259BCPZ100-R7 100 k
AD5259BCPZ10-R7 10 k
AD5259BCPZ50-R7 50 k
AD5259BCPZ5-R7 5k
AD5259BRMZ10 10 k
AD5259BRMZ100 100 k
AD5259BRMZ100-R7 100 k
AD5259BRMZ10-R7 10 k
AD5259BRMZ5 5k
AD5259BRMZ50 50 k
AD5259BRMZ50-R7 50 k
AD5259BRMZ5-R7 5k
1 Z = RoHS Compliant Part.

EVALUATION BOARDS
Model1 Description
EVAL-AD5259DBZ Evaluation Board2
1 Z = RoHS Compliant Part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

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