Chapter 4 01 Introduction

Sequential Circuit
02
Design Multivibrators

“Tell me and I forget, teach me and I may

remember, involve me and I understand” 03 Latch, Flip-Flop,
(Benjamin Franklin) 04 and Timers
Register and
Counters

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 Introduction
2

▪ Up until now, every logic circuit we have examined has mostly relied on the examination and creation
of combinational digital circuits.
▪ Despite their great importance, these kinds of circuits only make up a small portion of digital systems.
▪ Analyzing and designing sequential digital circuits is the other key component of a digital system.
▪ On the other hand, combinational circuit design has a significant influence on sequential circuit design.

▪ Sequential circuits are logic circuits whose outputs at any one time depend
on both the inputs that are being used and the outputs that have come
before. The output signals in sequential circuits are fed back into the input
side. Figure 4.1 displays a block diagram of a sequential circuit
Figure 4.1
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 Introduction
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▪ From Figure 4.1, we find that it consists of combinational circuits, which accept digital signals from
external inputs and from outputs of memory elements and generates signals for external outputs and for
inputs to memory elements, referred to as excitation.
Note that
▪ A memory element is a medium in which one bit of information (0 or 1) can be stored
or retained until necessary, and thereafter its contents can be replaced by a new value.
▪ The contents of memory elements can be changed by the outputs of combinational
circuits that are connected to its input.

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 Introduction
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Feature Sequential Circuit Computational Circuit

Stores and processes data in sequential fashion, where Performs computations or mathematical operations on
Functionality output depends on current state and input. input data to generate output.

State Utilizes memory elements (e.g., flip-flops) to store state Typically does not involve state storage elements;
Elements information. focuses on arithmetic and logic operations.
Feedback loops are commonly used to retain state Feedback loops are not typically utilized; computations
Feedback information and enable sequential behavior. are performed directly on input data.
Timing is important but may not be as strictly controlled;
Timing and sequencing of operations are critical;
Timing operations are synchronized with clock signals.
operations are performed based on input availability and
computational requirements.
May be less complex, particularly for simple arithmetic
Generally more complex due to the presence of memory
Complexity elements and sequential logic.
or logic operations without the need for sequential
behavior.
Arithmetic logic units (ALUs), adders, multipliers, digital
Examples Finite state machines, counters, shift registers.
signal processors (DSPs).
Mathematical computations, signal processing, data
Control units, data processing units in CPUs, digital
Application systems requiring memory and sequential logic.
manipulation in various applications such as DSPs,
calculators, and digital filters.
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 Introduction
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Depending on timing of their signal Sequential circuits are broadly classified into two main categories

Synchronous or Clocked Asynchronous or Unclocked

• Its defined from the knowledge of its signal at discrete ▪ Its behavior depends upon the sequence in which the
instants of time. The synchronization is achieved by a input signals change. The commonly used memory
timing device known as a system clock, w/c generates a
periodic train of clock pulses The outputs are affected only elements in these circuits are time-delay devices. There is
with the application of a clock pulse. no need to wait for a clock pulse. Therefore, in general,
▪ The rate at which the master clock generates pulses must asynchronous circuits are faster than synchronous
be slow enough to permit the slowest circuit to respond.
This limits the speed of all circuits. sequential circuits. However, in an asynchronous circuit,

▪ Synchronous circuits have gained considerable events are allowed to occur without any synchronization.
domination and wide popularity. ▪ Thus, in this case the system becomes unstable
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 Introduction
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Feature Synchronous Sequential Circuit Asynchronous Sequential Circuit

Clock Dependency Dependent on a clock signal for operation. Not dependent on a clock signal; operates based on events.
Timing constraints are critical; operations synchronized with clock
Timing Constraints edges.
Timing constraints are less critical; operations are event-driven.

Does not require a global clock signal; may use local signals or handshaking protocols for
Clock Signal Requires a global clock signal for synchronization.
synchronization.

State Changes State changes occur synchronously with clock edges. State changes can occur asynchronously in response to external events.

May be more complex due to the absence of a global clock and the need for hazard
Design Complexity Generally simpler in design due to synchronous operation.
avoidance mechanisms.

Propagation Delay Typically has uniform propagation delay across flip-flops. May exhibit variable propagation delay due to different paths and delays in the circuit.

Tends to have higher power consumption due to continuous clock

Power Consumption signal operation.
Can potentially have lower power consumption as activity is event-driven.

Noise Sensitivity Less susceptible to noise due to synchronous operation. More susceptible to noise, as changes in input may cause immediate state transitions.

Scalability Scalability may be limited due to clock distribution issues. Generally more scalable as it does not rely on a centralized clock.

Testing and debugging may be more challenging due to potential race conditions and
Testing and Debugging Testing and debugging may be facilitated by synchronous behavior. hazards.

Example Application CPU, microcontrollers, synchronous data transmission. Asynchronous communication protocols, asynchronous state machines.

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▪ Bistable, monostable, and astable logic devices called multivibrators.

Bistable
▪ Bistable devices are helpful as storage devices because they have two stable states that they
can maintain forever, dubbed SET and RESET.
▪ Two types of bistable devices are flip-flops and latches.
• The method by which latches and flip-flops are switched from one state to another is
their primary distinction.
• A fundamental component of registers, counters, and timer other sequential control
circuits, the flip-flop is found in several memory types.

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Monostable
▪ Only one stable state exists in the monostable multivibrator, sometimes referred to as the
one-shot.
• Upon activation or trigger, a one-shot generates a single controlled-width pulse.
Astable
▪ An oscillator, or self-sustaining waveform generator, is the main application for an astable
multivibrator as it lacks a stable state.
▪ For timing waveforms in digital systems, pulse oscillators are employed as sources.

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Latch's
1. S-R (Set-Reset) latch
▪ It can be constructed from
NOR gates or NAND gates.

a) S-R Latch Using NOR gates

To get the output of S-R latch we need present input (i.e. R-S) and
Present States (Q) as shown in the diagram. And we have different cases
0 1 1
0

1 0
1 0

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Latch's
▪ The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW. Hence, the next output
will be Q it self Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0)
When Q=0➔ Q1=(R+Q’)’=(0+1)’=0 or Q=1➔Q1=(R+Q’)=(0+1’)’=1
➔ Q1’=(S+Q)’=(0+0)’=1 or Q’=0➔Q1’=(S+Q)=(0+1)’=0
Hence, Q1=(R+Q’)’=(0+Q’)’=Q Q1’=(S+Q)’=(0+Q)’=Q’
▪ R=1 & S=1 and we have Q=0 or Q=1 as an input so the next output Q1 is determined by following the above
procedure. Hence, Q1=(R+Q’)’=(1+Q’)’=0 Q1’=(S+Q)’=(1+Q)’=0 so if Q1=0, Q1’ must be equal to 1 but here
we got Q1=Q1’ which is impossible. So, this state is called indeterminate or invalid state.

▪ To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW.
▪ To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW.

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Latch's
1. S-R (Set-Reset) latch
b) S-R Latch Using NAND gates
(follow the same procedure)

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Latch's
1. S-R (Set-Reset) latch
▪ S-R latches are frequently used for switch debounce (bounce
eliminator) circuits as shown:
✓ The switch is normally in position 1 keeping the R’ input LOW
and the latch reset.
✓ When the switch is thrown to position 2 R’ goes HIGH because
of pull-up resister in position to Vcc and S’ goes low in the 1st
contact and remain only for a very short time before the switch
bounces, this is efficient to set the latch and it remain SET.

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IMPLEMENTATION: S’R’ LATCH Fixed-Function Device 74HC279A

▪ The 74HC279A is a quad S@R latch represented by the logic diagram of Figure
4.2-(a) and the pin diagram in part (b). Notice that two of the latches each have two
S’ inputs.

FIGURE 4.2 The 74HC279A

quad S’R’ latch
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Latch's
2. The gated S-R (Set-Reset) latch
▪ A gated latch is a variation on the basic latch.
▪ The gated latch has an additional input, called
enable (EN) that must be HIGH in order for the
latch to respond to the S and R inputs.

EXAMPLE Determine the Q output waveform if the inputs shown in Figure above are applied to a gated S-
R latch that is initially RESET.

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3. The gated D-latch

▪ A gated latch is a variation on the basic latch.
▪ The gated latch has an additional input, called
enable (EN) that must be HIGH in order for
the latch to respond to the S and R inputs.
1. Example Determine the Q output waveform if the inputs shown in above (a) are applied to a gated D
latch, which is initially RESET.

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IMPLEMENTATION: GATED D LATCH Fixed-Function Device 74HC75

▪ It is an example of a gated D latch, represented by the logic symbol in Figure 4.3(a).
▪ The device has four latches. Notice that each active-HIGH EN input is shared by two
latches and is designated as a control input (C). The TT for each latch is shown in (b).

▪ The X in the truth table represents a “don’t

care” condition.
▪ In this case, when the EN input is LOW, it
does not matter what the D input is because
the outputs are unaffected and remain in

FIGURE 4.3 The 74HC75 quad D latch. their prior states.

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1. List three types of latches.

2. Develop the truth table for the active-HIGH input S-R latch
3. What is the Q output of a D latch when EN = 1 and D = 1?

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Did you know?

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Flip-Flops
▪ The basic 1-bit digital memory circuit is known as a flip-flop.
▪ It can have only two states, either the 1 state or the 0 state.
▪ It is also known as a bistable multivibrator.
▪ It can be obtained by using NAND or NOR gates and it is general block diagram representation is
shown in Figure 4.4. It has one or more inputs and two outputs.
▪ The state of Q is called the state of the flip flop, whereas the state of
Q' is called the complementary state of the flip-flop.
Figure 4.4 Block diagram of a flip-flop. ▪ Since the output of the flip-flop remains in the same state until the
trigger pulse is applied to change the state, it can be regarded as a memory device to store one binary bit.
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▪ As mentioned earlier, a flip-flop is also known as a bistable multivibrator, whose circuit is shown in
Figure 4.5, where the trigger inputs are named as Set, S and Reset, R.
▪ From the circuit shown in Figure 4.5, Obviously, if transistor T1 is initially turned
ON (saturated) by applying a positive signal through the Set input at its base, its
collector will be at VCE (sat) (0.2 to 0.4 V). The collector of T1 is connected to the
base of T2 , which cannot turn T2 On. Hence, T2 remains OFF (cut off).
Figure 4.5 Bistable ▪ Therefore, the voltage at the collector of T2 tries to reach VCC. This action only
multivibrator circuit. enhances the initial positive signal applied to the base of T1 .
Now if the initial signal at the Set input is removed, the circuit will maintain T1 in the ON state and T2 in the OFF state indefinitely
i.e., Q = 1 and Q' = 0. In this condition the bistable multivibrator is said to be in the Set state.
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▪ A positive signal applied to the Reset input at the base of T2 turns it ON. As we have discussed earlier,
in the same sequence T2 turns ON and T1 turns OFF, resulting in a second stable state, i.e., Q = 0 and Q'
= 1. In this condition the bistable multivibrator is said to be in the Reset state.

Thus,
✓ Flip flops is Synchronous bi-stable device.
• Synchronous means that the output changes states only at a specified
point on the triggering input called the clock (CLK).
• Hence, changes in the output occur in synchronization with the clock
✓ Therefore, a flip-flop differs from a latch in the manner it changes states.

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An edge-triggered flip-flop
▪ It changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the
clock pulse and is sensitive to its inputs only at this transition of the clock.
Four types of edge-triggered flip-flops are covered in this section:

D Flip-Flop T- Flip-Flop J-K Flip-Flop

S S

R R

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▪ The major difference between flip-flop and latch is that the flip-flop is an edge-
triggered type of memory circuit while the latch is a level-triggered type.
• It means that the output of a latch changes whenever the input changes.
▪ Thus, A flip flop,, is synchronous and is also known as gated or clocked SR latch.
• The output is changed (i.e. the stored data is changed) only when you give an active clock signal.

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▪ The S and R input of the S-R flip flop are called synchronous
▪ Remember: the flip flop can not change state except on the trigger edge of the clock pulse

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Example

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D Flip-Flop A basic D-flip flop is created by adding an inverter to an S-R flip flop.

FIGURE 4.5 Edge triggering.

▪ Notice that the basic D flip-flop differs from the gated D latch only in that it has a pulse transition
detector. One basic type of pulse transition detector is shown in Figure 4.5(b).
• As you can see, there is a small delay through the inverter on one input to the NAND gate so that the inverted clock pulse arrives at the
gate input a few nanoseconds after the true clock pulse. This circuit produces a very short-duration spike on the positive-going
transition of the clock pulse.
• In a negative edge-triggered flip-flop the clock pulse is inverted first, thus producing a narrow spike on the negative-going edge
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D Flip-Flop
A basic D-flip flop is created by adding an inverter to an S-R flip flop.
▪ This basic operation of a positive and negative edge-triggered D flip-flop is illustrated in Figure below

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D Flip-Flop

EXAMPLE Determine the Q and Q output waveforms of the flip-flop in Figure below for the D and CLK
inputs in. Assume that the positive edge-triggered flip-flop is initially RESET.

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D Flip-Flop

EXAMPLE Given the waveforms in Figure below for the D input and the clock, determine the Q output
waveform if the flip-flop starts out RESET.

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D Flip-Flop Did you know?

Semiconductor memories consist of large numbers of individual cells. Each storage cell holds a 1
or a 0. One type of memory is the Static Random Access Memory or SRAM, which uses flip-flops
for the storage cells because a flip-flop will retain either of its two states indefinitely as long as dc
power is applied, thus the term static. This type of memory is classified as a volatile memory
because all the stored data are lost when power is turned off. Another type of memory, the
Dynamic Random Access Memory or DRAM, uses capacitance rather than flip-flops as the basic
storage element and must be periodically refreshed in order to maintain the stored data.

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▪ It has identical function with S-R flip flop in the SET, RESET & no change condition
of operation but has no invalid state as does S-R flip flop when both inputs are HIGH
▪ When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the
rising edge). This called the toggle mode
The fundamental internal logic of a positive edge-triggered J-K flip-flop is depicted in Figure 7–23.
▪ The Q output is linked to both the input of gate G2 and the input of gate
G1, returning the Q output to both.
▪ Jack Kilby, the man who designed the integrated circuit, is honored by the
FIGURE 4.6 A simplified logic diagram for labels J and K on the two control inputs. It is possible for a J-K flip-flop to
a positive edge-triggered J-K flip-flop. be negative edge-triggered, in which case the clock input is reversed.

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▪ This basic operation of a positive edge-triggered flip-flop is illustrated in Figure 4.6,

and Table below is the truth table for this type of flip-flop.

▪ The J and K inputs can be changed at any time

when the clock input is LOW or HIGH (except for a
very short interval around the triggering transition
of the clock) without affecting the output.
FIGURE 4.6 Operation of a positive edge-triggered J-K flip-flop.
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EXAMPLE The waveforms in Figure below are applied to the J, K, and clock inputs as
indicated. Determine the Q output, assuming that the flip-flop is initially RESET.

1. At the first clock pulse, both J and K are HIGH; and

because this is a toggle condition, Q goes HIGH.
2. At clock pulse 2, a no-change condition exists on the inputs, keeping Q at a HIGH level.
3. When clock pulse 3 occurs, J is LOW and K is HIGH, resulting in a RESET condition; Q goes LOW.
4. At clock pulse 4, J is HIGH and K is LOW, resulting in a SET condition; Q goes HIGH.
5. A SET condition still exists on J and K when clock pulse 5 occurs, so Q will remain HIGH.
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Did you know?

All logic operations that are performed with hardware can also be implemented in
software. For example, the operation of a J-K flip-flop can be performed with specific
computer instructions. If two bits were used to represent the J and K inputs, the computer
would do nothing for 00, a data bit representing the Q output would be set (1) for 10, the
Q data bit would be cleared (0) for 01, and the Q data bit would be complemented for 11.
Although it may be unusual to use a computer to simulate a flip-flop, the point is that all
hardware operations can be simulated using software.

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▪ In toggle mode operation on each clock spike, the flip flop change to opposite
T- Flip-Flop
state. When a J-K flip flop connected for toggle operation is called T-flip flop

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Asynchronous Preset and Clear Inputs

▪ The S-R, D J-K and T inputs for the previously stated flip-flops are referred to as synchronous inputs
because the data on these inputs are only sent synchronously with the clock, that is, on the triggering
edge of the clock pulse.
▪ Asynchronous inputs are also included in the majority of integrated circuit (IC) flip-flops. These are
inputs that, apart from the clock, change the flip-flop's state.
▪ Typically, manufacturers name them as preset (PRE) and clear (CLR), or as direct set
(SD) and direct reset (RD). The flip-flop is set by an active level on the preset input
and reset by an active level on the clear input.
▪ Figure illustrates a logic symbol for a D flip-flop with preset and clear inputs.
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Asynchronous Preset and Clear Inputs

The logic diagram for an edge-triggered D flip-flop with clear (CLR) and active-LOW preset (PRE)
inputs is shown in Figure 4.7.
▪ This figure essentially shows how these inputs function.
▪ As you can see, they are linked in a way that negates the
impact of D, the clock, and the synchronous input.

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Asynchronous Preset and Clear Inputs

EXAMPLE For the positive edge-triggered D flip-flop with preset and clear inputs in Figure Below,
determine the Q output for the inputs shown in the timing diagram in part (a) if Q is initially LOW.

▪ Let’s look at two specific edge-triggered flip-flops. They are representative of the various types of flip-flops available in fixed-
function IC form and, like most other devices, are available in CMOS and in bipolar (TTL) logic families.

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IMPLEMENTATION: D FLIP-FLOP-Fixed-Function Device the 74HC74 dual D flip-flop

▪ It contains two identical D flip-flops that are independent of each other except for sharing VCC and
ground. The flip-flops are positive edge-triggered and have active-LOW asynchronous preset and
clear inputs.
▪ The logic symbols for the individual flip-flops within
the package are shown in Figure 4.8(a), and an
ANSI/IEEE standard single block symbol that
represents the entire device is shown in part (b).
▪ The pin numbers are shown in parentheses.

FIGURE 4.8 The 74HC74 dual positive edge-triggered D flip-flop.

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IMPLEMENTATION: J-K FLIP-FLOP Fixed-Function Device The 74HC112 dual J-K flip-flop
▪ It has two identical flip-flops that are negative edge-triggered and have active-LOW asynchronous
preset and clear inputs.
▪ The logic symbols are shown in Figure 4.9.

FIGURE 4.9 The 74HC112 dual negative edge-

triggered J-K flip-flop.

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EXAMPLE The 1J, 1K, 1CLK, 1PRE’, and 1CLR’ waveforms in Figure below (a) are applied to one of the
negative edge-triggered flip-flops in a 74HC112 package. Determine the 1Q output waveform.

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Operating Characteristics
▪ The performance, operating requirements, and limitations of flip-flops are specified by several
operating characteristics or parameters found on the data sheet for the device.
▪ Generally, the specifications are applicable to all CMOS and bipolar (TTL) flip-flops.
I. Propagation Delay Times
▪ A propagation delay time is the interval of time required after an input signal has been applied for the
resulting output change to occur. Four categories of propagation delay times are important in the
operation of a flip-flop:
1. Propagation delay tPLH as measured from the triggering edge of the clock pulse to the LOW-to-HIGH
transition of the output. This delay is illustrated in Figure 4.10(a).
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Operating Characteristics
2. Propagation delay tPHL as measured from the triggering edge of the clock pulse to the HIGH-to-LOW
transition of the output. This delay is illustrated in Figure 4.10(b).

FIGURE 4.10 Propagation delays, clock to output.

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Operating Characteristics
3. Propagation delay tPLH as measured from the leading edge of the preset input to the LOW-to-HIGH
transition of the output. This delay is illustrated in Figure 4.11(a) for an active-LOW preset input. 4
4. Propagation delay tPHL as measured from the leading edge of the clear input to the HIGH-to-LOW
transition of the output. This delay is illustrated in Figure 4.11(b) for an active-LOW clear input.

FIGURE 4.11 Propagation delays, preset input to output and clear input to output.
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Operating Characteristics
2. Set-up Time

▪ The set-up time (ts ) is the minimum interval required for the logic levels to be maintained constantly
on the inputs (J and K, or D) prior to the triggering edge of the clock pulse in order for the levels to be
reliably clocked into the flip-flop. This interval is illustrated in Figure 4.12 for a D flip-flop.

FIGURE 4.12 Set-up time (ts ). The logic level must be present on the D input for a time equal to or greater than ts before the
triggering edge of the clock pulse for reliable data entry.
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Operating Characteristics
3. Hold Time

▪ The hold time (th ) is the minimum interval required for the logic levels to remain on the inputs after
the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
This is illustrated in Figure 4.13 for a D flip-flop.

• FIGURE 4.13Hold time (th). The logic level must remain on the D input for a time equal to or greater than th after the
triggering edge of the clock pulse for reliable data entry.
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Operating Characteristics
4. Maximum Clock Frequency

▪ The maximum clock frequency (fmax) is the highest rate at which a flip-flop can be reliably triggered.
▪ At clock frequencies above the maximum, the flip-flop would be unable to respond quickly enough,
and its operation would be impaired.
5. Pulse Widths
▪ Minimum pulse widths (tW) for reliable operation are usually specified by the manufacturer for the
clock, preset, and clear inputs. Typically, the clock is specified by its minimum HIGH time and its
minimum LOW time.

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5. Power Dissipation Operating Characteristics

▪ The power dissipation of any digital circuit is the total power consumption of the device. For example, if
the flip-flop operates on a +5 V dc source and draws 5 mA of current, the power dissipation is
P = VCC * ICC = 5 V * 5 mA = 25 mW
▪ The power dissipation is very important in most applications in which the capacity of the dc supply is a
concern. As an example, let’s assume that you have a digital system that requires a total of ten flip-
flops, and each flip-flop dissipates 25 mW of power. The total power requirement is
PT = 10 * 25 mW = 250 mW = 0.25 W, This tells you the output capacity required of the dc supply.

▪ If the flip-flops operate on +5 V dc, then the amount of current that the supply must provide is I = 250
mW 5 V = 50 mA You must use a +5 V dc supply that is capable of providing at least 50 mA of current.
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Comparison of Specific Flip-Flops Operating Characteristics

▪ Table 4.2 provides a comparison, in terms of the operating parameters discussed in this section, of four
CMOS and bipolar (TTL) flip-flops of the same type but with different IC families (HC, AHC, LS, and F).
Table 4.2

Which specific flip-flop can be

operated at the highest frequency?

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Operating Characteristics

An advantage of CMOS is that it can operate over a wider range of dc supply voltages
(typically 2 V to 6 V) than bipolar and, therefore, less expensive power supplies that do
not have precise regulation can be used. Also, batteries can be used as secondary or
primary sources for CMOS circuits. In addition, lower voltages mean that the IC
dissipates less power. The drawback is that the performance of CMOS is degraded with
lower supply voltages. For example, the guaranteed maximum clock frequency of a
CMOS flip-flop is much less at VCC = 2 V than at VCC = 6 V.
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Flip-Flop Applications

▪ In this section, three general applications of flip-flops are discussed to give you an idea of
how they can be used. In lecture 1, flip-flop applications in registers and counters are
covered in detail.

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Flip-Flop Applications
Registers
▪ A register, in general, is used solely for storing and shifting data
(1s and 0s) entered into it from an external source and typically
possesses no characteristic internal sequence of states.
Example Parallel Data Storage
▪ This four group of flip flop is an example of basic register used
for data storage
▪ In digital system, data are normally stored usually in a group
of bit (usually 8-bir or multiple thereof) that represent
numbers, codes or other information's
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Frequency division Flip-Flop Applications

▪ Another application is reducing (dividing) the frequency of periodic waveform by applying a pulse
in a clock input of toggle J-K flip flop. Thus, a single flip flop can be applied as a divided by 2 device
as shown in figure 4.14. Further division of a clock frequency can be achieved by using the output of
one flipflop as the clock input to a second flip-flop, as shown in Figure4.15. The frequency of the QA
output is divided by 2 by flip-flop B. The QB output is, therefore, one-fourth the frequency of the
original clock input. Propagation delay times are not shown on the timing diagrams.

FIGURE 4.14 FIGURE 4.15

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Frequency division Flip-Flop Applications

▪ By connecting flip-flops in this way, a frequency division of 2𝑛 is achieved, where n is the number of
flip-flops. For example, three flip-flops divide the clock frequency by 23 = 8; four flip-flops divide
the clock frequency by 24 = 16; and so on.

Example: Develop the fout of 1KHz waveform from 8 kHz square wave input clock

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Counting Flip-Flop Applications

▪ Another important application flip-flops is in digital counter.
▪ Consider 2 a negative edge J-K flip flop both the flip flop is initially RESET as shown below
▪ The Q output of flip-flop A clocks flip-flop B, so
each time QA makes a HIGH-to-LOW transition,
flip-flop B toggles. The resulting QA and QB
waveforms are shown in the figure.
▪ Observe the sequence of QA and QB
▪ This binary sequence repeats every four clock pulses, as
shown in the timing diagram of Figure below Thus, the flip-
flops are counting in sequence from 0 to 3 (00, 01, 10, 11) and
then recycling back to 0 to begin the sequence again.
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Counting Flip-Flop Applications

EXAMPLE produce a binary sequence representing decimal numbers 0 through 7?

▪ The output timing diagram is shown in Figure

below. Notice that the outputs change on the
negative-going edge of the clock pulses.
▪ The outputs go through the binary sequence
000, 001, 010, 011, 100, 101, 110, and 111 as
indicated.
Related Problem
1. How many flip-flops are required to produce a binary sequence representing decimal numbers 0 through 15?
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1. What is a group of flip-flops used for data storage called?

2. How must a D flip-flop be connected to function as a divide-by-2 device?
3. How many flip-flops are required to produce a divide-by-64 device?

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58

▪ The one-shot, also known as a monostable multivibrator, is a device with only one
stable state.
▪ A one-shot is normally in its stable state and will change to its unstable state only
when triggered.
▪ Once it is triggered, the one-shot remains in its unstable state for a predetermined
length of time and then automatically returns to its stable state.
▪ The time that the device stays in its unstable state determines the pulse width of its
output.
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Assignment
1. Describe the basic operation of a one-shot
2. Explain how a non-retriggerable one-shot works
3. Explain how a retriggerable one-shot works
4. Set up the 74121 and the 74LS122 one-shots to obtain a specified output pulse width

1. Recognize a Schmitt trigger symbol and explain basically what it means

2. Describe the basic elements of a 555 timer
3. Set up a 555 timer as a one-shot

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▪ An astable multivibrator is a device that has no stable states;

▪ it changes back and forth (oscillates) between two unstable states without any external triggering.
▪ The resulting output is typically a square wave that is used as a clock signal in many types of
sequential logic circuits.
▪ Astable multivibrators are also known as pulse oscillators.

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Assignment

1. Describe the operation of a simple astable multivibrator using a Schmitt trigger circuit.
2. Set up a 555 timer as an astable multivibrator.

By Abdulaziz J. Sequential Circuit Design 5/20/2024