Sontyam,Anandapuram,Visakhapatnam, AP.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

ELECTRONIC DEVICES AND CIRCUITS

LABORATORY MANUAL
FOR
II B.TECH, I SEMESTER
(R20 Regulations)

Prepared by
Mr K.S.V.RAMANAJI , M.TECH
Assistant Professor ,Dept Of ECE
 INSTITUTE

VISION

 To promote societal empowerment and become an Institute of

Excellence in the field of engineering education, research

MISION

 To enable the students and develop into outstanding professionals

through innovative teaching learning process with high ethical
standards capable of creating, developing and managing global
engineering enterprises
 To involve students and faculty in collaborative research projects,
which offer opportunities for long term interaction with academic,
research institutions and industry
 To develop a responsible and productive citizenry

ECE DEPARTMENT

VISI
To undertake thrust research areas and to make the students globally
competent technocrats
ON

MISION

To bring out competent young Electronics & Communication

Engineers by achieving excellence in imparting technical skills, soft
skills and the right attitude for continuous learning
 CODE OF CONDUCT FOR THE LABORATORIES
A. All students must observe the Dress Code while in the laboratory.

B. Sandals or open-toed shoes are NOT allowed.

C. Foods, drinks and smoking are NOT allowed.

D. All bags must be left at the indicated place.

E. The lab timetable must be strictly followed.

F. Be PUNCTUAL for your laboratory session.

G. Program must be executed within the given time.

H. Noise must be kept to a minimum.

I. Workspace must be kept clean and tidy at all time.

J. Handle the systems and interfacing kits with care.

K. All students are liable for any damage to the accessories due to their own negligence.

L. All interfacing kits connecting cables must be RETURNED if you taken from the
lab supervisor.

M. Students are strictly PROHIBITED from taking out any items from the laboratory.

N. Students are NOT allowed to work alone in the laboratory without the Lab Supervisor

O. USB Ports have been disabled if you want to use USB drive consult lab supervisor.

P. Report immediately to the Lab Supervisor if any malfunction of the accessories, is there.

Before leaving the lab

1. Place the chairs properly.

2. Turn off the kits properly

Please check the laboratory notice board regularly for updates

 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA
B.TECH. (ELECTRONICS AND COMMUNICATION ENGINEERING)

II Year – I SEMESTER
T P C
0 3 2
ELECTRONIC DEVICES AND CIRCUITS LAB
PART A: Electronic Workshop Practice
 Identification, Specifications, Testing of R, L, C Components (Colour Codes), Potentiometers,
Coils, Gang Condensers, Relays, Bread Boards.
 Identification, Specifications and Testing of active devices, Diodes, BJTs, JFETs, LEDs, LCDs,
SCR, UJT.
 Soldering Practice- Simple circuits using active and passive components.
 Study and operation of Ammeters, Voltmeters, Transformers, Analog and Digital
Multimeter, Function Generator, Regulated Power Supply and CRO.
PART B: List of Experiments (For Laboratory Examination-Minimum of Ten Experiments)
1. P-N Junction Diode Characteristics
a. Part A: Germanium Diode (Forward bias& Reverse bias)
b. Part B: Silicon Diode (Forward Bias only)
2. Zener Diode Characteristics
a. Part A: V-I Characteristics
b. Part B: Zener Diode as Voltage Regulator
3. Rectifiers (without and with c-filter)
a. Part A: Half-wave Rectifier Part B: Full-wave Rectifier
4. BJT Characteristics(CE Configuration)
a. Part A: Input Characteristics Part B: Output Characteristics
5. FET Characteristics(CS Configuration)
a. Part A: Drain Characteristics Part B: Transfer Characteristics
6. SCR Characteristics
7. UJT Characteristics
8. Transistor Biasing
9. CRO Operation and its Measurements
10. BJT-CE Amplifier
11. Emitter Follower-CC Amplifier
12. FET-CS Amplifier
PART C: Equipment required for Laboratory
1. Boxes 2. Ammeters (Analog or Digital)
3. Voltmeters (Analog or Digital) 4. Active & Passive Electronic Components
5. Regulated Power supplies 6. Analog/Digital Storage Oscilloscopes
7. Analog/Digital Function Generators 8. Digital Multimeters
9. Decade Résistance Boxes/Rheostats 10. Decade Capacitance
 ELECTRONIC CIRCUIT ANALYSIS LABORATORY

LIST OF EXPERIMENTS
(HARDWARE)

S.No Name of the Page No

Experiment

1 P-N Junction Diode Characteristics 1

2 Zener Diode Characteristics 7

3 Rectifiers (without and with c-filter) 13
4 BJT Characteristics 20
5 FET Characteristics 25
6 SCR Characteristics 29
7 UJT Characteristics 33
8 Transistor Biasing 37
9 CRO Operation and its Measurements 40
10 BJT-CE Amplifier 44
11 Emitter Follower-CC Amplifier 48
12 FET-CS Amplifier 52

ADDITIONAL EXPERIMENTS

S.No Name of the Page No

Experiment
1 Characteristics of Phototransistor 56
2 Design and Verification Of Collector To Base Bias Circuits. 58
 ELECTRONIC DEVICES AND CIRCUITS LABORATORY

Note: The students are required to perform the experiment to obtain the V-I characteristics and to
determine the relevant parameters from the obtained graphs.

Course Objectives:
 To Obtain the V-I Characteristics of PN junction diode,BJT,FET,etc
 To Design amplifier using BJT and FET
 To Understand the working of Rectifier with and without filters
 To Understand the need for Biasing for BJT and Operation of CRO.

Course Outcomes:

After successful completion of this course, the students should be able to

CO1: Understand the basic characteristics of all Semiconductor components like

diodes,BJTs,FETs etc.,

CO2: Measure voltage, frequency and phase of any waveform using CRO and Generate sine,

square and triangular waveforms with required frequency and amplitude using function

generator.

CO3: Design the circuits with basic semiconductor devices (active & passive elements),

measuring instruments & power supplies that serves many practical purposes.

CO4: Construct simple circuits, measure and record the experimental data, analyze the

results, and prepare a report..

PROGRAMME OUTCOMES (PO)

PO1: Engineering knowledge: Apply the knowledge of mathematics, science,
engineering fundamentals, and an engineering specialization to the solution of complex
engineering problems.
PO2: Problem analysis: Identify, formulate, research literature, and analyze
complex engineering problems reaching substantiated conclusions using the first
principles of mathematics, natural sciences, and engineering sciences.
PO3: Design/development of solutions: Design solutions for complex engineering
problems and system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
PO4: Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid conclusions.
 PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
PO6: The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.

PO7: Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
PO8: Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
PO9: Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multi-disciplinary settings.
PO10: Communication: Communicate effectively on complex engineering activities
with the engineering community and with society at large, such as, being able to
comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
PO11: Project management and finance: Demonstrate knowledge and understanding
of the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multi-disciplinary
environments.
PO12: Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context of
technological change.
PSO1: Apply the fundamental concept of Electronincs and communication
Engineering to design a variety of components and systems for applications including
image and signal processing.communication ,networking,embedded systems,VLSI and
control system.
PSO2: select and apply cutting-edge engineering hardware and software tools to solve
complex electronics and communication engineering problems.

CO-PO Mapping
Programme Outcomes
Cos PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO1 3 2 1 1 0 0 0 0 2 2 0 0 2 2
CO2 3 2 1 1 0 0 0 0 2 2 0 0 2 2
CO3 3 2 3 1 0 0 0 0 2 2 0 0 2 2
CO4 3 2 0 1 0 0 0 0 2 2 0 0 2 2

Strengh of correlation:1-Weak,Medium-2 & Strong-3

 INDEX

Sl.No Date Name of the Experiment Page no Marks Signature

 EDC LAB MANUAL

EXPERIMENT-1
P-N JUNCTION DIODE CHARACTERISTICS
DATE:
AIM: To verify the V-I characteristics of P-N junction diode and to calculate the Static and
dynamic resistances at suitable operating points in forward and reverse bias conditions.

EQUIPMENTS:
1. Regulated Power Supply (0-30V)-1No.
2. Volt meter-(0-20V)&(0-2V)-1No.
3.Ammeter-(0-20mA)&(0-750µA)-1No.

ELECTRONIC COMPONENTS:
1. P-N junction diode (1N 4007)-1No.
2. Resistors 1kΩ-1No. 3. Bread Board-1No.
4. Connecting Wires-1 Set.

THEORY:
Forward bias of p-n junction diode:
If an external d.c. voltage is connected in such a way that the p-region terminal is connected to
the positive of the d.c. voltage and the n-region is connected to the negative of the d.c. voltage, the biasing
condition is called forward biasing. The p-n junction is said to be forward biased.
While crossing the junction, the electrons give up the amount of energy equivalent to the barrier
potential.
Forward resistance of a diode:
The forward resistance is defined in two ways:
1. Static Forward Resistance:
Forward d c voltage 𝑂𝐴
RF = = 𝑎𝑡 𝑝𝑜𝑖𝑛𝑡 𝐸
Forward d c current 𝑂𝐶
2. Dynamic Forward Resistance:
The resistance offered by the p-n junction under a.c. conditions is called Dynamic
resistance denoted as rf
∇𝑉 1 1
rf = = ∇𝐼 =
∇𝐼 𝑠𝑙𝑜𝑝𝑒 𝑜𝑓 𝑓𝑎𝑟𝑤𝑎𝑟𝑑 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠
∇𝑉
Reverse bias of p-n junction diode:
If an external d.c. voltage is connected in such a way that the p-region terminal of a p- n junction
is connected to the negative of the battery and the n-region terminal of a p-n junction is connected to the
positive of the battery, the biasing condition is called reverse biasing. The p-n junction is said to be
forward biased.
Reverse resistance of a diode: The p-n junction offers large resistance in the reverse biased condition
called reverse resistance. This is also defined in two ways.
OQ Applied reverse voltage
Rr = =
I0 Reverse sturation current

Reverse dynamic resistance:

This is the reverse resistance under the a.c. conditions, denoted as r r. It is the ratio
of incremental change in the reverse voltage applied to the corresponding change in the
reverse current.

∇𝑉 𝐶ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒

rr = ∇𝐼 R = 𝐶ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝑟𝑒𝑣𝑒𝑟se c𝑢𝑟𝑟𝑒𝑛𝑡
R

1
 EDC LAB MANUAL
Cut –in Voltage:
The voltage at which the diode current starts increasing rapidly is called cut-in
voltage, offset voltage, break-point voltage or threshold voltage. It is denoted by Vγ.
CIRCUIT DIAGRAM:
Forward bias:

Reverse bias:

PROCEDURE:

a) Forward Bias:
1) The circuit is connected as per the circuit Diagram.
2) The forward voltage is increased in steps of 0.1V to 1V and in steps of
1Vfrom 1V to 15V.
3) The readings of the meters (ammeter and voltmeter) are observed for every
value of forward voltage and are tabulated.

b) Reverse Bias:
1) The circuit is connected as per the circuit diagram.
2) The reverse voltage is increased in steps of 1V from 1V to 15 V.
3) The readings of meters (ammeter and voltmeter) are observed for every value
of Reverse voltage and are tabulated.

PRECAUTIONS:
1) Continuity of the wires must be checked.
2) The voltage level in the power supply must be kept in minimum position
before switching it ON and OFF.
3) The polarities of the diode (anode and cathode) are to be identified carefully
2
 EDC LAB MANUAL
before connecting the circuit.
OBSERVATIONS:
Forward bias:

S.NO Applied Voltage(V) Diode Voltage (VD in V) Diode Current(ID in mA)

1. 0
2. 0.1
3. 0.2
4. 0.3
5. 0.4
6. 0.5
7. 0.6
8. 0.7
9. 0.8
10 0.9
11 1.0
12. 2.0
13. 3.0
14. 4.0
15 5.0
16. 6.0
17. 7.0
18. 8.0
19. 9.0
20. 10.0
21. 11.0
22. 12.0
23. 13.0
24. 14.0
25. 15.0

Reverse bias:

S.NO Applied Voltage(v) Diode Voltage(VD in V) Diode Current(ID in µA)

1. 0
2. 1
3. 2
4. 3
5. 4
6. 5
7. 6
8. 7
9. 8
10. 9
11. 10
12. 11
13. 12
14. 13
15. 14
16. 15

MODEL WAVEFORMS:

Forward Bias V-I characteristics

3
 EDC LAB MANUAL

Reverse Bias V-I characteristics

1.The cut in voltage (Vγ) of the diode is found to be V.

2.Static resistance in forward bias at V = VD/ID = Ω.
3. Dynamic resistance in forward bias between V and V =∆VD/∆ID= Ω.
4. Static resistance in reverse bias at V =VD/ID = MΩ.
5. Dynamic resistance in reverse bias between V and V=∆VD/∆ ID= MΩ.

RESULT:

REMARKS:

SIGNATURES OF FACULTY

4
 EDC LAB MANUAL
EXPERIMENT-2

ZENER DIODE CHARACTERISTICS

DATE:

AIM: To verify the V-I characteristics of Zener diode and to calculate the Static and
dynamic resistances at suitable operating points in forward and reverse bias conditions.

EQUIPMENTS:
1. Regulated Power Supply (0-30V) 1No.
2. Volt meter-(0-20V)&(0-2V)-1No.
3.Ammeter-(0-20mA)-1No.

ELECTRONIC COMPONENTS:
1. Zener diode (6Z)-1No.
2. Resistors 1kΩ-1No.
3. Bread Board-1No.
4. Connecting Wires-1 Set.

THEORY:
The zener diode is a silicon p-n junction semiconductor device, which is
generally operated in its reverse breakdown region. The zener diodes have breakdown
voltage range from 3V to 200V.

In the forward biased condition, the normal rectifier diode and the zener diode
operate in similar fashion. But the zener diode is designed to be operated in the reverse
saturation current till the reverse voltage applied is less than the reverse breakdown voltage.
When the reverse voltage exceeds reverse breakdown voltage, the current through it changes
drastically but the voltage across it remains almost constant. Such a breakdown region is a
normal operating region for a zener diode.

When the reverse voltage applied to a zener diode is increased, initially the current
through it is very small, of the order of few μA or less. This is the reverse leakage current of
the diode, denoted by I0. At a certain reverse voltage, current through zener diode increases
rapidly. The change from a low value to large value of current is very sharp and well
defined. Such a sharp change in the reverse characteristics is called knee or zener knee of
the curve. At this knee, a breakdown is said to occur in the device. The reverse bias voltage
at which the breakdown occurs is called Zener breakdown voltage.

From the graph the dynamic resistance is defined as,

∇𝑉z 1 1
r= = ∇𝐼 = 𝑠𝑙𝑜𝑝𝑒 𝑜𝑓 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠 𝑖𝑛
∇𝐼
∇𝑉z 𝑍𝑒𝑛𝑎𝑟 𝑅𝑒𝑔𝑖𝑜𝑛

Breakdown Mechanisms in Zener Diode:

There are two distinct mechanisms due to which breakdown may occur in the zener
diode. One is called zener breakdown and the other avalanche breakdown.
5
 EDC LAB MANUAL

CIRCUIT DIAGRAM:

Forward Bias:

Reverse Bias:

PROCEDURE:

a) Forward Bias:
1) The circuit is connected as per the circuit Diagram.
2) The forward voltage is increased in steps of 0.1V to 1V and in steps of
1Vfrom 1V to 15V.
3) The readings of the meters (ammeter and volt meter) are observed for every
value of forward voltage and are tabulated.

b) Reverse Bias:
1) The circuit is connected as per the circuit diagram.
2) The reverse voltage is increased in steps of 1V from 1V to 15 V.
3) The readings of meters (ammeter and voltmeter) are observed for every value
of Reverse voltage and are tabulated.
c) Regulation characteristics:-
6
 EDC LAB MANUAL
1. Connections are made as per the circuit diagram
2. The load resistance is fixed to known value and the zener voltage (Vz), and Zener current
(lz), are measured.
3. The load resistence is varied in steps and the corresponding values are noted down for each load
resistance value.
4. All the readings are tabulated.

PRECAUTIONS:
1) Continuity of the wires must be checked.
2) The voltage level in the power supply must be kept in minimum position
before switching it ON and OFF.
3) The polarities of the diode (anode and cathode) are to be identified
carefully before connecting the circuit.
OBSERVATIONS:
Forward Bias:
S.NO Applied Voltage (V) Diode Voltage (VD) in V Diode Current (ID) in mA
1 0.1
2 0.2
3 0.3
4 0.4
5 0.5
6 0.6
7 0.7
8 0.8
9 0.9
10 1.0
11 2.0
12 3.0
13 4.0
14 5.0
15 6.0
16 7.0
17 8.0
18 9.0
19 10.0
20 11.0
21 12.0
22 13.0
23 14.0
24 15.0

Reverse Bias:

S.NO Applied Voltage (V) Diode Voltage (VD) in V Diode Current (ID ) in mA
1 1.0
2 2.0
3 3.0
4 4.0
5 5.0
6 6.0
7 7.0
8 8.0
9 9.0
7
 EDC LAB MANUAL
10 10.0
11 11.0
12 12.0
13 13.0
14 14.0
15 15.0

Regulation characteristics:-

SL.No V (Volts) IR1 (Amperes) RL(Ω)

1
2

MODEL WAVEFORMS:

Forward Bias V-I characteristics

Reverse Bias V-I characteristics:

8
 EDC LAB MANUAL

Regulation Characteristics

1. Static resistance in forward bias at V= VD/ID= Ω.

2. Dynamic resistance in forward bias between _V and V =∆VD/∆ID= Ω.
3. Static resistance in reverse bias at V =VD/ID = KΩ.
4. Dynamic resistance in reverse bias between _V and V=∆VD/∆ ID = KΩ.

RESULT:

REMARKS:

SIGNATURE OF FACULTY

9
 EDC LAB MANUAL

EXPERIMENT-3

RECTIFIERS (WITHOUT AND WITH C-FILTER)

DATE:

AIM: To study the characteristics and performance of Half Wave Rectifier and Full Wave
Rectifier with and without filter.

EQUIPMENTS:
1. Cathode Ray Oscilloscope (1 MHz) - 1No.
2. 9-0-9 V Center tapped step down transformer-1No.
3. Multemeters-2No.

ELECTRONIC COMPONENTS:
1. P-N junction diode -2No.
2. Resistors 1kΩ-1No,3.3kΩ , 5.6kΩ-1No,22kΩ-1No,100kΩ-1No.
3. Capacitors 100µf-1No.
4. Bread Board-1No.
5. CRO probes-2No.
6. Connecting Wires-1 Set.

THEORY:

A rectifier is a device which converts a.c. voltage to pulsating d.c. voltage, using one
or more p-n junction diodes.

Half Wave Rectifier:

The p-n junction diode conducts only in one direction. It conducts when forward
biased while practically it does not conduct when reverse biased. Thus if an alternating
voltage is applied across a p-n junction diode, during positive half cycle the diode will be
forward biased and will conduct successfully. While during the negative half cycle it will be
reversed biased and will not conduct at all. Thus the conduction occurs only during positive
half cycle.

Rectifier Efficiency: It signifies, how efficiently the rectifier circuit converts a.c. power
into d.c. power.

Ripple factor: The output of the rectifier is of pulsating d.c. type. The amount of a.c.
content in the output can be mathematically expressed by a factor called ripple factor. Less
is the ripple factor, better is the performance of the circuit.

Im
I DC   average value


𝐼𝑚
IRMS = 2

10
 EDC LAB MANUAL

𝑅.𝑀.𝑆 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝐴.𝐶 𝑐𝑜𝑚𝑝𝑜𝑛𝑒𝑛𝑡 𝑜𝑓 𝑜𝑢𝑡𝑝𝑢𝑡 𝐼 2

Ripple Factor  = = √( 𝐼𝑅𝑀𝑆 ) − 1
𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑜𝑟 𝐷.𝐶 𝐶𝑜𝑚𝑝𝑜𝑛𝑒𝑛𝑡 𝑜𝑓 𝑜𝑢𝑡𝑝𝑢𝑡 𝐷𝐶

Full Wave Rectifier:

The full wave rectifier conducts during both positive and negative half cycles of input
a.c. supply. In order to rectify both the half cycles of a.c. input, two diodes are used in this
circuit. The diodes feed a common load RL with the help of a center tap transformer. The
a.c. voltage is applied through a suitable power transformer with proper turns ratio.

It is noted that the load current flows in both the half cycle of ac voltage and in the
same direction through the load resistance.
Ripple Factor( )
As derived earlier in case of half wave rectifier the ripple factor is given by a general
expression,
𝐼𝑅𝑀𝑆 2
√( ) −1
𝐼𝐷𝐶
𝐼𝑚 2𝐼𝑚
For full wave IRMS = and IDC = so,
√2 𝜋
Substituting in the above equation , 

This indicates that the ripple contents in the output are 48% of the d.c. component

which is much less than that for the half wave circuit

CIRCUIT DIAGRAM:

Half Wave Rectifier Without Filter:

Full Wave Rectifier Without Filter:

11
 EDC LAB MANUAL
Full Wave Rectifier With Filter:

PROCEDURE:

a) HWR WITHOUT FILTERS:

1) The circuit is connected as per the circuit Diagram.
2) The readings of ammeter and voltmeter are taken with the switch in both ac and dc
modes for IRMS RRMS IRMS and VDC.
3) Ripple factor is calculated by the formula:
γ =Vrm/V dc from the readings obtained. Observed for every value of
1) Step 2 is repeated for various values of load resistors.
b) HWR WITH FILTER
1) The circuit is connected as per the circuit Diagram.
2) The readings of ammeter and voltmeter are taken with the switch in both ac and dc
modes for Irms , vrms, Idc and Vdc..
3)Ripple factor is calculated by the formula:
γ =Vrms /V dc from the readings obtained. Observed for every value of
4) The values of ripple factor obtained practically are verified with the theoretical value given
𝟏
by: 𝟐√𝟑 𝒇𝑪 𝑹
𝑳

c) FWR WITHOUT FILTERS:

1) The circuit is connected as per the circuit Diagram.
2) The readings of ammeter and voltmeter are taken with the switch in both ac and dc
modes for Irms, vrms, Idc and Vdc.
3) Ripple factor is calculated by the formula:
γ =Vrm/V dc from the readings obtained. Observed for every value of Step 2 is repeated
for various values of load resistors.
d) FWR WITH FILTER :
1) The circuit is connected as per the circuit Diagram.
2) The readings of ammeter and voltmeter are taken with the switch in both ac and dc
12
 EDC LAB MANUAL

modes For IrmsvrmsIdcand Vdc.

3) Ripple factor is calculated by the formula:
γ = Vrms/V dc from the readings obtained. Observed for every value of the values of ripple
factor obtained practically are verified with the theoretical value given by the formula
𝟏
𝟒√𝟑 𝒇𝑪 𝑹 
𝑳
PRECAUTIONS:
1. The continuity of wires and C.R.O. probes must be checked.
2. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
3. The terminals of the transistor should be identified properly.
4. Readings should be taken without errors.
5. Interconnections should not be made on the bread board with power switched on.
OBSERVATIONS:
Half wave Rectifier without filter:-

S. No. RL(Ω) I DC (mA) VDC(volts) I rms (mA) V rms γ=

(volts) Vrms/VDC
1
2
3
4
5

Half wave Rectifier with filter:-

S. RL(Ω) I DC VDC(volts) I rms (mA) V rms γ= γ=

No. (mA) (volts) Vrms/VDC 1/2√3fCRL
1
2
3
4
5

Full wave Rectifier Without filter:-

S. No. RL(Ω) I DC (mA) VDC(volts) I rms (mA) V rms(volts) γ=

Vrms/VDC
1.
2.
3.
4.
5.

Full wave Rectifier with filter:-

S. RL(Ω) I DC VDC(volts) I rms (mA) V rms γ= γ=

No. (mA) (volts) Vrms/VDC 1/4√3fCRL
1.
2.
3.

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 EDC LAB MANUAL
4.
5.

MODEL WAVEFORMS:

Half Wave Rectifier Full Wave Rectifier:

The performance of Half wave rectifier is observed and its input and output waveforms
are observed

Theoretical value:
The ripple factor of HWR (γ) without filter =
1.21 The ripple factor of HWR (γ) with filter =
0.0296 Practical value:
The ripple factor of HWR (γ) without filter =
The ripple factor of HWR (γ) with filter =

The performance of Full Wave Rectifier is observed and its input and output waveforms
are observed
Theoretical value:
The ripple factor of HWR (γ) without filter =
0.48 The ripple factor of HWR (γ) with filter =
0.0234 Practical value:
The ripple factor of HWR (γ) without filter =
The ripple factor of HWR (γ) with filter =

14
 EDC LAB MANUAL
RESULT:

REMARKS:

SIGNATURE OF THE FACULTY

15
 EDC LAB MANUAL
EXPERIMENT-4

BJT CHARACTERISTICS(CE CONFIGURATION)

DATE

AIM: To obtain the input and output characteristics of a given transistor in CE

configuration.

EQUIPMENTS:

1. Regulated Power Supply (0-30V)- 1No

2.Volt meter-(0-20V) & (0-2V)-1No
3.Ammeter (0-20mA) & (0-750µA)-1No

ELECTRONIC COMPONENTS:
1. Transistor BC107-1No.
2. Resistors 100kΩ-1No, 1kΩ-1No.
3. Bread Board-1No.
4. Connecting Wires-1 Set.

THEORY:
If transistor is connected so that the emitter of the transistor is common to input as
well as the output, the configuration termed as common emitter configuration. In this
configuration the input is given between the base and emitter whereas output is obtained
between collector and emitter. Operation of a transistor in the active region is ensured by
forward biasing of the emitter-base junction and reverse biasing of the collector-base
junction

Input Characteristics:
It is the curve of input current versus input voltage for a given output voltage.
The input characteristic for a CE configuration should be a curve of VBE versus IB for a
given value of VCE . For different values of VCE we can get different input characteristics
Ri = ∆VBE/IB at VCE constant.

Output characteristics:
It is the curve of output voltage versus output current for a given input current.
The output characteristics for a CE configuration should be a curve of V CE versus IC for a
given value of IB .For different values of IB we can get different output characteristics.

Ro = ∆VCE/IC at IB constant
βDC = IC/IB at constant VCE
βAC = ∆IC/∆IB at constant VCE
CIRCUIT DIAGRAM:

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 EDC LAB MANUAL

PROCEDURE:

PROCEDURE:-

1. The circuit is connected as per the circuit diagram.

2. For the input characteristics Output Voltage VCE kept constant and by varying VBE in
steps the I/P Current IB is noted.
3. For Output characteristics I/P Current I B is kept constant at particular value and
for different values of VCE , O/P Current IC is noted.
4. Graphs are plotted for both I/P and O/P values.

PRECAUTIONS:

1. The continuity of wires must be checked.

2. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
3. The terminals of the transistor should be identified properly.
4. Readings should be taken without errors.
5. Interconnections should not be made on the bread board with power switched on.

17
 EDC LAB MANUAL
OBSERVATION:
INPUT CHARACTERISTICS:

VCE = 0 volt VCE = 2 volt VCE =4 volt

S. No. VBB(v)
VBE(v) IB (µA) VBE (v) IB (µA) VBE(v) IB (µA)
1. 0.0
2. 0.1
3. 0.2
4. 0.3
5. 0.4
6. 0.5
7. 0.6
8. 0.7
9. 0.8
10. 0.9
11. 1.0
12. 2.0
13. 3.0
14. 4.0
15. 5.0
16. 6.0
17. 7.0
18. 8.0
19. 9.0
20. 10.0
21. 11.0
22. 12.0
23. 13.0
24. 14.0
25. 15.0

OUTPUT CHARACTERISTICS:

IB = 10 µA IE= 20µA IE = 30 µA
S. No. VCC(v)
VCE(v) IC (mA) VCE (v) IC (mA) VCE(v) IC (mA)
1. 0
2. 1.0
3. 2.0
4. 3.0
5. 4.0
6. 5.0
7. 6.0
8. 7.0
9. 8.0
10. 9.0
11. 10.0
12. 11.0
13. 12.0
14. 13.0

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 EDC LAB MANUAL
MODEL WAVEFORMS:

Input Characteristics:

Output Characteristics:

RESULT:

REMARKS:

SIGNATURE OF THE FACULTY:

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 EDC LAB MANUAL

EXPERIMENT-5

FET CHARACTERISTICS(CS CONFIGURATION)

DATE

AIM: To obtain the transfer and drain characteristics of a given FET configuration.

EQUIPMENTS:

1. Regulated Power Supply (0-30V)- 1No

2.Volt meter-(0-20V) & (0-2V)-1No
3.Ammeter (0-20mA) & (0-750µA)-1No

ELECTRONIC COMPONENTS:
1. FET (Field Effect Transistor) – BFW – 11-1No.
2. Resistors 100kΩ-1No, 680Ω-1No.
3. Bread Board-1No.
4. Connecting Wires-1 Set.

THEORY:
FET is a three terminal, unipolar device i.e, source, drain and gate. FET, the operation
depends upon the flow of majority charge carriers only. FETs have high input impedance,
High power gain. JFET can be either n-channel or p- channel. From the construction point
of View an n- channel JFET consists of bar of N-type silicon and heavily doped P-type
regions on either side of the bar. The bar acts as resistor between its two ends known as
source and drain. The heavily doped p-regions are called gates. Two gates are connected
together. The gate controls the the current flow from source to drain. The terminals source
and drain are interchangeable.

Static Drain Characteristics:

It is a curve between the drain current ID and to drain to source voltage V DS for a
given value of gate –source voltage VGS.
Pinch- Off Voltage: The value of VDS at which ID becomes essentially constant for VGS
=0V is known as Pinch- Off voltage (Vp) for a given FET, Vp has a fixed value. A
continuous increase VDS above the pinch-off voltage produces an almost constant drain
current.
A break down occurs when ID begins to increase very rapidly, with any further
increase in VDS break down can result in permanent damage to device, so JFETs should be
operated below breakdown within the constant current area.V GS controls ID.
Drain dynamic resistance rds= ∆VDS/∆ID at constant VGS

Transfer Characteristics:
It is a curve between VGS and ID fpr a given value of VDS.
Forward transfer admittance or mutual conductance=gm = ∆ID/∆VGS at a constant value
of VDS

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 EDC LAB MANUAL

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.

2. Connect the signal generator output to input terminals of the circuit and CH-I of dual
trace CRO.
3. Connect the output terminal of the circuit CH-II of the dual trace CRO.
4. Set the power supply voltage to 22V and connect to the circuit.
5. Set the signal generator output, sine wave of 20mV 1kHz is applied to input terminal
of circuit diagram.
6. By making input voltage as constant, vary the function generator frequency from
100 Hz to 1MHz (as per in the given tabular form) and note down the corresponding
output voltages.
7. Calculation the gain AV =Vo/Vi .
8. Plot the graph frequency V s gain (dB) on a semi log sheet.
9. And finally calculate the maximum gain and bandwidth from graph.

PRECAUTIONS:
1. The continuity of wires and C.R.O. probes must be checked.
2. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
3. The terminals of the transistor should be identified properly.
4. Readings should be taken without errors.
5. Interconnections should not be made on the bread board with power switched on.

OBSERVATIONS:
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 EDC LAB MANUAL

STATIC DRAIN CHARACTERISTICS:

VGS = 0 V VGS= -1V VGS = -2 V

S. No. VDD(v)
VDS(v) ID (mA) VDS (v) ID(mA) VDS (v) ID(mA)
1. 0
2. 1
3. 2
4. 3
5. 4
6. 5
7. 6
8. 7
9. 8
10. 9
11. 10

TRANSFER CHARACTERISTICS:

VDS = 2V VDS= 4V VDS = 6 V

S. No. VGG(v)
VGS(v) ID (mA) VGS (v) ID(mA) VGS (v) ID(mA)
1. 0
2. 0.1
3. 0.2
4. 0.3
5. 0.4
6. 0.5
7. 0.7
8. 1.0
9. 0.5
10. 2.0
11. 2.5

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 EDC LAB MANUAL
MODEL WAVEFORMS:

Drain Characteristics Transfer Characteristics

RESULT:

REMARKS:

SIGNATURE OF THE FACULTY

23
 EDC LAB MANUAL

EXPERIMENT-6
SCR CHARACTERISTICS
DATE:

AIM: To study and plot the V-I characteristics of a Silicon controlled rectifier.

EQUIPMENTS:
1. Regulated Power Supply (0-30V)-1No.
2. Volt meter-(0-20V) -1No.
3.Ammeter-(0-20)mA-2No.

ELECTRONIC COMPONENTS:
1. SCR -TYN604-1No.
2. Resistors 1kΩ-2No.
3. Bread Board-1No.
4. Connecting Wires-1 Set.

THEORY:
SCR is a three terminal junction 4 layer (PNPN) semiconductor device. It performs various
function like rectification, inversion and regulation of power flow in a load. It performs
conducts the power in directional (just like diode).
The SCR has appeared in the masked names under different names such as thyristar,
thyroid and transistor TYN604, CN106 AND C22F are some of the SCR’s available in the
marked.
An SCR has two states that us either it does not conductor or it conduct heavily. There
is no state in between. Therefore SCR behaves like a switch.
There are two ways to turn on SCR. The first method is to make gate terminal open
and make the supply voltage equal to break over voltage. The second method is to operate
SCR with supply voltage. The second method is to operate SCR with supply voltage. Then
the SCR switches ‘ON’ and will not switch ‘OFF’ until the anode cathode Y AK is removed.
Hence the name of silicon rectifier.
1. Breakdown over voltage: it is the minimum forward voltage gate being open at which
SCR starts conducting heavily, that is SCR turn ON.
2. Holding current: it is minimum anode current, gate being opened at which SCR is
turned ‘OFF’.
3. Triggering current: when the supply voltage is less than the applying the gate current,
this minimum value of gate current is known as triggering current.
4. Forward current rating: It is maximum anode current that an SCR is capable of
passing without destruction.

V-I Characteristics of SCR:

It is the curve between the anode cathode voltage (v) and anode current(I) of an SCR
at constant gate current(I) of an SCR. The curve between V-I is called forward characteristic
curve at IC1=0. If the supply voltage is increased from 0, a point is reached when SCR starts
conducting under this condition, voltage across SCR suddenly drops. When anode is made
negative with respect to cathode the curve between V-I characteristics is known as gradually

24
 EDC LAB MANUAL
increased at first the anode current reains small and ar some reverse voltage, avalanche
breakdown occurs and SCR starts conducting heavily in the reverse direction.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the circuit as per circuit diagram.

2. Set VAK = 10v and vary VG till VAK drop suddenly. Note IG.
3. Set IG equal to firing current VAK in steps of 1v and note IA.
4. Note the voltage (VBO) where VAK suddenly drops and IA increases and note
IA, it is nothing but latching current(ILA = Imax).
5. Increase VAK in steps of 1v to its maximum.
6. Decrease VAK after gate is opened.
7. Note holding current that is the reading of ammeter (I A) at which suddenly
reduces to zero.
8. Tabulate the results.

PRECAUTIONS:
1. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
2. The terminals of the transistor should be identified properly.
3. Readings should be taken without errors.
4. Interconnections should not be made on the bread board with power switched on.

25
 EDC LAB MANUAL
OBSERVATIONS:

VAK = 10 v, VAK = 15 v,
S. No. IG = 6.5mA IG = 6.3 mA
VA(v) IA (mA) VA (v) IA (mA)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.

MODEL WAVEFORMS:

26
 EDC LAB MANUAL
RESULT:

REMARKS:

SIGNATURE OF THE FACULTY

27
 EDC LAB MANUAL

EXPERIMENT-7

UJT CHARACTERISTICS
AIM: To obtain the static emitter characteristics of a given UJT.

EQUIPMENTS:
1. Regulated Power Supply (0-30V)-1No.
2. Volt meter-(0-20V)&(0-2V)-1No
3.Ammeter-(0-20)mA-1No.

ELECTRONIC COMPONENTS:
1. UJT-2N2646-1No.
2. Resistors 1kΩ-2No.
3. Bread Board-1No.
4. Connecting Wires-1 Set.

THEORY:

A Unijunction Transistor (UJT) is an electronic semiconductor device that has only one
junction. The UJT Unijunction Transistor (UJT) has three terminals an emitter (E) and two
bases (B1 and B2). The base is formed by lightly doped n-type bar of silicon. Two ohmic
contacts B1 and B2 are attached at its ends. The emitter is of p-type and it is heavily doped.
The resistance between B1 and B2, when the emitter is open-circuit is called interbase
resistance.The original unijunction transistor, or UJT, is a simple device that is essentially a
bar of N type semiconductor material into which P type material has been diffused
somewhere along its length. The 2N2646 is the most commonly used version of the UJT. The
UJT is biased with a positive voltage between the two bases. This causes a potential drop
along the length of the device. When the emitter voltage is driven approximately one diode
voltage above the voltage at the point where the P diffusion (emitter) is, current will begin to
flow from the emitter into the base region. Because the base region is very lightly doped, the
additional current (actually charges in the base region) causes (conductivity modulation)
which reduces the resistance of the portion of the base between the emitter junction and the
B2 terminal. This reduction in resistance means that the emitter junction is more forward
biased, and so even more current is injected. Overall, the effect is a negative resistance at the
emitter terminal. This is what makes the UJT useful, especially in simple oscillator
circuits.When the emitter voltage reaches Vp, the current starts to increase and the emitter
voltage starts to decrease.This is represented by negative slope of the characteristics which is
reffered to as the negative resistance region,beyond the valleypoint ,RB1 reaches minimum
value and this region,VEB propotional to IE.

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 EDC LAB MANUAL

CIRCUIT DIAGRAM:

PROCEDURE:

1) The circuit is connected as per the circuit diagram.

2) For static emitter characteristics, voltage (VBB) is kept constant and by varying the emitter
voltage ( VEE ) in steps, the voltage (VEB) and current (IE) is noted.
3) Graphs are plotted for both static emitter characteristics. Which makes it useful as an
oscillator.

PRECAUTIONS:
1. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
2. The terminals of the transistor should be identified properly.
3. Readings should be taken without errors.
4. Interconnections should not be made on the bread board with power switched on.

OBSERVATIONS:

VBB =5V VBB =10V

S.NO VEB(V) IE(mA) VE(V) VEB(V) IE(mA)
VE(V)

1. 0 0

2. 0.3 0.3

3. 0.5 0.5

4. 1 1

5. 2 2

6. 3 3

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 EDC LAB MANUAL

7. 4 4

8. 5 5

6
9. 6
7

10. 7 8

9
11. 8
10

12. 9 11

12
14. 10
13

15. 11 14

15
16. 12

17. 13

18 14

19. 15
MODEL WAVEFORMS:

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 EDC LAB MANUAL

RESULT:

REMARKS:

SIGNATURE OF THE FACULTY

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 EDC LAB MANUAL

EXPERIMENT-8

TRANSISTOR BIASING
DATE:

AIM: To design a fixed bias circuit and observe stability by changing β of the given
transistor in CE configuration.

EQUIPMENTS:

1. Regulated Power Supply (0-30V)-1No.

2. Volt meter-(0-20V)&(0-2V)-1No
3.Ammeter-(0-20)mA-1No.

ELECTRONIC COMPONENTS:

1. Transistor BC107-1No.
2. Resistors 50Ω,80 Ω -1No, 30kΩ,49 kΩ -1No.
3. Bread Board-1No.
4. Connecting Wires-1 Set.

THEORY:
The Bipolar Junction Transistor (BJT) is a nonlinear three terminal device with following dc
models:
a) Cutoff mode: VBE< VF, IB=0, IC=0.

b) Active mode: VBE≥VF, VCE≥VCESAT, IC=ßFIB+ICEO(ICEO is usually negligibly small)

c)Saturation mode: VBE≥VF, VCE=VCESAT, IC< ßFIB IC is determined by the external circuit.

c) In analog circuits, the BJT is operated in the active mode. For this purpose a biasing circuit
is employed. Figure (2) has various biasing circuits that use only one power supply.
d)
e) The bias circuit without feedback is the simplest of all: The base current of the BJT is set
by the resistor RB. In the design ,RB is set to be (VCC-VBE)/IB.
f) For the emitter feedback bias circuit, the resistor RE causes negative feedback and reduces
the changes in the operating point.

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 EDC LAB MANUAL
g) In the collector feedback bias circuit, the resistor RC has essentially the same effect as the
RE in the emitter feedback bias circuit.
h)
i) The operating point of a transistor in a circuit depends not only on the voltage sources and
resistors, but also on VF, ßF and ICO of the transistor. The BJT parameters may vary due to
production line spread or temperature. As the variation of these parameters will affect the
operating point, the stability of the operating point should be considered during the bias
circuit design. To observe this variation, the following stability factors should
be investigated:

CIRCUIT DIAGRAM:

PROCEDURE:

1. Assemble the circuit on breadboard with design values of RC, RB and β.

2. Apply VCC and measure VCE and VBE and record the readings in the table.
3. Without changing bias resistors, change the transistors with other β values and repeat
the above step.
4. Repeat the above steps using the collector to base bias circuit and tabulate all
the readings.

PRECAUTIONS:
1. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
2. The terminals of the transistor should be identified properly.
3. Readings should be taken without errors.
4. Interconnections should not be made on the bread board with power switched on.

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 EDC LAB MANUAL

OBSERVATIONS:
FIXED BIASING:

Design Combination of Value Observed Stability Factor

Values Condition
RC RB VCC IC VCE IC VCE β

CALCULATIONS:

Fixed Bias Circuit:

1. Given VCC = 10V, IC = 100mA, VBE = 0.7V, β = 317

IC = IB / β
RB = (VCC-
VBE)/IB RC =
(VCC-VCE)/IC
VCE= VCC/2=10/2=5V

IB= IC/ β = 100Ma/317= 0.317Ma

RC = (VCC-VCE)/IC RB = (VCC-VBE)/IB

2. Given VCC = 12V, IC = 75mA, VBE = 0.7V, β = 317

IC = IB / β
VCE= VCC/2=12/2=6V
IB= IC/ β = 75Ma/317= 0.23Ma
RC = (VCC-VCE)/IC RB = (VCC-VBE)/IB

RESULT:

REMARKS:

SIGNATURE OF THE FACULTY

34
 EDC LAB MANUAL

EXPERIMENT-9

CRO OPERATION AND ITS MEASUREMENTS

DATE:
AIM: To study the operation and applications of Cathode Ray Oscilloscope.

EQUIPMENTS:

1. Regulated Power Supply (0-30V)-1No.

2. Volt meter-(0-20V) & (0-2V)-1No.
3. Fuction Generator (100-1MHz)-1No.
4. Cathode Ray Oscilloscope (10-2MHz)-1No.

ELECTRONIC COMPONENTS:
1 Resistor 1kΩ -1No.
2. Capacitor 1µF-1No.
3. Bread Board-1No.
4. Connecting Wires-1 Set.

THEORY:

BLOCK DIAGRAM OF CATHODE RAY OSCILLOSCOPE

An oscilloscope is a measuring device used commonly for measurement of voltage,

current, frequency, phase difference and time intervals. The heart of the oscilloscope is the
cathode ray tube, which generates the electron beam, accelerates the beam to high velocity,
deflects the beam to create the image, and contains the phosphor screen where the electron
beam eventually becomes visible. To accomplish these tasks, various electrical signals and
35
 EDC LAB MANUAL

voltages are required. The power supply block provides the voltages required by the cathode
ray tube to generate and accelerate the electron beam, as well as to supply the required
operating voltages for the other circuits of the oscilloscope. Relatively high voltages are
required by the cathode tubes, on the order of a few thousand volts, for acceleration, as well
as a low voltage for the heater of the electron gun, which emits the electrons. Supply voltages
for the other circuits are various values usually not more than few hundred volts.
The oscilloscope has a time base, which generates the correct voltage to supply the cathode ray
tube to deflect this part at a constant time dependent rate. The signal to be view isfed to you
vertical amplifier, which increases the potential of the input signal to a level that will provide a
usable deflection of the electron beam. To synchronize the horizontal deflection the vertical
input, such that the horizontal deflection starts at the same point of the input vertical signal
each time it sweeps, a synchronizing or triggering circuit is used. This circuit is the link
between the vertical input and the horizontal time base.

CIRCUIT DIAGRAM:

VOLTAGE AND CURRENT MEASUREMENT:

PHASE MEASUREMENT USING LISSAJOUS PATTERNS (X-Y MODE):

PROCEDURE:

1. Select the sine output of the signal generator, set at 1 KHz

2. Feed the signal to the vertical input of CRO.

36
 EDC LAB MANUAL

3. Adjust level and time base to get one or two cycles of the sine signal on the oscilloscope,
and Calculate the vertical scale.
4.Count the number of vertical divisions N on the scope and find peak-peak level.
Vpp = NV X (Volts/Division)
Calculate Vrms as Vpp / 2 Square root of 2
5. Measure the signal with an AC milli voltmeter as well. It gives the rms value of the signal.
6. Measure the Time period ‘T’ of the signal by counting the number of horizontal
divisions NH covering the span of one cycle. T = N H X (Time/Division)
7. Calculate the frequency as f = 1/T.
8.Apply DC voltage from the regulated power supply and measure the DC level on the
scope.
PRECAUTIONS:

1. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
2. The terminals of the transistor should be identified properly.
3. Readings should be taken without errors.
4. Interconnections should not be made on the bread board with power switched on.

OBSERVATIONS:

1. AC VOLTAGE & FREQUENCY MEASUREMENT:

S.No CRO Reading

Input Signal Peak-to-Peak Time Vrms = Frequency
Frequency(Hz) Amplitude(V) Period(ms) f=1/T(Hz)
Vpp /2√𝟐

2. DC VOLTAGE & DC CURRENT MEASUREMENT:

S.No DC Input CRO Reading DC Current

Voltage (V) Idc = Vdc/R(A)

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 EDC LAB MANUAL

3. PHASE MEASUREMENT USING LISSAJOUS PATTERN:

s.No Lissajous Pattern Practical Phase Theoretical Phase
Difference ( Φ) Difference(θ)

CALCULATIONS:

1)Calculate current as I = V/R.

2)Calculate Phase angle(Practical) :

Calculate the phase angle as Sine Ø = A/B

A: Distance between the points where the ellipse crosses the y-axis and the origin.
B: Distance between the origin and the y – co-ordinate of the maxima of the ellipse.

Calculate theoretical phase difference as θ = tan-1 (f1/f2).

Where f 2 = 1/ (2ΠRC)
f1 = input signal frequency

RESULT:

REMARKS:

SIGNATURE OF THE FACULTY

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 EDC LAB MANUAL

EXPERIMENT-10

BJT CE AMPLIFIER
DATE:

AIM: To obtain the frequency response of the Common Emitter BJT Amplifier and
calculate the Voltage gain and Bandwidth of CE amplifier.

EQUIPMENTS:
1. Regulated Power Supply (0-30V)-1No.
2. Function Generator(10-1MHz)-1No
3. Cathode Ray Oscilloscope (10-2MHz)-1No.

ELECTRONIC COMPONENTS:
1. Transistor BC107-1No.
2. Resistors 22KΩ, 3.3KΩ, 5.6KΩ-1No, 1 KΩ - 2 No.
3. Capacitors -47µf-1No, 10µf – 2No.
4. Bread Board-1No.
5. CRO probes-2No.
5. Connecting Wires-1 Set.

THEORY:
Amplification is the process of increasing the amplitude of the electronic signal
maintaining its original wave shape, The device performing this function is known as
amplifier. A transistor biased in its active region can work as an amplifier, the CE mode a
transistor can work as an amplifier if a.c. voltage is applied between base and emitter
terminals. If the amplitude of the input signal is small and fluctuations in the collector
current are also small compared to its quiescent values, the amplifier is termed as a small
signal amplifier or voltage amplifier.

In the circuit, the capacitor CC is termed as blocking capacitor because it allows a.c.
current and blocks d.c. current from passing through it. The emitter side this circuit consists
of a parallel combination of resistance RE and capacitance CE, centered as a bypass capacitor
as it bypasses all the a.c. current to ground. As a result the resistance RE is more effective.
The net effect of RE is to provide a negative feedback (reduce noise). It reduces the gain of
the amplifier.

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 EDC LAB MANUAL

CIRCUIT DIAGRAM:

PROCEDURE:

 The circuit is connected as per the circuit diagram.

 A Sinusoidal input of 20 mv peak to peak is applied at 1K Hz frequency from Function
Generator and O/P waveform is observed on the C.R.O.
 The Output Voltage VO is directly read from the C.R.O. screen.
 The frequency of the I/P signal is changed in steps and the individual O/P voltages are
noted down from the C.R.O.
 A Graph is plotted between 20 log VO/VI and frequency.

PRECAUTIONS:
1. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
2. The terminals of the transistor should be identified properly.
3. Readings should be taken without errors.
4. Interconnections should not be made on the bread board with power switched on.

40
 EDC LAB MANUAL

OBSERVATIONS:

VIN = 20 mv at 1 KHz

S. NO. Frequency VOUT (volt) A = Vout/VIN Gain= 20 log Vout/VIN (db)

1. 20Hz
2. 50 Hz
3. 100 Hz
4. 200 Hz
5. 500 Hz
6. 1KHz
7. 2 KHz
8. 5 KHz
9. 10 KHz
10. 20 KHz
11. 50 KHz
12. 100 KHz
13. 200 KHz
14. 500 KHz
15. 1MHz

MODEL GRAPHS:

Frequency Spectrum Input and Ouput Signals

CALCULATIONS:

1) Calculate the Voltage Gain by using the formula Av== Output voltage (V0) / Input voltage (Vs).

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Voltage Gain in dB = 20log(Av).

2) The Bandwidth of the amplifier is calculated from the graph using the expression,
Bandwidth, BW=f2-f1
Where f1 is lower 3-dB frequency
f2 is upper 3-dB frequency

RESULT:

The Voltage gain and Bandwidth of CE amplifier is measured and

the frequency response of the CE Amplifier is obtained.
1. The Voltage gain of CE Amplifier is .
2. The Bandwidth of CE Amplifier is .

REMARKS:

SIGNATURE OF THE FACULTY

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 EDC LAB MANUAL

EXPERIMENT-11

EMITTER FOLLOWER-CC AMPLIFIER

DATE:

AIM: To obtain the frequency response of Emitter Follower-CC amplifier .

EQUIPMENTS:

1. Regulated Power Supply (0-30V)-1No.

2. Function Generator(10-1MHz)-1No
3. Cathode Ray Oscilloscope (10-2MHz)-1No.

ELECTRONIC COMPONENTS:
1. Transistor BC107-1No.
2. Resistors 22KΩ-1No,5.6KΩ-1No, 1 KΩ - 2 No.
3. Capacitors -10µf – 2No.
4. Bread Board-1No.
5. CRO probes-2No.
5. Connecting Wires-1 Set.

THEORY:
The biasing arrangement used is potential divider biasing. No collector resistance has been
used, i.e. the collector of the transistor has been connected to the supply directly. In the
emitter circuit an emitter resistance, RE has been connected, but without any by pass
capacitor. This results in negative feedback. Coupling capacitor have been used on the Input
as well as on output side.

When Vi goes positive, the forward bias, Vb increases resulting in an increase the
emitter voltage. Since Ve = Vb-VBE and VBE remain constant effectively. This means that
output voltage is almost the same its input voltage. This means that output voltage at the
emitter terminal follows the input signal applied to the base terminal. This justifies the name
(emitter follower) given to this circuit.

The voltage gain of this amplifier is little less than unity. The input impedance of this
circuit is very high. The output impedance is very low. This circuit is used for impedance
matching. It is used as last stage of measuring instruments and signal generators. This circuit
is capable of delivering power to a load without requiring much power at the input.
Therefore, it can be used as a buffer stage of an amplifier.

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PROCEDURE:

1. The circuit is connected as per the circuit diagram.

2. A Sinusoidal input of 1 v peak to peak is applied at 1K Hz frequency from

Function Generator and O/P waveform is observed on the C.R.O.

3. The Output Voltage VO is directly read from the C.R.O. screen .

4. The frequency of the I/P signal is changed in steps and the individual O/P
voltages are noted down from the C.R.O.

A Graph is plotted between 20 log VO/VI and frequency

PRECAUTIONS:
1. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
2. The terminals of the transistor should be identified properly.
3. Readings should be taken without errors.
4. Interconnections should not be made on the bread board with power switched on.

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OBSERVATIONS:
VIN = 1V at 1 KHz

S. NO. Frequency VOUT (volt) A = Vout/VIN Gain= 20 log Vout/VIN (db)

1. 20Hz
2. 50 Hz
3. 100 Hz
4. 200 Hz
5. 500 Hz
6. 1KHz
7. 2 KHz
8. 5 KHz
9. 10 KHz
10. 20 KHz
11. 50 KHz
12. 100 KHz
13. 200 KHz
14. 500 KHz
15. 1MHz

MODEL GRAPHS:

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 EDC LAB MANUAL

CALCULATIONS:

1)Calculate the Voltage Gain by using the formula Av== Output voltage (V0) / Input voltage (Vs).

Voltage Gain in dB = 20log(Av).

RESULT:

The Voltage gain and Bandwidth of CE amplifier is measured and

the frequency response of the CE Amplifier is obtained.
1. The Voltage gain of CE Amplifier is .

REMARKS:

SIGNATURE OF THE FACULTY

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 EDC LAB MANUAL

EXPERIMENT-12

FET - CS AMPLIFIER
DATE:

AIM: To obtain the frequency response of the Common Source FET Amplifier and Measure
the Voltage gain and Bandwidth of CS Amplifier.

EQUIPMENTS:

1. Regulated Power Supply (0-30V)-1No.

2. Function Generator(10-1MHz)-1No
3. Cathode Ray Oscilloscope (10-2MHz)-1No.

ELECTRONIC COMPONENTS:

1. Transistor BFW10-1No.
2. Resistors 100KΩ-1No, 3.3KΩ-1No, 1 KΩ - 1 No.
3. Capacitors -10µf – 3No.
4. Bread Board-1No.
5. CRO probes-2No.
5. Connecting Wires-1 Set.

THEORY:
A field-effect transistor (FET) is a type of transistor commonly used for weak-signal
amplification (for example, for amplifying wireless (signals). The device can amplify analog
or digital signals. It can also switch DC or function as an oscillator. In the FET, current flows
along a semiconductor path called the channel. At one end of the channel, there is an
electrode called the source. At the other end of the channel, there is an electrode called the
drain. The physical diameter of the channel is fixed, but its effective electrical diameter can
be varied by the application of a voltage to a control electrode called the gate. Field-effect
transistors exist in two major classifications. These are known as the junction FET (JFET)
and the metal-oxide- semiconductor FET (MOSFET). The junction FET has a channel
consisting of N-type semiconductor (N-channel) or P-type semiconductor (P-channel)
material; the gate is made of the opposite semiconductor type. In P-type material, electric
charges are carried mainly in the form of electron deficiencies called holes. In N-type
material, the charge carriers are primarily electrons. In a JFET, the junction is the boundary
between the channel and the gate. Normally, this P-N junction is reverse-biased (a DC
voltage is applied to it) so that no current flows between the channel and the gate. However,
under some conditions there is a small current through the junction during part of the input
signal cycle.

The FET has some advantages and some disadvantages relative to the bipolar transistor.
Field-effect transistors are preferred for weak-signal work, for example in wireless,

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communications and broadcast receivers. They are also preferred in circuits and systems
requiring high impedance. The FET is not, in general, used for high-power
amplification, such as is required in large wireless communications and broadcast
transmitters.Field-effect transistors are fabricated onto silicon integrated circuit (IC)
chips. A single IC can contain many thousands of FETs, along with other components
such as resistors,capacitors, and diodes.

PROCEDURE:

PRECAUTIONS:

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1. The voltages levels in the RPS must be kept in minimum position before switching it
“ON” or “OFF”.
2. The terminals of the transistor should be identified properly.
3. Readings should be taken without errors.
4. Interconnections should not be made on the bread board with power switched on.

OBSERVATIONS:

VIN = 50mV at 1 KHz

S. NO. Frequency VOUT (volt) A = Vout/VIN Gain= 20 log Vout/VIN (db)
1. 20Hz
2. 50 Hz
3. 100 Hz
4. 200 Hz
5. 500 Hz
6. 1KHz
7. 2 KHz
8. 5 KHz
9. 10 KHz
10. 20 KHz
11. 50 KHz
12. 100 KHz
13. 200 KHz
14. 500 KHz
15. 1MHz
MODEL GRAPHS:

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 EDC LAB MANUAL

CALCULATIONS:

1) Calculate the Voltage Gain by using the formula Av== Output voltage (V0) / Input voltage (Vs).

Voltage Gain in dB = 20log(Av).

2) The Bandwidth of the amplifier is calculated from the graph using the expression,
Bandwidth, BW=f2-f1
Where f1 is lower 3-dB frequency
f2 is upper 3-dB frequency

RESULT:

The Voltage gain and Bandwidth of CS FET amplifier is measured and

the frequency response of the CS FET Amplifier is obtained.
1. The Voltage gain of CS FET Amplifier is .
2. The Bandwidth of CE Amplifier is .

REMARKS:

SIGNATURE OF THE FACULTY

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 EDC LAB MANUAL

EXPERIMENT-13

CHARACTERISTICS OF PHOTOTRANSISTOR
AIM: To obtain the V-I characteristics of the given photo transistor.

APPARATUS:

1. Photo transistor IR 3MM 935NM

3. R.P.S (O-30V) 2Nos
4. Resistors 220 ohm
5. Bread board and connecting wires

CIRCUIT DIAGRAM:

THEORY:
The photo transistor is a 3 terminal device which gives an electrical current as output if
an input light excitation is provided. It works in reverse bias. When reverse biased along with the
reverse bias current ICO, the light current IL is also added to the total output current. The
amount of current flow depends on the input light intensity given as excitation. Phototransistor is
basically a photodiode with amplification and operates by exposing its base region to the light
source. Phototransistor light sensors operate the same as photodiodes except that they can
provide current gain and are much more sensitive than the photodiode with currents are 50 - 100
times greater than that of the standard photodiode. Phototransistors consist mainly of a bipolar
NPN transistor with the collector-base PN-junction reverse-biased. The phototransistor’s large
base region is left electrically unconnected and uses photons of light to generate a base current
which in turn causes a collector to emitter current to flow.

PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Keep the input light excitation fixed. Then vary the Vce in steps of 1V till the maximum
voltage rating of the transistor is reached and then note down the corresponding values of Ic.
3. Tabulate the readings. For various values of input excitation record the values of Vce

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and Ic and plot the characteristics of the photo transistor.

OBSERVATIONS:

V-I Characteristics:

Sl.No VCE(Voltage) Ic (mA)

MODEL GRAPH:

PRECAUTIONS:

1. The photo transistor must be given a proper excitation for a reasonable current flow.
2. Connections must be tight.

RESULT:

REMARKS:

SIGNATURE OF THE FACULTY

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 EDC LAB MANUAL

EXPERIMENT 14

DESIGN AND VERIFICATION OF COLLECTOR TO BASE BIAS

CIRCUITS
Aim : To design a collector to base bias circuit and observe stability by changing β of the given
transistor in CE configuration.

APPARATUS:

Transistors (BC 107) with different β values

R.P.S (O-30V) 2 No.s
Resistors (from design values)
Bread board and connecting wires

CIRCUIT DIAGRAM:

Collector-to-base bias circuit

CALCULATIONS:

Collector-to-base bias circuit

Given VCC=10V, IC=4mA, VCE=6V, VBE=0.6V

IC=IB/ β
RC=(VCC-VCE)/(IB+IC)
RB={(VCC-VBE-ICRC) β}/IC – RC

PROCEDURE:

1. Assemble the circuit on breadboard with design values of R C, RB and β.

2. Apply VCC and measure VCE and VBE and record the readings in the table.

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3. Without changing bias resistors, change the transistors with other β values and repeat the
above step.
4. Repeat the above steps using the collector to base bias circuit and tabulate all the readings.

OBSERVATIONS

Collector to base bias

S.No β value VCE VBE IC=(VCC-VCE)/RC - IB

PRECAUTIONS:

1. The supply voltage should not exceed the rating of the transistor
2. Meters should be connected properly according to their polarities

RESULT:

REMARKS:

SIGNATURE OF THE FACULTY

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