Module 4

8086 interrupts , program examples, interrupt Types, 8254 software ,programmable

TIMER/ COUNTER , basic 8253 and 8254 operations, 8255A, 8259A Priority
interrupt controller. Direct Memory Access data transfer – circuit connections and
operations of the Intel 8257 DMA controller, DMA transfer timing diagram.

Microprocessor - 8086 Interrupts

Interrupt is the method of creating a temporary halt during program execution and
allows peripheral devices to access the microprocessor. The microprocessor responds
to that interrupt with an ISR (Interrupt Service Routine), which is a short program to
instruct the microprocessor on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin
associated is INTA called interrupt acknowledge.
NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of the
return address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using
clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is
disabled, then the microprocessor first completes the current execution and sends ‘0’ on
INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and
during the second ‘0’ the microprocessor receives the 8 bit, say X, from the
programmable interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return
address are pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0

Software Interrupts
Some instructions are inserted at the desired position into the program to create
interrupts. These interrupt instructions can be used to test the working of various
interrupt handlers. It includes −
INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
  CS value of the return address and IP value of the return address are pushed on
to the stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H
similarly for type2 is 00008H and ……so on. The first five pointers are dedicated
interrupt pointers. i.e. −
 TYPE 0 interrupt represents division by zero situation.
 TYPE 1 interrupt represents single-step execution during the debugging of a
program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced
microprocessors, and interrupts from 32 to Type 255 are available for hardware and
software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the
program so that when the processor reaches there, then it stops the normal execution
of program and follows the break-point procedure.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on
to the stack.
 IP is loaded from the contents of the word location 3×4 = 0000CH
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is
CEH. As the name suggests it is a conditional interrupt instruction, i.e. it is active only
when the overflow flag is set to 1 and branches to the interrupt handler whose interrupt
type number is 4. If the overflow flag is reset then, the execution continues to the next
instruction.
Its execution includes the following steps −
 Flag register values are pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on
to the stack.
 IP is loaded from the contents of word location 4×4 = 00010H
 CS is loaded from the contents of the next word location.
 Interrupt flag and Trap flag are reset to 0
Microprocessor | 8254 programmable
interval timer
8254 is a device designed to solve the timing control problems in a microprocessor. It has
3 independent counters, each capable of handling clock inputs up to 10 MHz, and size of
each counter is 16 bit. It operates in +5V regulated power supply and has 24 pin signals.
All modes are software programmable. The 8254 is an advanced version of 8253 which
did not offered the feature of read back command.
The basic block diagram of 8254 is:

The pin diagram for 8254 is :

 It has 3 counters each with two inputs (Clock and
Gate) and one output. Gate is used to enable or disable counting. When any
value of count is loaded and value of gate is set(1), after every step value of
count is decremented by 1 until it becomes zero.
Depending upon the value of CS, A1, and A0 we can determine the addresses
of the selected counter.
Applications –
1. To generate an accurate time delay
2. As an event counter
3. Square wave generator
4. Rate generator
5. Digital one shot

Intel 8253/54 - Operational Modes

253/54 can be operated in 6 different modes. In this chapter, we will discuss these
operational modes.

Mode 0 ─ Interrupt on Terminal Count

 It is used to generate an interrupt to the microprocessor after a certain interval.
 Initially the output is low after the mode is set. The output remains LOW after the
count value is loaded into the counter.
 The process of decrementing the counter continues till the terminal count is
reached, i.e., the count become zero and the output goes HIGH and will remain
high until it reloads a new count.
 The GATE signal is high for normal counting. When GATE goes low, counting is
terminated and the current count is latched till the GATE goes high again.
Mode 1 – Programmable One Shot
 It can be used as a mono stable multi-vibrator.
 The gate input is used as a trigger input in this mode.
 The output remains high until the count is loaded and a trigger is applied.

Mode 2 – Rate Generator

 The output is normally high after initialization.
 Whenever the count becomes zero, another low pulse is generated at the output
and the counter will be reloaded.

Mode 3 – Square Wave Generator

 This mode is similar to Mode 2 except the output remains low for half of the timer
period and high for the other half of the period.

Mode 4 − Software Triggered Mode

 In this mode, the output will remain high until the timer has counted to zero, at
which point the output will pulse low and then go high again.
 The count is latched when the GATE signal goes LOW.
 On the terminal count, the output goes low for one clock cycle then goes HIGH.
This low pulse can be used as a strobe.

Mode 5 – Hardware Triggered Mode

 This mode generates a strobe in response to an externally generated signal.
 This mode is similar to mode 4 except that the counting is initiated by a signal at
the gate input, which means it is hardware triggered instead of software triggered.
 After it is initialized, the output goes high.
 When the terminal count is reached, the output goes low for one clock cycle.

8255A - Programmable Peripheral Interface

The 8255A is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O under certain conditions as required. It can be used with almost
any microprocessor.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as
per the requirement.

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
  Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C
upper (PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A
and upper PORT C. Group B includes PORT B and lower PORT C. These two groups
can be programmed in three different modes, i.e. the first mode is named as mode 0,
the second mode is named as Mode 1 and the third mode is named as Mode 2.

Operating Modes
8255A has three different operating modes −
 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two
4-bit ports. Each port can be programmed in either input mode or output mode
where outputs are latched and inputs are not latched. Ports do not have interrupt
capability.
 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be
configured as either input or output ports. Each port uses three lines from port C
as handshake signals. Inputs and outputs are latched.
 Mode 2 − In this mode, Port A can be configured as the bidirectional port and
Port B either in Mode 0 or Mode 1. Port A uses five signals from Port C as
handshake signals for data transfer. The remaining three signals from Port C can
be used either as simple I/O or as handshake for port B.

Features of 8255A
The prominent features of 8255A are as follows −
 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux'd.
 It is TTL compatible.
 It has improved DC driving capability.

8255 Architecture
The following figure shows the architecture of 8255A −
Intel 8255A - Pin Description
8259A Interrupt Controller
8259A Interrupt Controller is designed to transfer the interrupt with highest priority to the CPU, along
with interrupt address information.
Key Features:
 Eight interrupt request input per chip
 Up to 64 interrupt request inputs per system
 Edge or level triggered interrupt request inputs
 Individually maskable interrupt requests
 Programmable interrupt request priority orders
 Polling operation capability
 Two modes of operation make the controller compatible with 8080/85 and 8086/88/286
microprocessors
 Microcomputer systems with I/O devices are serviced with efficient manner by using iW-
8259A interrupt controller
 Extended mode with cascade connection of external interrupts
Supported Devices:
 SmartFusion2
 IGLOO2

Microprocessor - 8257 DMA Controlle

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the
fastest rate. It allows the device to transfer the data directly to/from memory without any
interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and
control bus, so the device is free to transfer data directly to/from the memory. The DMA
data transfer is initiated only after receiving HLDA signal from the CPU.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −
 Initially, when any device has to send data between the device and the memory,
the device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU
to assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus.
The CPU leaves the control over bus and acknowledges the HOLD request
through HLDA signal.
  Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.

Features of 8257
Here is a list of some of the prominent features of 8257 −
 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer
operations.
 It generates MARK signal to the peripheral device that 128 bytes have been
transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture
The following image shows the architecture of 8257 −
8257 Pin Description
The following image shows the pin diagram of a 8257 DMA controller −

DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the
peripheral devices for using DMA services. When the fixed priority mode is selected,
then DRQ0 has the highest priority and DRQ3 has the lowest priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting
peripheral about the status of their request by the CPU. These lines can also act as
strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller. In the Slave mode, it carries command words to
8257 and status word from 8257. In the master mode, these lines are used to send
higher byte of the generated address to the latch. This address is further latched using
ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read
internal registers of 8257 in the Slave mode. In the master mode, it is used to read data
from the peripheral devices during a memory write cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data
bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or
terminal count register. In the master mode, it is used to load the data to the peripheral
devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A3
These are the four least significant address lines. In the slave mode, they act as an
input, which selects one of the registers to be read or written. In the master mode, they
are the four least significant memory address output lines generated by 8257.
CS
It is an active-low chip select line. In the Slave mode, it enables the read/write
operations to/from 8257. In the master mode, it disables the read/write operations
to/from 8257.
A4 - A7
These are the higher nibble of the lower byte address generated by DMA in the master
mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait
states.
HRQ
This signal is used to receive the hold request signal from the output device. In the
slave mode, it is connected with a DRQ input line 8257. In Master mode, it is connected
with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus
has been granted to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed
memory locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the
DMA controller into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous
MARK output to the selected peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.