CEN468: Computer Organization and Design

Lab Experiment 3
Building a Cache Memory with Quartus II and Altera DE2
Board
Prepared By:
Eng. Maha Yaghi & Eng. Gasm El Bary

Objectives
1. Understand the principles of cache memory and its role in computer architecture.
2. Implement a basic cache memory system with read, write, and replacement functionality in VHDL.
3. Design and analyze the Least Recently Used (LRU) replacement policy for managing cache data.
4. Create a multi-level cache hierarchy with L1 and L2 caches connected to main memory.

5. Test and validate the cache system on the Altera DE2 FPGA board, observing cache hits, misses, and data retrieval
patterns.

Required Equipment

(a) Altera DE2 Board [1] (b) Altera Quartus II Software [2]

Figure 1: List of equipment

Introduction
In this lab, we will explore the essential concepts and functions of cache memory by designing and testing cache systems on
the Altera DE2 FPGA board. Cache memory is a critical component in computer architecture, significantly enhancing the
speed and efficiency of data access by temporarily storing frequently used data close to the processor. By implementing a
two-level cache hierarchy, we will observe how data is managed between L1, L2, and main memory to optimize performance
in data retrieval and processing tasks.
The DE2 board features the Cyclone II FPGA chip, which includes numerous configurable components such as
switches, LEDs, and displays, enabling us to simulate and visualize the behaviors of different cache levels in real-time.
The DE2 board allows for the testing of cache hit and miss scenarios, the impact of replacement policies, and the efficiency
of cache hierarchy.

1
1 Cache Memory Overview
Cache memory operates as a high-speed intermediary between the CPU and main memory. It holds copies of frequently
accessed data, allowing the CPU to retrieve this information faster than if it had to access the main memory directly.
Most systems implement multiple levels of cache:
• L1 Cache: The primary cache, closest to the CPU, offering the fastest access speeds. L1 cache has limited capacity,
storing only essential data.

• L2 Cache: A secondary cache with a larger capacity than L1 but with slightly slower access. It serves as a backup,
holding data that may not be available in L1.
When the CPU requests data, it first checks the L1 cache, followed by L2 if the data is not found in L1. If the
data is absent in both caches (a cache miss), it is fetched from main memory. Replacement policies, such as the Least
Recently Used (LRU) policy, help determine which data to retain or replace when the cache reaches capacity, ensuring
that frequently accessed data remains in the cache for quick retrieval.
This lab is organized into three exercises, each focusing on different aspects of cache memory:
• Exercise 1: Direct-Mapped - In this exercise, we will implement a simple cache with read and write operations to
observe the fundamental behavior of a cache. This exercise will demonstrate basic cache data storage and retrieval.

• Exercise 2: LRU Replacement Policy - The second exercise introduces the Least Recently Used (LRU)
replacement policy in a two-line cache. Here, we will explore how the LRU policy manages data when the cache
reaches full capacity.
• Exercise 3: L1 and L2 Cache with Memory Access - In the final exercise, we will implement a dual-level
cache system with both L1 and L2 caches, along with access to main memory. This exercise allows us to simulate
a realistic cache hierarchy, observe cache misses, and validate the memory access flow.
Through these exercises, students will gain practical insights into cache operation, replacement policies, and the role
of cache hierarchy in minimizing data access times. This lab provides a hands-on understanding of cache memory as a
foundational concept in modern computer architecture, reinforcing the importance of caching in achieving efficient data
management and system performance.

2 Setup: Create a Project in Quartus II

To start using Quartus II, navigate to the Start Menu and search for Quartus II. Select Quartus II (64-bit) as shown in
Figure 2.

Figure 2: Quartus II (64-bit)

The default view of Quartus II is shown in Figure 3.

2
 Figure 3: Default view of Quartus II

To create a new project, you need to follow the steps below:

1. From the Menu, select File →
− New Project Wizard. This will open the project creator wizard shown in Figure 4.

Figure 4: Project Wizard I

2. In the first page of the Wizard, specify the working directory of the project then select a name. Note that the
selected name should be used as the top-level design entity name (Example: lab2).

3. On the second page, the Wizard asks for any source files that could be imported from other designs and projects
so that it can be used in the current project. Since no such files has to be included for this experiment, click next.

3
 4. The third page asks for the target device on which the circuit will be synthesized. Check the ALTERA chip
connected to the board and note down the device family and number. In the Device family option scroll for the
device family of your board. Then, in the available device options scroll for the device number as shown in Figure 5.
Click finish to start programming.

Figure 5: Project Wizard III

5. To open a VHDL design file, select File from the main menu then New →
− VHDL File as shown in Figure 6.

Figure 6: Creating a VHDL File

6. Congratulations! You can start working on your VHDL code now.

3 Exercise 1: Implementing a Direct-Mapped Cache

This exercise demonstrates the implementation of a simple direct-mapped cache using VHDL. The cache enables reading
and writing data to specific addresses, with each address mapped directly to a cache line. This approach provides
straightforward cache management and fast access times.
Follow the steps below to design the direct-mapped cache. This implementation will allow you to perform read and
write operations on memory locations using control signals and observe cache hits and misses.

1. Include the necessary IEEE libraries

Include the IEEE libraries needed for the VHDL code, including conversions.

1 library ieee;
2 use ieee.std_logic_1164.all;

4
 3 use ieee.numeric_std.all;

2. Define the cache module parameters

Define the parameters and ports for the cache module, including clock, enable, read, write, address, and data
signals.
• Ports:
– clk: The clock signal.
– enable: Signal to enable cache operations.
– read: An input signal to initiate a read operation.
– write: An input signal to initiate a write operation.
– address: The address for read/write operations (2 bits).
– data in: Data to be written to the cache (4 bits).
– data out: Data output for read operations (4 bits).
– hit: Signal indicating whether the data was found in the cache (cache hit).

1 entity lab3test is
2 port (
3 clk: in std_logic;
4 enable: in std_logic;
5 read: in std_logic;
6 write: in std_logic;
7 address: in std_logic_vector(1 downto 0);
8 data_in: in std_logic_vector(3 downto 0);
9 data_out: out std_logic_vector(3 downto 0);
10 hit: out std_logic
11 );
12 end lab3test;

3. Define the cache array and valid bits

Declare an array cache to hold the data for each cache line and a valid signal to keep track of valid data in each
cache line.

1 architecture Behavioral of lab3test is

2 type cache_array is array (0 to 3) of std_logic_vector(3 downto 0);
3 signal cache: cache_array := (others => "0000");
4 signal valid: std_logic_vector(3 downto 0) := "0000"; -- 4 valid bits
5 begin

4. Create a process for read and write operations

Implement a process block within the architecture with a sensitivity list containing clk.
• When enable is ’1’:
– If read is ’1’:
(a) Check if the address has valid data by reading the valid bit for the specified address.
(b) If valid, output data from the cache array and set hit to ’1’.
(c) If not valid, set data out to high impedance (others => ’Z’) and hit to ’0’.
– If write is ’1’:
(a) Write data in to the cache array at the specified address.
(b) Set the valid bit for the address to ’1’ to indicate data is valid.
(c) Set hit to ’1’ to confirm data was written successfully.

1 process(clk)
2 begin
3 if rising_edge(clk) then
4 if enable = ’1’ then

5
 5 if read = ’1’ then
6 if valid(to_integer(unsigned(address))) = ’1’ then
7 data_out <= cache(to_integer(unsigned(address)));
8 hit <= ’1’; -- Cache hit
9 else
10 data_out <= (others => ’Z’); -- High impedance for miss
11 hit <= ’0’; -- Cache miss
12 end if;
13 elsif write = ’1’ then
14 cache(to_integer(unsigned(address))) <= data_in;
15 valid(to_integer(unsigned(address))) <= ’1’; -- Mark as valid
16 hit <= ’1’;
17 end if;
18 end if;
19 end if;
20 end process;
21 end Behavioral;

5. Assign your input and output pins

Assign the input and output pins on the FPGA as follows:

Input/Output Pin
clk KEY0
enable SW0
read SW2
write SW3
address[1] SW5
address[0] SW4
data in[3] SW9
data in[2] SW8
data in[1] SW7
data in[0] SW6
data out[3] LEDR9
data out[2] LEDR8
data out[1] LEDR7
data out[0] LEDR6
hit LEDG5

Table 1: Pin Assignments for Exercise 1

6. Test your design as follows

Test the cache by performing read and write operations and verifying cache hits and misses:
(a) Set data in = ”1010”.
(b) Set address = ”01”.
(c) Set write = 1 and enable = 1.
(d) Produce a clock event (from low to high) by setting clk = 1 and then back to 0.
(e) The cache should now hold the value ”1010” at address ”01” and valid should be set for that address.
(f) To read the value:
• Set address = ”01”.
• Set read = 1 and enable = 1.
• Produce a clock event.
• data out should display ”1010” and hit should be ’1’ for a cache hit.
(g) Test additional read/write scenarios to verify the cache behavior across various addresses.

6
4 Exercise 2: Implementing Least Recently Used (LRU) Cache Replacement Policy
This exercise focuses on the implementation of a Least Recently Used (LRU) replacement policy in a two-line cache.
LRU is a common replacement strategy where the cache replaces the least recently accessed data when a new entry needs
to be stored in a full cache. This exercise will demonstrate how to track and manage data to keep frequently accessed
entries available for fast retrieval.
Follow the steps below to implement the LRU policy in a direct-mapped cache. The cache will determine which line
to replace based on recent usage.

1. Include the necessary IEEE libraries

Start by including the necessary IEEE libraries for signal types and integer conversions.

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;

2. Define the cache module parameters

Define the ports for the cache module, including clock, reset, enable, read, write, address, and data signals, as well
as output indicators for data output and cache hit status.
• Ports:
– Clock: The clock signal.
– Reset: Resets the cache and clears stored values.
– Enable: Signal to enable cache operations.
– Read: An input signal to initiate a read operation.
– Write: An input signal to initiate a write operation.
– Address: The address for read/write operations (2 bits).
– Data in: Data to be written to the cache (2 bits).
– Data out: Data output for read operations (2 bits).
– Cache hit: Signal indicating whether the data was found in the cache.

1 entity lab3test is
2 port(
3 Clock : in std_logic;
4 Reset : in std_logic;
5 Enable : in std_logic;
6 Read : in std_logic;
7 Write : in std_logic;
8 Address : in std_logic_vector(1 downto 0);
9 Data_in : in std_logic_vector(1 downto 0);
10 Data_out : out std_logic_vector(1 downto 0);
11 Cache_hit : out std_logic
12 );
13 end lab3test;

3. Define the cache arrays and LRU tracker

Declare arrays to hold the cache data, cache tags, and valid bits, as well as an lru tracker signal to keep track of
which line is the least recently used.

1 architecture Behavioral of lab3test is

2 type cache_type is array (1 downto 0, 1 downto 0) of std_logic_vector(1 downto 0);
3 type cache_tags_type is array (1 downto 0) of std_logic_vector(1 downto 0);
4

5 signal cache_data : cache_type := (others => (others => "00"));

6 signal cache_tags : cache_tags_type;
7 signal lru_tracker : std_logic := ’0’;
8 signal cache_valid : std_logic_vector(1 downto 0) := "00";
9 begin

7
 4. Create a process for read, write, and LRU replacement operations
Implement a process block with a sensitivity list containing Clock and Reset.

• When Reset is ’1’, clear all cache data, tags, valid bits, and set the lru tracker to ’0’.
• On a rising clock edge:
– If Enable is ’1’:
∗ If Write is ’1’:
(a) Check if there is an empty (invalid) line in the cache:
· Write data to the first invalid line and store the address as the tag.
· Update cache valid to mark the line as valid and set the lru tracker to point to the next line.
(b) If both lines are valid, use lru tracker to identify the least recently used line:
· Write data to the identified line, update the tag, and toggle the lru tracker.
∗ If Read is ’1’:
(a) Check if the requested data is present in either cache line by comparing tags.
(b) If a match is found, output data from the corresponding cache line and set Cache hit to ’1’.
(c) If no match is found, set Cache hit to ’0’ to indicate a cache miss.

1 process (Clock, Reset)

2 begin
3 if Reset = ’1’ then
4 cache_data <= (others => (others => "00"));
5 cache_valid <= "00";
6 lru_tracker <= ’0’;
7 elsif rising_edge(Clock) then
8 if Enable = ’1’ then
9 if Write = ’1’ then
10 if cache_valid(0) = ’0’ then
11 cache_data(0, to_integer(unsigned(Address))) <= Data_in;
12 cache_valid(0) <= ’1’;
13 cache_tags(0) <= Address;
14 lru_tracker <= ’1’;
15 elsif cache_valid(1) = ’0’ then
16 cache_data(1, to_integer(unsigned(Address))) <= Data_in;
17 cache_valid(1) <= ’1’;
18 cache_tags(1) <= Address;
19 lru_tracker <= ’0’;
20 else
21 if lru_tracker = ’0’ then
22 cache_data(0, to_integer(unsigned(Address))) <= Data_in;
23 cache_tags(0) <= Address;
24 lru_tracker <= ’1’;
25 else
26 cache_data(1, to_integer(unsigned(Address))) <= Data_in;
27 cache_tags(1) <= Address;
28 lru_tracker <= ’0’;
29 end if;
30 end if;
31 elsif Read = ’1’ then
32 if cache_valid(0) = ’1’ and cache_tags(0) = Address then
33 Data_out <= cache_data(0, to_integer(unsigned(Address)));
34 Cache_hit <= ’1’;
35 elsif cache_valid(1) = ’1’ and cache_tags(1) = Address then
36 Data_out <= cache_data(1, to_integer(unsigned(Address)));
37 Cache_hit <= ’1’;
38 else
39 Cache_hit <= ’0’;
40 end if;
41 end if;
42 end if;
43 end if;

8
44 end process;
45 end Behavioral;

5. Assign your input and output pins

Assign the input and output pins on the FPGA as follows:

Input/Output Pin
Clock KEY0
Reset SW0
Enable SW1
Read SW2
Write SW3
Address[1] SW5
Address[0] SW4
Data in[1] SW9
Data in[0] SW8
Data out[1] LEDR9
Data out[0] LEDR8
Cache hit LEDG7

Table 2: Pin Assignments for Exercise 2

6. Test your design as follows

(a) Initialize the System

i. Set Reset = 1 (slide switch SW0 high) to clear the cache and initialize the system.
ii. Set Reset = 0 to begin normal operation.
(b) Test Write Operation with Empty Cache
i. Set Enable = 1 (slide switch SW1 high) to activate the cache.
ii. Set Write = 1 (slide switch SW3 high) to enable write mode.
iii. Set Address = ”00” by setting both Address[1] (SW5) and Address[0] (SW4) low.
iv. Set Data in = ”10” (slide switch SW7 high, SW6 low).
v. Press Clock (KEY0) to execute the write operation.
Expected Outcome: Data in (10) should be written to the first cache line since the cache is empty.
Cache hit LED should remain off, as this is a write operation. The lru tracker should update to point
to the next line.
(c) Test Write Operation with LRU Replacement
i. Set Address = ”01” to select a new address (SW5 low, SW4 high).
ii. Set Data in = ”11” (both SW7 and SW6 high).
iii. Press Clock to perform the write operation.
Expected Outcome: Data in (11) should be written to the second cache line since the first is already
occupied. The lru tracker should update to point back to the first line, setting it as the least recently used
line.
(d) Test Read Operation with LRU Replacement Verification
i. Set Read = 1 (slide switch SW2 high) to enable read mode.
ii. Set Address = ”00” (both SW5 and SW4 low).
iii. Press Clock to perform the read.
Expected Outcome: Data out should show 10, retrieved from the first cache line. Cache hit LED should
light up to indicate a cache hit. The lru tracker should now update to make the second line the least recently
used.
(e) Test LRU Replacement on Full Cache
i. Set Write = 1 (slide switch SW3 high) and Address = ”10” (SW5 high, SW4 low) to test a new address.

9
 ii. Set Data in = ”01” (SW7 low, SW6 high).
iii. Press Clock to perform the write.
Expected Outcome: Since both cache lines are occupied, the least recently used line (second cache line in
this case) should be replaced with the new data. Data in (01) should be written to the second cache line,
replacing the old data, and the lru tracker should update.
(f) Test Cache Miss and LRU Replacement with Read Operation
i. Set Read = 1 and Address = ”00” (SW5 and SW4 high) to read from an address not currently in the
cache.
ii. Press Clock to perform the read.
Expected Outcome: Since the address is not in either cache line, Cache hit should be off, indicating a
cache miss. After this read, one cache line (determined by the lru tracker) should be replaced with data
from Address = ”11”.

5 Exercise 3: Implementing Multi-Level Cache with L1, L2, and Main Memory Access
This exercise extends the cache design to include a multi-level cache system with both L1 and L2 caches, along with
access to main memory. When data is requested, the system first checks L1, then L2, and if the data is not present in
either cache, it is retrieved from main memory. This approach mirrors a real-world memory hierarchy, improving system
performance by maintaining frequently accessed data in faster, smaller caches.
The system in this exercise will simulate the behavior of a multi-level cache with a focus on understanding cache hits
and misses at different levels.

1. Include the necessary IEEE libraries

Start by including the IEEE libraries needed for signal types and integer conversions.

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;

2. Define the cache module parameters

Define the ports for the multi-level cache module, including clock, reset, enable, read, write, address, and data
signals, as well as output indicators for L1 cache hit, L2 cache hit, and main memory access.
• Ports:
– Clock: The clock signal.
– Reset: Resets the cache and clears stored values.
– Enable: Signal to enable cache operations.
– Read: An input signal to initiate a read operation.
– Write: An input signal to initiate a write operation.
– Address: The address for read/write operations (2 bits).
– Data in: Data to be written to the cache (2 bits).
– Data out: Data output for read operations (2 bits).
– L1 Cache hit: Signal indicating a hit in L1 cache.
– L2 Cache hit: Signal indicating a hit in L2 cache.
– Memory access: Signal indicating access to main memory.

1 entity lab3test is
2 port(
3 Clock : in std_logic;
4 Reset : in std_logic;
5 Enable : in std_logic;
6 Read : in std_logic;
7 Write : in std_logic;
8 Address : in std_logic_vector(1 downto 0);
9 Data_in : in std_logic_vector(1 downto 0);
10 Data_out : out std_logic_vector(1 downto 0);

10
11 L1_Cache_hit : out std_logic;
12 L2_Cache_hit : out std_logic;
13 Memory_access : out std_logic
14 );
15 end lab3test;

3. Define the cache arrays, valid bits, and main memory

Declare arrays to hold the L1 and L2 cache data, cache valid bits, a flag for delayed updates to L1, and the main
memory array with predefined data values.

1 architecture Behavioral of lab3test is

2 type cache_type is array (0 to 3) of std_logic_vector(1 downto 0); -- 4-address cache
3 signal L1_cache : cache_type := (others => "00");
4 signal L2_cache : cache_type := (others => "00");
5 signal L1_valid : std_logic_vector(3 downto 0) := "0000";
6 signal L2_valid : std_logic_vector(3 downto 0) := "0000";
7 signal temp_data_out : std_logic_vector(1 downto 0) := "00";
8 signal update_L1_next : std_logic := ’0’; -- Delayed update flag for L1
9

10 -- Internal main memory array with predefined data

11 type memory_array is array (0 to 3) of std_logic_vector(1 downto 0);
12 signal main_memory : memory_array := ("01", "10", "11", "00");
13 begin

4. Create a process for read, write, and multi-level cache operations

Implement a process block with a sensitivity list containing Clock and Reset.
• When Reset is ’1’, clear all cache data, valid bits, and reset flags.
• On a rising clock edge:
– If Enable is ’1’:
∗ If Write is ’1’:
(a) Write Data in to both L1 and L2 caches at the specified address, updating valid bits.
(b) Set L1 and L2 hit signals to ’0’ and Memory access to ’0’.
∗ If Read is ’1’:
(a) Check L1 Cache: If data is valid and matches the address in L1, output data from L1, set
L1 Cache hit to ’1’, and disable further checks.
(b) Check L2 Cache: If data is valid in L2 (and L1 misses), output data from L2, set L2 Cache hit
to ’1’, and enable an update to L1 for the next cycle.
(c) Main Memory Access: If both L1 and L2 miss, load data from main memory, signal Memory access,
and update both caches.

1 process (Clock, Reset)

2 begin
3 if Reset = ’1’ then
4 -- Reset all cache data, valid bits, and flags
5 L1_cache <= (others => "00");
6 L2_cache <= (others => "00");
7 L1_valid <= "0000";
8 L2_valid <= "0000";
9 temp_data_out <= "00";
10 update_L1_next <= ’0’;
11 L1_Cache_hit <= ’0’;
12 L2_Cache_hit <= ’0’;
13 Memory_access <= ’0’;
14 elsif rising_edge(Clock) then
15 if Enable = ’1’ then
16 if Write = ’1’ then
17 -- Write operation: Update both L1 and L2 to keep them consistent
18 L1_cache(to_integer(unsigned(Address))) <= Data_in;

11
19 L2_cache(to_integer(unsigned(Address))) <= Data_in;
20 L1_valid(to_integer(unsigned(Address))) <= ’1’;
21 L2_valid(to_integer(unsigned(Address))) <= ’1’;
22 L1_Cache_hit <= ’0’;
23 L2_Cache_hit <= ’0’;
24 Memory_access <= ’0’;
25 update_L1_next <= ’0’;
26

27 elsif Read = ’1’ then

28 if L1_valid(to_integer(unsigned(Address))) = ’1’ and
L1_cache(to_integer(unsigned(Address))) = Data_in then
29 -- L1 hit
30 Data_out <= L1_cache(to_integer(unsigned(Address)));
31 L1_Cache_hit <= ’1’;
32 L2_Cache_hit <= ’0’;
33 Memory_access <= ’0’;
34 update_L1_next <= ’0’;
35

36 elsif L2_valid(to_integer(unsigned(Address))) = ’1’ and

L2_cache(to_integer(unsigned(Address))) = Data_in then
37 -- L2 hit, L1 miss
38 Data_out <= L2_cache(to_integer(unsigned(Address)));
39 temp_data_out <= L2_cache(to_integer(unsigned(Address))); -- Prepare for L1 load
40 L1_Cache_hit <= ’0’;
41 L2_Cache_hit <= ’1’;
42 Memory_access <= ’0’;
43 update_L1_next <= ’1’;
44

45 else
46 -- Miss in both caches: Access main memory
47 Data_out <= main_memory(to_integer(unsigned(Address)));
48 temp_data_out <= main_memory(to_integer(unsigned(Address)));
49 Memory_access <= ’1’;
50 L1_cache(to_integer(unsigned(Address))) <= main_memory(to_integer(unsigned(Address)));
51 L2_cache(to_integer(unsigned(Address))) <= main_memory(to_integer(unsigned(Address)));
52 L1_valid(to_integer(unsigned(Address))) <= ’1’;
53 L2_valid(to_integer(unsigned(Address))) <= ’1’;
54 L1_Cache_hit <= ’0’;
55 L2_Cache_hit <= ’0’;
56 update_L1_next <= ’0’;
57 end if;
58 end if;
59 end if;
60

61 -- Update L1 in the next cycle if L2 hit

62 if update_L1_next = ’1’ then
63 L1_cache(to_integer(unsigned(Address))) <= temp_data_out;
64 L1_valid(to_integer(unsigned(Address))) <= ’1’;
65 update_L1_next <= ’0’;
66 end if;
67 end if;
68 end process;
69 end Behavioral;

5. Assign your input and output pins

Assign the input and output pins on the FPGA as follows:

12
 Input/Output Pin
Clock KEY0
Reset SW0
Enable SW1
Read SW2
Write SW3
Address[1] SW5
Address[0] SW4
Data in[1] SW9
Data in[0] SW8
Data out[1] LEDR9
Data out[0] LEDR8
L1 Cache hit LEDG7
L2 Cache hit LEDG6
Memory access LEDG5

Table 3: Pin Assignments for Exercise 3

6. Test your design as follows

(a) Initialize the System

i. Set Reset = 1 (slide switch SW0 high) to clear both L1 and L2 caches and initialize the system.
ii. Set Reset = 0 to begin normal operation.
(b) Test Write Operation
i.Set Enable = 1 (slide switch SW1 high) to activate the cache.
ii.Set Write = 1 (slide switch SW3 high) to enable write mode.
iii.Choose an address by setting Address[1] (SW5) and Address[0] (SW4) to the desired values.
iv. Example: Set Address = ”00” (both SW5 and SW4 low).
v. Set Data in values:
• Example: Set Data in = ”10” (slide switch SW7 high, SW6 low).
vi. Press Clock (KEY0) to execute the write operation.
Expected Outcome: Data in (10 in this example) should be written to both L1 cache and L2 cache at
address 00. L1 Cache hit, L2 Cache hit, and Memory access LEDs should be off, as this is only a write
operation.
(c) Test Read Operation with L1 Cache Hit
i. Set Read = 1 (slide switch SW2 high) to enable read mode.
ii. Set Address = ”00” to read from the previously written location.
iii. Press Clock to perform the read.
Expected Outcome: Data out should show 10 (LEDR1 on, LEDR0 off) from L1 cache. L1 Cache hit LED
(LEDR8) should be lit, indicating an L1 hit. L2 Cache hit and Memory access LEDs should be off, as data
was retrieved directly from L1.
(d) Test Cache Miss and Main Memory Access
i. Set an address that is not in either cache:
• Example: Set Address = ”01” (SW5 low, SW4 high).
ii. Set Enable = 1 and Read = 1.
iii. Press Clock to perform the read operation.
Expected Outcome: Since Address = 01 is not in L1 cache or L2 cache, Memory access LED (LEDR10)
should light up. Data out will display the predefined data from main memory at Address = 01, which is 10.
L1 cache and L2 cache will update with this value for future accesses. Both L1 Cache hit and L2 Cache hit
LEDs should be off, as this was a main memory access.
(e) Verify Cache Behavior after Main Memory Access
i. Perform a read from Address = 01 again.

13
 Expected Outcome: The data should now be in L1 cache, resulting in an L1 Cache Hit. L1 Cache hit
LED should light up, L2 Cache hit and Memory access LEDs should remain off. Data out should display 10,
retrieved directly from L1 cache.

References
[1] 2018. [Online]. Available: https://www.cl.cam.ac.uk/teaching/1011/ECAD+Arch/background/DE2.html

[2] 2011. [Online]. Available: https://www.element14.com/community/docs/DOC-40098/l/

altera-introduction-to-the-quartus-ii-software

14