Design and Simulation of Power Amplfier
Design and Simulation of Power Amplfier
Design and Simulation of Power Amplfier
Voltage waveforms
2. CLASS B COMPLEMENTARY SYMMETRY AMPLIFIER
Circuit diagram.
Voltage waveforms
3. CLASS A POWER AMPLIFIER. (SERIES FED)
AC sweep
5. CLASS –A TRANSORMER COUPLED POWER AMPIFIER
AMPLIFIER SPECIFICATIONS
Load of 10Ω
Power Supply: 24v Dc
Minimum Bandwidth: 50 Khz
Low Cut-Off Frequency: 60 Hz
Gain at Medium Frequency: 150
Input Voltage (Vin): 12mV
Icq = 12 Ma
OPERATION POINT Q
Output voltage swing = (Gain × input Voltage)
= (150 × 12mV)
= 1.8 V
Vopeak = 1.8 √ 2 = 2.54558 V
To pick Vce from the load line, considering the voltage swing of 2.54558 V, Vce should
be between 5 and 12 V
Vce = 10V
EMITTER RESISTOR
Vre
Re =
Ie
2
=
12 x 10−3
= 166.67 Ω
BIASING RESISTOR
Ic
B=
Ib
Ic
Ib =
B
B from the transistor data sheet is 110
12 x 10−3
=
110
= 109mA
Ip = 20 x 109mA
= 2.18mA
VR2 = VRE + VBE
Since transistor is silicon VBE = 0.7V
= 2 + 0.7
= 2.7 V
V R2
R2 =
Ip
2.7
=
2.18 mA
= 1.238K Ω
VR1 = Vcc - VR2
= 24 – 2.7
= 21.3 V
V R1
R1 =
Ip
21.3
= 2.18 mA
= 9.77K Ω
Capacitor values
Impedance for capacitors = 20 Ω
1
C1, 2 =
2 π x 60 x 20
= 133 nF
1
Ce =
2 π x 60 x 8
= 331.6nF
TRANSFORMER RATIO
Measuring the resistance as seen from primary we pick ratio to match the load impedance which
is 10Ω