INTEGRATED 10/100/1000M ETHERNET Controller For Pci Express Applications
INTEGRATED 10/100/1000M ETHERNET Controller For Pci Express Applications
INTEGRATED 10/100/1000M ETHERNET Controller For Pci Express Applications
RTL8111HS-CG
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
21 January 2014
Track ID: JATR-8275-15
COPYRIGHT
©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
REVISION HISTORY
Revision Release Date Summary
1.0 2014/01/21 First release.
Integrated 10/100/1000M Ethernet Controller for PCI Express ii Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1
2. FEATURES .........................................................................................................................................................................3
3. SYSTEM APPLICATIONS...............................................................................................................................................3
4. FUNCTION BLOCK DIAGRAM.....................................................................................................................................4
5. PIN ASSIGNMENTS .........................................................................................................................................................5
5.1. RTL8111H PIN ASSIGNMENTS ....................................................................................................................................5
5.2. PACKAGE IDENTIFICATION ...........................................................................................................................................5
5.3. RTL8111HS PIN ASSIGNMENTS ..................................................................................................................................6
5.4. PACKAGE IDENTIFICATION ...........................................................................................................................................6
6. PIN DESCRIPTIONS.........................................................................................................................................................7
6.1. POWER MANAGEMENT/ISOLATION ..............................................................................................................................7
6.2. PCI EXPRESS INTERFACE .............................................................................................................................................7
6.3. TRANSCEIVER INTERFACE ............................................................................................................................................8
6.4. CLOCK .........................................................................................................................................................................8
6.5. REGULATOR AND REFERENCE ......................................................................................................................................8
6.6. LEDS ...........................................................................................................................................................................9
6.7. POWER AND GROUND ..................................................................................................................................................9
6.8. GPO PIN ......................................................................................................................................................................9
7. FUNCTIONAL DESCRIPTION.....................................................................................................................................10
7.1. PCI EXPRESS BUS INTERFACE....................................................................................................................................10
7.1.1. PCI Express Transmitter ......................................................................................................................................10
7.1.2. PCI Express Receiver ...........................................................................................................................................10
7.2. CUSTOMIZABLE LED CONFIGURATION ......................................................................................................................11
7.2.1. LED Blinking Frequency Control.........................................................................................................................13
7.3. PHY TRANSCEIVER ...................................................................................................................................................14
7.3.1. PHY Transmitter...................................................................................................................................................14
7.3.2. PHY Receiver .......................................................................................................................................................14
7.3.3. Link Down Power Saving Mode ...........................................................................................................................15
7.3.4. Next Page .............................................................................................................................................................15
7.4. POWER MANAGEMENT...............................................................................................................................................15
7.5. RECEIVE-SIDE SCALING (RSS) ..................................................................................................................................17
7.5.1. Receive-Side Scaling (RSS) Initialization .............................................................................................................17
7.5.2. Protocol Offload...................................................................................................................................................18
7.5.3. RSS Operation ......................................................................................................................................................18
7.6. ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................18
7.7. PHY DISABLE MODE .................................................................................................................................................19
7.8. LATENCY TOLERANCE REPORTING (LTR) .................................................................................................................19
7.9. WAKE PACKET INDICATION (WPI) ............................................................................................................................19
7.10. ‘REALWOW!’ (WAKE-ON-WAN) TECHNOLOGY ......................................................................................................19
7.11. L1.OFF AND L1.SNOOZE ............................................................................................................................................20
7.12. GIGA LITE (500M) .....................................................................................................................................................20
7.13. XTAL-LESS WAKE-ON-LAN....................................................................................................................................20
7.14. LAN DISABLE MODE .................................................................................................................................................20
8. SWITCHING REGULATOR (RTL8111HS ONLY) ....................................................................................................21
9. LDO REGULATOR (RTL8111H ONLY)......................................................................................................................21
Integrated 10/100/1000M Ethernet Controller for PCI Express iii Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
10. POWER SEQUENCE..................................................................................................................................................22
10.1. POWER SEQUENCE PARAMETERS ...............................................................................................................................23
11. CHARACTERISTICS.................................................................................................................................................24
11.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................24
11.2. RECOMMENDED OPERATING CONDITIONS .................................................................................................................24
11.3. ELECTROSTATIC DISCHARGE PERFORMANCE ............................................................................................................24
11.4. CRYSTAL REQUIREMENTS ..........................................................................................................................................25
11.5. OSCILLATOR REQUIREMENTS ....................................................................................................................................25
11.6. ENVIRONMENTAL CHARACTERISTICS ........................................................................................................................25
11.7. DC CHARACTERISTICS ...............................................................................................................................................26
11.8. REFLOW PROFILE RECOMMENDATIONS .....................................................................................................................27
11.9. PCI EXPRESS BUS PARAMETERS ................................................................................................................................28
11.9.1. Differential Transmitter Parameters ...............................................................................................................28
11.9.2. Differential Receiver Parameters ....................................................................................................................29
11.9.3. REFCLK Parameters.......................................................................................................................................29
11.9.4. Auxiliary Signal Timing Parameters ...............................................................................................................33
12. MECHANICAL DIMENSIONS.................................................................................................................................34
13. ORDERING INFORMATION ...................................................................................................................................35
Integrated 10/100/1000M Ethernet Controller for PCI Express iv Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
List of Tables
TABLE 1. POWER MANAGEMENT/ISOLATION ...............................................................................................................................7
TABLE 2. PCI EXPRESS INTERFACE ..............................................................................................................................................7
TABLE 3. TRANSCEIVER INTERFACE ............................................................................................................................................8
TABLE 4. CLOCK ..........................................................................................................................................................................8
TABLE 5. REGULATOR AND REFERENCE ......................................................................................................................................8
TABLE 6. LEDS ............................................................................................................................................................................9
TABLE 7. POWER AND GROUND ...................................................................................................................................................9
TABLE 8. GPO PIN .......................................................................................................................................................................9
TABLE 9. LED SELECT (IO REGISTER OFFSET 18H~19H) ..........................................................................................................11
TABLE 10. CUSTOMIZED LEDS ...................................................................................................................................................11
TABLE 11. FIXED LED MODE .....................................................................................................................................................11
TABLE 12. LED FEATURE CONTROL-1........................................................................................................................................12
TABLE 13. LED FEATURE CONTROL-2........................................................................................................................................12
TABLE 14. LED OPTION 1 & OPTION 2 SETTINGS .......................................................................................................................12
TABLE 15. LED BLINKING FREQUENCY CONTROL (IO OFFSET 1AH) .........................................................................................13
TABLE 16. L1.OFF AND L1.SNOOZE PCIE PORT CIRCUIT ON/OFF ..............................................................................................20
TABLE 17. POWER SEQUENCE PARAMETERS ...............................................................................................................................22
TABLE 18. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................24
TABLE 19. RECOMMENDED OPERATING CONDITIONS .................................................................................................................24
TABLE 20. ELECTROSTATIC DISCHARGE PERFORMANCE ............................................................................................................24
TABLE 21. CRYSTAL REQUIREMENTS ..........................................................................................................................................25
TABLE 22. OSCILLATOR REQUIREMENTS ....................................................................................................................................25
TABLE 23. ENVIRONMENTAL CHARACTERISTICS ........................................................................................................................25
TABLE 24. DC CHARACTERISTICS ...............................................................................................................................................26
TABLE 25. REFLOW PROFILE RECOMMENDATIONS .....................................................................................................................27
TABLE 26. DIFFERENTIAL TRANSMITTER PARAMETERS ..............................................................................................................28
TABLE 27. DIFFERENTIAL RECEIVER PARAMETERS .....................................................................................................................29
TABLE 28. REFCLK PARAMETERS .............................................................................................................................................29
TABLE 29. AUXILIARY SIGNAL TIMING PARAMETERS.................................................................................................................33
TABLE 30. ORDERING INFORMATION ..........................................................................................................................................35
List of Figures
FIGURE 1. FUNCTION BLOCK DIAGRAM .......................................................................................................................................4
FIGURE 2. RTL8111H PIN ASSIGNMENTS ....................................................................................................................................5
FIGURE 3. RTL8111HS PIN ASSIGNMENTS ..................................................................................................................................6
FIGURE 4. LED BLINKING FREQUENCY EXAMPLE .....................................................................................................................13
FIGURE 5. POWER SEQUENCE .....................................................................................................................................................22
FIGURE 6. SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING ..................................................31
FIGURE 7. SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT ...........................................................................31
FIGURE 8. SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING ........................................................31
FIGURE 9. DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD ....................................................................32
FIGURE 10. DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME ...........................................................................32
FIGURE 11. DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK ............................................................................................32
FIGURE 12. REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING .........................................................................33
FIGURE 13. AUXILIARY SIGNAL TIMING ......................................................................................................................................33
Integrated 10/100/1000M Ethernet Controller for PCI Express v Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
1. General Description
The Realtek RTL8111H-CG/RTL8111HS-CG 10/100/1000M Ethernet controller combines a triple-speed
IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI
Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode
signal technology, the RTL8111H/RTL8111HS offers high-speed transmission over CAT 5 UTP cable or
CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection and Auto-Correction, polarity
correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error
correction are implemented to provide robust transmission and reception capability at high speeds.
The RTL8111H/RTL8111HS supports the PCI Express 1.1 bus interface for host communications with
power management, and complies with the IEEE 802.3u specification for 10/100Mbps Ethernet and the
IEEE 802.3ab specification for 1000Mbps Ethernet. It supports an auxiliary power auto-detect function,
and will auto-configure related bits of the PCI power management registers in PCI configuration space.
The RTL8111H/RTL8111HS features embedded One-Time-Programmable (OTP) memory. The
RTL8111H provides a built-in LDO regulator, and the RTL8111HS provides a built-in switching
regulator.
In addition to the ACPI feature, remote wake-up (including AMD Magic Packet and Microsoft Wake-Up
Frame) is supported in both ACPI and APM (Advanced Power Management) environments. To support
WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary exists), the
auxiliary power source must be able to provide the needed power for the RTL8111H/RTL8111HS. To
further reduce power consumption, the RTL8111H/RTL8111HS also supports PCIe L1.Off and
L1.Snooze.
The RTL8111H/RTL8111HS supports ‘RealWoW!’ technology that enables remote wake-up of a sleeping
PC through the Internet. This feature allows PCs to reduce power consumption by remaining in low
power sleeping state until needed.
Note: The ‘RealWoW!’ service requires registration on first time use.
The RTL8111H/RTL8111HS supports Protocol offload. It offloads some of the most common protocols to
NIC hardware in order to prevent spurious wake-up and further reduce power consumption. The
RTL8111H/RTL8111HS can offload ARP (IPv4) and NS (IPv6) protocols while in the D3 power saving
state.
Integrated 10/100/1000M Ethernet Controller for PCI Express 1 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
The RTL8111H/RTL8111HS supports the ECMA (European Computer Manufacturers Association) proxy
for sleeping hosts standard. The standard specifies maintenance of network connectivity and presence via
proxies in order to extend the sleep duration of higher-powered hosts. It handles some network tasks on
behalf of the host, allowing the host to remain in sleep mode for longer periods. Required and optional
behavior of an operating proxy includes generating reply packets, ignoring packets, and waking the host.
The RTL8111H/RTL8111HS supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet
(EEE). IEEE 802.3az-2010 operates with the IEEE 802.3 Media Access Control (MAC) sublayer to
support operation in Low Power Idle mode. When the Ethernet network is in low link utilization, EEE
allows systems on both sides of the link to save power.
The RTL8111H/RTL8111HS is fully compliant with Microsoft NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP)
Checksum and Segmentation Task-offload (Large send and Giant send) features, and supports IEEE 802
IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above
features contribute to lowering CPU utilization, especially benefiting performance when in operation on a
network server.
The RTL8111H/RTL8111HS supports Receive-Side Scaling (RSS) to hash incoming TCP connections
and load-balance received data processing across multiple CPUs. RSS improves the number of
transactions per second and number of connections per second, for increased network throughput.
The device features inter-connect PCI Express technology. PCI Express is a high-bandwidth,
low-pin-count, serial, interconnect technology that offers significant improvements in performance over
conventional PCI and also maintains software compatibility with existing PCI infrastructure.
The RTL8111H/RTL8111HS is suitable for multiple market segments and emerging applications, such as
desktop, mobile, workstation, server, communications platforms, and embedded applications.
Integrated 10/100/1000M Ethernet Controller for PCI Express 2 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
2. Features
Hardware LAN disable with GPIO pin
Integrated 10/100/1000M transceiver Supports LTR (Latency Tolerance
Reporting)
Supports Giga Lite (500M) mode
Wake-On-LAN and ‘RealWoW!’
Auto-Negotiation with Next Page capability Technology (remote wake-up) support
Supports PCI Express 1.1 Supports 32-set 128-byte Wake-Up Frame
Supports pair swap/polarity/skew correction pattern exact matching
Crossover Detection & Auto-Correction Supports Microsoft WPI (Wake Packet
Indication)
Supports 1-Lane 2.5Gbps PCI Express Bus
Supports PCIe L1.Off and L1.Snooze
Embedded OTP memory
IEEE
Supports hardware ECC (Error Correction
Code) function Fully compliant with IEEE 802.3,
IEEE 802.3u, IEEE 802.3ab
Supports hardware CRC (Cyclic
Redundancy Check) function Supports IEEE 802.1P Layer 2 Priority
Encoding
Transmit/Receive on-chip buffer support
Supports IEEE 802.1Q VLAN tagging
Supports PCI MSI (Message Signaled
Interrupt) and MSI-X Supports IEEE 802.3az-2010 (EEE)
Supports 25MHz or 48MHz Oscillator Supports Full Duplex flow control
(IEEE 802.3x)
Built-in switching (RTL8111HS) and LDO
(RTL8111H) regulator Software Offload
Supports power down/link down power Microsoft NDIS5, NDIS6 Checksum
saving/PHY disable mode Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send v1
Customized LEDs
and Large send v2) support
Controllable LED Blinking Frequency and
Supports jumbo frame to 9K bytes
Duty Cycle
Supports quad core Receive-Side Scaling
32-pin QFN ‘Green’ package
(RSS)
Supports EMAC-393 ECMA ProxZzzy
Supports Protocol Offload (ARP & NS)
Standard for sleeping hosts
XTAL-Less Wake-On-LAN
3. System Applications
PCI Express 10/100/1000M Ethernet on Motherboard, Notebook, or Embedded systems
Integrated 10/100/1000M Ethernet Controller for PCI Express 3 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 4 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
5. Pin Assignments
5.1. RTL8111H Pin Assignments
LANWAKEB
ISOLATEB
VDDREG
REGOUT
PERSTB
DVDD10
HSON
HSOP
24 23 22 21 20 19 18 17
LED 2 25 16 REFCLK _N
LED0 27
REALTEK 14 HSIN
CKXTAL1 28 13 HSIP
8111H
CKXTAL2 29
LLLLLLL 12 CLKREQB
AVDD10 30 11 AVDD33
GXXXV
RSET 31 10 MDIN3
33 GND ( Exposed Pad )
AVDD33 32 9 MDIP3
1 2 3 4 5 6 7 8
AVDD10
AVDD10
MDIN0
MDIN1
MDIN2
MDIP0
MDIP1
MDIP2
Integrated 10/100/1000M Ethernet Controller for PCI Express 5 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 6 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
6. Pin Descriptions
The signal type codes below are used in the following tables:
O: Output P: Power
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RTL8111H/RTL8111HS
Datasheet
6.4. Clock
Table 4. Clock
Symbol Type Pin No Description
CKXTAL1 I 28 Input of 25MHz or 48MHz Clock Reference.
Input of External Clock Source.
CKXTAL2 IO 29
Output of 25MHz or 48MHz Clock Reference.
Integrated 10/100/1000M Ethernet Controller for PCI Express 8 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
6.6. LEDs
Table 6. LEDs
Symbol Type Pin No Description
LED0 O 27 See Section 7.2 Customizable LED Configuration, Page 11 for Details.
LED1/GPO O 26
LED2 O 25
Note 1: During power down mode, the LED signals are logic high.
Note 2: The LED1 pin can be changed to a GPO pin. The setting is changed from the register. Only one function (LED1
or GPIO) may be selected at one time (Default: LED1). For GPO function details, see section 6.8 GPO Pin, page 9.
Integrated 10/100/1000M Ethernet Controller for PCI Express 9 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
7. Functional Description
7.1. PCI Express Bus Interface
The RTL8111H/RTL8111HS complies with PCI Express Base Specification Revision 1.1, and runs at a
2.5GHz signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The
RTL8111H/RTL8111HS supports four types of PCI Express messages: interrupt messages, error
messages, power management messages, and hot-plug messages. To ease PCB layout constraints, PCI
Express lane polarity reversal is supported.
Integrated 10/100/1000M Ethernet Controller for PCI Express 10 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 11 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 12 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 13 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 14 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 15 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Magic Packet Wake-Up occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8111H/RTL8111HS,
e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8111H/RTL8111HS.
• The received Magic Packet does not contain a CRC error.
• The RTL8111H/RTL8111HS driver has set up the needed registers (automatically set), and the
corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current
power state.
• The Magic Packet pattern matches, i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID)
in any part of a valid Ethernet packet.
A Wake-Up Frame event occurs only when the following conditions are met:
• The destination address of the received Wake-Up Frame is acceptable to the RTL8111H/RTL8111HS,
e.g., a broadcast, multicast, or unicast address to the current RTL8111H/RTL8111HS.
• The received Wake-Up Frame does not contain a CRC error.
• The RTL8111H/RTL8111HS driver has set up the needed registers (automatically set).
• The 16-bit CRC of the received Wake-Up Frame matches the 16-bit CRC of the sample Wake-Up
Frame pattern given by the local machine’s OS. Or, the RTL8111H/RTL8111HS is configured to
allow direct packet wake-up, e.g., a broadcast, multicast, or unicast network packet.
• The 128 bytes of the received Wake-Up Frame exactly matches the 128 bytes of the sample Wake-Up
Frame pattern given by the local machine’s OS.
Note 1: 16-bit CRC: The RTL8111H/RTL8111HS supports 32-set 16-bit CRC Wake-Up Frames (covering
128 mask bytes from offset 0 to 127 of any incoming network packet).
CRC16 polynomial=x16+x12+x5+1.
Note 2: 128-byte Wake-Up Frame: The RTL8111H/RTL8111HS supports 32-set 128-byte Wake-Up
Frames. If enabled, the 16-bit CRC Wake-Up match will be disabled.
The corresponding wake-up method (message or LANWAKEB) is asserted only when the following
conditions are met:
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8111H/RTL8111HS may assert the corresponding wake-up method (message or
LANWAKEB) in the current power state or in isolation state, depending on the PME_Support
(bit15~11) setting of the PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wake-Up Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears
this bit and causes the RTL8111H/RTL8111HS to stop asserting the corresponding wake-up method
(message or LANWAKEB) (if enabled).
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RTL8111H/RTL8111HS
Datasheet
When the RTL8111H/RTL8111HS is in power down mode, e.g., D1~D3, the IO, and MEM accesses to
the RTL8111H/RTL8111HS are disabled. After a PERSTB assertion, the device’s power state is restored
to D0 automatically if the original power state was D3cold. There is almost no hardware delay at the
device’s power state transition. When in ACPI mode, the device does not support PME (Power
Management Enable) from D0 (this is the Realtek default setting). The setting may be changed from the
eFUSE, if required.
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RTL8111H/RTL8111HS
Datasheet
BaseCPUNumber
The lowest number CPU to use for RSS. BaseCPUNumber is added to the result of the indirection table
lookup.
Secret Hash Key
The key used in the Toeplitz function. For different hash types, the key size is different.
Integrated 10/100/1000M Ethernet Controller for PCI Express 18 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 19 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 20 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 21 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Rt1
3.3V
2.5~2.6V
1.0V (REGOUT)
0V
Rt3 Rt2
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RTL8111H/RTL8111HS
Datasheet
If there is any action that involves consecutive ON/OFF toggling of the switching regulator source
(3.3V), the design must make sure the OFF state of both the switching regulator source (3.3V) and output
(1.0V) reach 0V, and the time period between the consecutive ON/OFF toggling action must be longer
than 50ms.
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RTL8111H/RTL8111HS
Datasheet
11. Characteristics
11.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the
device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise
specified.
Table 18. Absolute Maximum Ratings
Symbol Description Minimum Maximum Unit
AVDD33 Supply Voltage 3.3V -0.3 3.6 V
AVDD10, DVDD10 Supply Voltage 1.0V -0.3 1.2 V
3.3V DCinput Input Voltage
-0.3 3.6 V
3.3V DCoutput Output Voltage
1.0V DCinput Input Voltage
-0.3 1.2 V
1.0V DCoutput Output Voltage
N/A Storage Temperature -55 +125 °C
Note: Refer to the most updated schematic circuit for correct configuration.
Integrated 10/100/1000M Ethernet Controller for PCI Express 24 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 25 Track ID: JATR-8275-15 Rev. 1.0
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Datasheet
11.7. DC Characteristics
Table 24. DC Characteristics
Symbol Parameter Conditions Minimum Typical Maximum Units
3.3V Supply Mean
AVDD33 - 3.14 3.3 3.46 V
Voltage
AVDD10, 1.0V Supply Mean
- 0.95 1.0 1.05 V
DVDD10 Voltage
Minimum High Level
Voh Ioh = -4mA 0.9*VDD33 - VDD33 V
Output Voltage
Maximum Low Level
Vol Iol = 4mA 0 - 0.1*VDD33 V
Output Voltage
Minimum High Level
Input Voltage for 3.3V - 2.0 - - V
only Pinout
Vih
Minimum High Level
Input Voltage for 3.3V & - 1.62 - - V
1.8V compatible Pinout
Maximum Low Level
Vil - - - 0.8 V
Input Voltage
Iin Input Current Vin = VDD33 or GND 0 - 0.5 µA
Average Operating Supply
Current from 3.3V (does At 1Gbps with heavy
Icc33 - TBD - mA
NOT include 1.0V power network traffic
consumption)
Average Operating Supply At 1Gbps with heavy
Icc10 - TBD - mA
Current from 1.0V network traffic
Average Operating Supply
Current for total system At 1Gbps with heavy
Isys33 - Note3 - mA
3.3V (includes 1.0V network traffic
power consumption)
Note 1: Refer to the latest schematic circuit for correct configuration.
Note 2: All Supply Mean Voltage power noise <±5% of Mean Voltage.
Note 3: The total operating current Isys33=Icc33 + (Icc10 / efficiency / 3.3),
Where efficiency=0.75 for SWR-mode or efficiency=0.33 for LDO-mode.
Integrated 10/100/1000M Ethernet Controller for PCI Express 26 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 27 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 28 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 29 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 30 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Figure 6. Single-Ended Measurement Points for Absolute Cross Point and Swing
Figure 8. Single-Ended Measurement Points for Rise and Fall Time Matching
Integrated 10/100/1000M Ethernet Controller for PCI Express 31 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Figure 10. Differential Measurement Points for Rise and Fall Time
Integrated 10/100/1000M Ethernet Controller for PCI Express 32 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 33 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
Integrated 10/100/1000M Ethernet Controller for PCI Express 34 Track ID: JATR-8275-15 Rev. 1.0
RTL8111H/RTL8111HS
Datasheet
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