ESC-391 ADE Manual

Analog & Digital
Electronics Laboratory
(ESC-391)
LABORATORY MANUAL
DEPARTMENT OF ELECTRONICS &

COMMUNICATION ENGINEERING
COLLEGE OF ENGINEERING AND

MANAGEMENT, KOLAGHAT.
College of Engineering and Management, Kolaghat.
ESC-391: Analog & Digital Electronics Laboratory
LIST OF CONTENTS
Contents Page
No.
Syllabus i
Guidelines for Laboratory Note Book ii
Experiment # 1 Design a Class A amplifier 1-2
Experiment # 2 Design a Phase-Shift Oscillator 3-4
Experiment # 3 Design of a Schmitt Trigger using 555 timer 5-7

Design a Full Adder using basic gates and verify its
Experiment # 4 8 - 12
output.
Construction of simple Decoder & Multiplexer
circuits using logic gates
Experiment # 6 Realization of RS / JK / D flip flops using logic gates 18 - 23
Design a 4-Bit Serial In - Parallel Out Shift Register
using D Flip Flop
Experiment # 8 Realization of Synchronous Up/Down counter 27 - 30
Experiment # 9 Design of MOD - 8 Counter 31 - 32
Experiment # 10 Study of DAC 33 - 34
Department of Electronics & Communication Engineering

SYLLABUS
Analog Electronics
1. Design a Class A amplifier
2. Design a Phase-Shift Oscillator
3. Design of a Schmitt Trigger using 555 timer
Digital Electronics
4. Design a Full Adder using basic gates and verify its output / Design a Full
Subtractor circuit using basic gates and verify its output.
5. Construction of simple Decoder & Multiplexer circuits using logic gates.
6. Realization of RS / JK / D flip flops using logic gates
7. Design of Shift Register using J-K / D Flip Flop
8. Realization of Synchronous Up/Down counter
9. Design of MOD- N Counter
10. Study of DAC
Page |i Department of Electronics & Communication Engineering

GUIDELINES FOR LABORATORY NOTEBOOK
The laboratory notebook is a record of all work pertaining to the experiment.

Organization in notebook is important. Descriptive heading should be used to
separate and identify the various parts of the experiment. A neat, organized and
complete record of an experiment is just as important as the experimental work.
1. Heading: The experiment identification (number) should be at the top of each

page.
2. Title: The name of the experiment.
3. Aim: A brief but complete statement of what to find out or verify in the
experiment should be at the beginning of each experiment.
4. Theory: A brief theory of the experiment should be written in report.
5. Procedure: How to perform the experiment. In general, lengthy explanations
of procedure are unnecessary. Short commentaries alongside the data may be
used.
6. Graphs / Waveform / Figures: Figures are used to present large amounts of
data in concise visual form. Each curve if more than one on a graph should be
labelled.
7. Results: The results should be presented in a form which makes the
interpretation easy. Theoretical and experimental results should be on the
same graph or arrange in the same table in a way for easy correlation of these
results.
8. Conclusion: This is the interpretation of results of the experiment as an
engineer or designer and should be brief and specific.
P a g e | ii Department of Electronics & Communication Engineering

Experiment # 1
TITLE: DESIGN A CLASS A AMPLIFIER
AIM
To design and test the class A power amplifier
THEORY
In a Class A amplifier, If the collector current flows at all times during the full cycle of the
input signal, the power amplifier is known as class A power amplifier. It conducts all of
the time, even for very small signals, or when no signal is present. As the output device is
always conducting this current represents a loss of power in the amplifier. The maximum
theoretical efficiency that a class A amplifier can achieve is 50% efficiency with inductive
output coupling or just 25% with capacitive coupling. In practice, the actual figures
obtained are much less than this for a variety of reasons including circuit losses and the
fact that waveforms do not normally remain at their maximum values, where the
maximum efficiency levels are achieved.
Accordingly, the Class A amplifier provides a linear output with the lowest distortion, but
it also has the lowest efficiency level.
COMPONENTS / APPARATUS REQUIRED
 Trainer kit
 CRO
 Multimeter
CIRCUIT DIAGRAM
Page |1 Department of Electronics & Communication Engineering

PROCEDURE
1. Switch ON Class-A power amplifier.
2. Set input voltage (50 to 100 mV), at 1 kHz using a signal generator and observe
the output voltage.
3. By keeping the input voltage constant, vary the frequency from 0 to 1 MHz in the
regular step.
4. Note down the corresponding output voltage from CRO.
5. Calculate the DC input power using the formula Pdc = VccIc
6. Calculate the AC output power using the formula Pac = Vo(p-p)2/8RL
7. Calculate the efficiency η = (Pac / Pdc)*100
8. Plot the graph between Gain [Gain in dB = 20log (Vo/Vi)] and frequency.
9. Calculate bandwidth from the graph.
EXPERIMENTAL DATA
Data table for bandwidth

Input
Applied Output Gain in dB =
voltage Vi
frequency voltage Vo 20log (Vo/Vi)
(constant)
RESULT
Gain and frequency as observed of Class A amplifier.
Efficiency η = (Pac / Pdc)*100 =

Experiment # 2
TITLE: PHASE SHIFT OSCILLATOR USING OPAMP
AIM
To design an RC Phase Shift oscillator using op-amp for a given frequency of 1 kHz.
THEORY
An oscillator is a circuit that produces a periodic waveform on its output with only the dc
supply voltage as a required input. A repetitive input signal is not required but is
sometimes
used to synchronize oscillations. The output voltage can be either sinusoidal or non-
sinusoidal, depending on the type of oscillator.
RC phase-shift oscillator is a linear electronic oscillator circuit that produces a sine wave
output. It consists of an inverting amplifier element such as a transistor or op-amp with
its
output fed back to its input through a phase-shift network consisting of resistors and
capacitors in a ladder network. Each of the three RC networks in the feedback loop can
provide a maximum phase shift approaching 90 degrees. Oscillation occurs at the
frequency where the total phase shift through the three RC networks is 180 degrees.
Inversion output at the output of op-amp itself produces the additional 180 degree to
meet the requirement for oscillation of 360 degrees (or zero degree) phase shift around
the feedback loop. The attenuation B of the three section RC feedback network is B =
1/29.
DESIGN
Given frequency, f = 1 kHz. We have =

√
Assume C = 0.1μF.
1 1
= = = 650 Ω
2 √6 2 X 10 X 0.1 X 10 X √6
Select the nearest value of 680Ω for R
R1 = 10R = 6497Ω ≈ 6.5KΩ, Select nearest value of 6.8KΩ for R1
Rf = ACL X R1 = 29 X 6.8 X 103 = 197.2 KΩ, Select the value of 220 KΩ or 1 MΩ for Rf
for a stable result
 Op-Amp IC: LM741

 Resistor: (6.8 KΩ – 1 no, 680Ω – 3 nos, 220 KΩ – 1 no)
 Capacitor: (0.1 µF – 3 nos)
 Oscilloscope

CIRCUIT DIAGRAM
RESULT
An RC phase shift oscillator was designed for a frequency of 1 kHz.
The observed frequency is _______________ kHz
What is Phase and Phase Shift?
Phase is a full cycle period of a sinusoidal wave in a 360-degree reference. A complete

cycle is defined as the interval required for the waveform to return its arbitrary initial
value. Phase is denoted as a pointed position on this waveform cycle. If we see the
sinusoidal wave we can easily identify the phase

Experiment # 3
TITLE: SCHMITT TRIGGER USING 555 TIMER
AIM
To design and construct a Schmitt trigger using IC 555 Timer.
THEORY
The high and low transitions on the inputs of most of the CMOS devices should be fast
edges. If the edges are not fast enough, they tend to provide more current and this might
damage the device. Analog signals are generally not perfect and might not have clean
edges all the time. Schmitt Trigger is a special type of comparator that is used to avoid
such signals.
The important characteristic of the Schmitt trigger is Hysteresis. The output of the
Schmitt trigger is high if the input voltage is greater than the upper threshold value and
the output of the Schmitt trigger is low if the input voltage is lower than the lower
threshold value.
The output retains its value when the input is between the two threshold values. The
usage of two threshold values is called Hysteresis and the Schmitt trigger acts as a
memory element (a bistable multivibrator or a flip-flop).
The threshold values are 2/3 VCC and 1/3 VCC i.e. the upper comparator trips at 2/3 VCC
and the lower comparator trips at 1/3 VCC. The input voltage is compared to these
threshold values by the individual comparators and the flip-flop is SET or RESET
accordingly. Based on this the output becomes high or low.
When a sine wave of amplitude (>2/3 VCC) is applied at the input, the flip-flop is set and
reset alternately for the positive cycle and the negative cycle. The output is a square
wave and the waveforms for the input sine wave and output square wave are shown.

 IC555 -1 No
 Resistors (100 KΩ-2 Nos, 1 KΩ-1No.)
 Capacitors (0.1 µF, 0.01 µF)
 Trainer kit
 Multimeter
 CRO
CIRCUIT DIAGRAM
PROCEDURE:
1. Initially set +VCC = 12 volts.
2. As shown in the circuit diagram connect the circuit for Schmitt Trigger on
breadboard.
3. Apply the input sine wave with peak voltage greater than the designed voltage
(upper threshold) using function generator.
4. Connect the channel-1 of CRO at the input terminals and Channel-2 at the output
terminals.
5. Observe the output square waveform corresponding to input sinusoidal signal.
6. Overlap both the input and output waves and note down voltages at positions on
sine wave where output changes its state. These voltages denote the Upper
threshold voltage and the Lower threshold voltage.
7. Verify that these practical threshold voltages are almost same as the theoretical
Threshold voltages calculated using formula.
8. Sketch/Trace the waveforms on graph paper by noting down the amplitude and
the time period of the input Vin and the output Vo.

RESULT

Experiment # 4
TITLE: FULL ADDER AND FULL SUBTRACTOR CIRCUIT USING BASIC GATES
AIM
Design a Full Adder and Full Subtractor circuit using basic gates and verify the truth
tables.
COMPONENTS REQUIRED:
IC 7404, IC 7408, IC 7486, and IC 7432, Patch chords and Trainer Kit.
FULL ADDER
THEORY
Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are
A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and
the normal output is designated as S which is SUM. Full adder logic is designed in such a manner
that can take eight inputs together to create a byte-wide adder and cascade the carry bit from
one adder to another. We use a full adder because when a carry-in bit is available, another 1-bit
adder must be used since a 1-bit half-adder does not take a carry-in bit. A 1-bit full adder adds
three operands and generates 2-bit results.
A SUM
Full
B Adder
C-Out
C-IN
CIRCUIT DIAGRAM

TRUTH TABLE
INPUTS OUTPUTS
A B C-IN SUM C-Out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logical Expression for SUM: = A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN = C-IN (A’ B’ +
A B) + C-IN’ (A’ B + A B’) = C-IN XOR (A XOR B) = (1, 2, 4, 7)
Boolean expression: SUM = A ⊕ B ⊕ C-IN
K-map Simplification for output SUM ‘S’:
The equation obtained is,

S = A'B'C-IN + AB'C-IN' + ABC + A'BC-IN'
The equation can be simplified as,
S = B'(A'C-IN+AC-IN') + B(AC + A'C-IN')
S = B'(A xor C-IN) + B (A xor C-IN)'
S = A xor B xor C-IN

Logical Expression for C-Out: = A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN = A B + B C-IN +

A C-IN = (3, 5, 6, 7)
Boolean expression: C-Out = A B + B C-IN + A C-IN
K-map Simplification for output variable ‘C-Out‘
The equation obtained is,

C-Out = B C-IN + A B + A C-IN
FULL SUBTRACTOR
THEORY
A full subtractor is a combinational circuit that performs subtraction involving three bits, namely
A (minuend), B (subtrahend), and Bin (borrow-in). It accepts three inputs: A (minuend), B
(subtrahend), and a B-in (borrow bit) and it produces two outputs: D (difference) and B-out
(borrow out). The logic symbol and truth table are shown below
A D (difference)
Full
B Subtractor
B-out
B-in
P a g e | 10 Department of Electronics & Communication Engineering

CIRCUIT DIAGRAM
TRUTH TABLE
INPUTS OUTPUTS
A B B-in DIFFERENCE(D) B-out
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Logical expression for difference (D):

D = A’B’B-in + A’BB-in’ + AB’B-in’ + ABB-in
= B-in (A’B’ + AB) + B-in’ (AB’ + A’B)
= B-in (A XNOR B) + B-in’ (A XOR B)
= B-in (A XOR B)’ + B-in’ (A XOR B)
= B-in XOR (A XOR B)
= (A XOR B) XOR B-in
Boolean expression: DIFFERENCE (D) = A ⊕ B ⊕ B-in

Logical expression for borrow:

B-out = A’B’B-in + A’BB-in’ + A’BB-in + ABB-in
= A’B’B-in +A’BB-in’ + A’BB-in + A’BB-in + A’BB-in + ABB-in
= A’B-in (B + B’) + A’B (B-in + B-in’) + BB-in (A + A’)
= A’B-in + A’B + BB-in
Boolean expression: B-out = A’B-in + A’B + BB-in
PROCEDURE
 Check the components for their working

 Insert the appropriate IC into the breadboard
 Make connections as shown in the circuit diagram.
 Verify the Truth Tables and observe the outputs.
RESULT/OBSERVATION
Full Adder and Full Subtractor circuits were constructed using basic gates and values of
the truth tables were also verified.

Experiment # 5
TITLE: CONSTRUCTION OF SIMPLE DECODER & MULTIPLEXER CIRCUITS USING
LOGIC GATES
AIM
To construct simple Decoder & Multiplexer circuits using logic gates and verify the truth
tables
IC 7404, IC 7408, IC 7411, IC 4072, Patch chords, and Trainer Kit.
DECODER
THEORY
The name “Decoder” means to translate or decode coded information from one format
into another, so a digital decoder transforms a set of digital input signals into an
equivalent decimal code at its output
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of m = 2n unique output lines.
Q
A
2X4 Binary Q Output
Input
Decoder Q
B
Q
The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic
level “1” while the remaining outputs are held “LOW” at logic “0” so only one output can
be active (HIGH) at any one time. Therefore, whichever output line is “HIGH” identifies
the binary code present at the input, in other words, it “decodes” the binary input. Some
binary decoders have an additional input pin labeled “Enable” that controls the outputs
from the device.

This extra input allows the decoder's outputs to be turned “ON” or “OFF” as required.
Output is only generated when the Enable input has a value of 1; otherwise, all outputs
are 0. Only a small change in the implementation is required: the Enable input is fed into
the AND gates which produce the outputs.
If Enable is 0, all AND gates are supplied with one of the inputs as 0 and hence no output
is produced. When Enable is 1, the AND gates get one of the inputs as 1, and now the
output depends upon the remaining inputs. Hence the output of the decoder is
dependent on whether the Enable is high or low.
CIRCUIT DIAGRAM OF 2-TO-4 DECODER
TRUTH TABLE OF 2-TO-4 DECODER

MULTIPLEXER
THEORY
A digital multiplexer is similar to a multi-position switch with many inputs and only one
output. It has control inputs to select a particular input. Multiplexer is a data selector
that provides the mechanism to select single binary information from many input lines
and passes it to the output line. It is also called a channel selector and abbreviated as
Mux. A multiplexer has m select lines, 2m inputs, and only one output as shown in the
figure. Commercially, multiplexers ICs (integrated circuits) are available in powers of 2,
e.g. 2:1, 4:1, 8:1, and 16:1 Mux
To construct a 4 to 1 multiplexer 22 that gives 4 input lines and 2 selection lines are
required.

CIRCUIT DIAGRAM OF 4:1 MULTIPLEXER
OR
TRUTH TABLE OF 4:1 MULTIPLEXER
S0 S1 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

CIRCUIT DIAGRAM OF 2:1 MULTIPLEXER
Y = I0S +
TRUTH TABLE OF 2:1 MULTIPLEXER
S Y
0 I0
1 I1
PROCEDURE

RESULT/OBSERVATION
Decoder & Multiplexer circuits were constructed using logic gate ICs and values of the
truth table were also verified.

Experiment # 6
TITLE: REALIZATION OF RS / JK / D FLIP FLOPS USING LOGIC GATES
AIM
To construct and realize RS / JK / D flip-flops circuits using logic gates and verify the truth
tables
IC 7400, IC 7410, Patch chords, and Trainer Kit.
RS FLIP-FLOP
THEORY
The simplest kind of sequential circuit which is capable of storing one bit of information is called
latch. The operation of basic latch can be modified, by providing an additional control input that
determines when the state of the circuit is to be changed. The latch with additional control input
is called the Flip-Flop. The additional control input is either the clock or enable input. Clock signal
controls the instant at which flip flop changes the state. Whenever the clock signal is LOW, the
inputs S and R are never going to affect the output. The clock has to be high for the inputs to get
active. Thus, SR flip-flop is a controlled Bi-stable latch where the clock signal is the control signal.
There are majorly 4 types of flip-flops, with the most common one being RS flip-flop. This simple
flip-flop circuit has a set input (S) and a reset input (R). In this system, when Set (S) as active the
output Q would be high and Q‘ will be low. Once the outputs are established, the wiring of the
circuit is maintained until S or R go high, or power is turned off.
NAND-based S-R Flip-Flop:

CIRCUIT DIAGRAM OF S-R FLIP-FLOP
TRUTH TABLE OF S-R FLIP-FLOP
Sl. No. clock S R Q(n-1) Q(n-1) Q Q Remark

1 0 0 0 X X 0 1
2 1 0 0 0 1 0 1 No change
3 1 0 1 0 1 0 1 Reset
4 1 1 0 0 1 1 0 Set
5 1 1 1 1 0 0 0 INVALID
CLOCK DIAGRAM

JK FLIP-FLOP
THEORY
The name JK flip-flop is termed by the inventor Jack Kilby from texas instruments. In an
RS flip-flop, the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit may
be re-joined if both inputs are 1 then also the outputs complement each other and the
advantage is that this has a toggling function.
One of the most useful and versatile flip-flops is the JK flip-flop the unique features of a
JK flip-flop are:
1. If the J and K input are both at 1 and the clock pulse is applied, then the output
will change state, regardless of its previous condition.
2. If both J and K inputs are at 0 and the clock pulse is applied there will be no
change in the output. There is no indeterminate condition in the operation of the
JK flip-flop i.e. it has no ambiguous state.
Operation:
When J = 0 and K = 0
When both J and K inputs are at 0, these J and K inputs disable the NAND gates, therefore
clock pulse does not affect the flip-flop. In other words, Q returns its last value.
The upper NAND gate is disabled the lower NAND gate is enabled if Q is 1 therefore, the
flip flop will be reset (Q = 0, Q =1) if not already in that state.
The lower NAND gate is disabled and the upper NAND gate is enabled if Q is at 1, As a
result, we will be able to set the flip flop (Q = 1, Q = 0) if not already set.
If Q = 0 the lower NAND gate is disabled the upper NAND gate is enabled. This will set
flip-flop and hence Q will be 1. On the other hand If Q = 1 the lower NAND gate is
enabled and flip-flop will be reset and hence Q will be 0. In other words, when J and K are
both high, the clock pulse causes the JK flip-flop to toggle.

CIRCUIT DIAGRAM OF J K FLIP-FLOP
TRUTH TABLE OF JK FLIP-FLOP
Sl. No. Clock J K Q(n-1) Q(n-1) Q Q Remark

1 0 0 0 X X 0 1 Latched
2 1 0 0 0 1 0 1 No change
3 1 0 1 0 1 0 1 Reset
4 1 1 0 0 1 1 0 Set
5 1 1 1 1 0 0 1 Toggles
CLOCK DIAGRAM

D FLIP-FLOP
THEORY
A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop
by connecting the R input through an inverter, and the S input is connected directly to
data input. The modified clocked SR flip-flop is known as D-flip-flop and It ensures that at
the same time, both the inputs, i.e., S and R, are never equal to 1.
Only single data bit, D is required to drive the flip-flop. When clock signal is at low level,
data bit D is prevented to reach at output Q until clock signal becomes high at next pulse.
When data bit D is high, output Q gets at high level and when data bit D is low, output Q
gets at low level. So D flip-flop transfers the data bit D to Q as it is. and Q remains in the
same state until the next pulse of clock arrives.
CIRCUIT DIAGRAM OF D FLIP-FLOP

TRUTH TABLE OF D FLIP-FLOP
Sl. No. clock D Q(n-1) Q'(n-1) Q Q' Remark

1 0 0 X X 0 1 No Change
2 1 0 0 1 0 1 Reset
3 0 1 0 1 0 1 No change
4 1 1 0 1 1 0 Set
CLOCK DIAGRAM
PROCEDURE

RESULT/OBSERVATION
RS / JK / D flip flops circuits were constructed using logic gate ICs and values of the truth
table were also verified.

Experiment # 7
TITLE: DESIGN AND VERIFY THE 4-BIT SERIAL IN - PARALLEL OUT SHIFT REGISTER
AIM
To design and verify a 4-bit serial in - parallel out (SIPO) shift register
COMPONENTS REQUIRED
IC 7474, Patch Cords, and Trainer Kit.
THEORY
Shift registers are a type of sequential logic circuit, mainly used for the storage and
transfer of digital data. They are a group of flip-flops connected in a chain so that the
output from one flip-flop becomes the input of the next flip-flop. All the flip-flops are
driven by a common clock and are set or reset simultaneously.
The serial in/serial out shift register accepts data serially - that is, one bit at a time on a
single line. It produces the stored information on its output also in serial form.
The serial in/parallel out shift register consists of one serial input, and outputs are taken
from all the flip-flop parallel. In this register, data is shifted in serially but shifted out in
parallel. In order to shift the data out in parallel, it is necessary to have all the data
available at the outputs at the same time. Once the data is stored, each bit appears on its
respective output line and all the bits are available simultaneously, rather than on a bit-
by-bit basis as with the serial output.
The parallel in/serial out shift register accepts data in parallel, i.e., the bits are entered
simultaneously into their respective flip-flops rather than on a bit-by-bit basis on one
line. The I/P of the second FF is the 0/P of the first flip-flop. It produces the stored
information on its output also in serial form.
The parallel in/parallel out shift register accepts data in parallel. Data inputs can be
shifted either in or out of the register in parallel. It produces the stored information on its
output in parallel form.

CIRCUIT DIAGRAM OF SERIAL IN/PARALLEL OUT SHIFT REGISTER
TRUTH TABLE OF SERIAL IN/PARALLEL OUT SHIFT REGISTER
Serial No. Clock Data Input Q3 Q2 Q1 Q0

1 1 1 1 0 0 0
2 2 0 0 1 0 0
3 3 1 1 0 1 0
4 4 1 1 1 0 1
CLOCK DIAGRAM
The serial data 1011 pattern is presented at the Serial input. This data is synchronized
with the clock CLK.

On the first clock at t1, the data 1 at Serial input is shifted from D to Q of the first shift
register stage. After t2 this first data bit is at Q2.
After t3 it is in Q1. After t4 it is at Q0. Four clock pulses have shifted the first data bit all the
way to the last stage Q0.
The second data bit a 0 is at Q1 after the 4th clock. The third data bit a 1 is at Q2. The
fourth data bit another 1 is in Q3.
Thus, the serial data input pattern 1011 is contained in (Q0 Q1 Q2 Q3). It is now available
on the four outputs.
It will available on the four outputs from just after clock t4 to just before t5.
PROCEDURE

 Connect the circuit as per the circuit diagram and pin configuration of the ICs.
 Clear all the flip-flops by applying a high signal to the clear (reset) input.
 Feed the data into the Serial mode.
 Observe the output through LED and it's verified with the help of Truth tables.
RESULT/OBSERVATION
4-Bit Serial In - Parallel Out shift Register circuit was constructed using D flip-flop ICs and
values of the truth table were also verified.

Experiment # 8
TITLE: REALIZATION OF SYNCHRONOUS UP/DOWN COUNTER
AIM
To construct and realize a 3-bit synchronous Up/Down counter circuit and verify the
truth table.
IC 7476, IC 7408, IC 7404, IC 7432, Patch chords, and Trainer Kit.
THEORY
A counter in which each flip-flop is triggered by the output goes to the previous flip-flop.
As all the flip-flops do not change states simultaneously in the asynchronous counter,
spikes occur at the output. To avoid this, a strobe pulse is required. Because of the
propagation delay, the operating speed of the synchronous counter is low. This problem
can be solved by triggering all the flip-flops in synchronous with the clock signal and such
counters are called synchronous counters.
“Universal” type of counter that can count in both directions either Up or Down
depending on the state of their input control pin and these are known as Bidirectional
Counters which are capable of counting in either direction through any given count
sequence and they can be reversed at any point within their count sequence by using an
additional control input (M).
The circuit below is of a simple 3-bit Up/Down synchronous counter using JK flip-flops
configured to operate as a toggle or T-type flip-flops giving a maximum count of zero
(000) to seven (111) and back to zero again. Then the 3-Bit counter advances upward in
sequence (0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0).
CIRCUIT DIAGRAM

Decision for Mode control input M

 When M=0, then the counter will perform up counting.
 When M=1, then the counter will perform down counting.
TRUTH TABLE
M Clock Q3 Q2 Q1
0 0 0 0 0
0 1 0 0 1
0 2 0 1 0
0 3 0 1 1
0 4 1 0 0
0 5 1 0 1
0 6 1 1 0
0 7 1 1 1
0 8 0 0 0
1 0 0 0 0
1 1 1 1 1
1 2 1 1 0
1 3 1 0 1
1 4 1 0 0
1 5 0 1 1
1 6 0 1 0
1 7 0 0 1
1 8 0 0 0
STATE TRANSITION DIAGRAM

TIMING DIAGRAM
OPERATION
Here -ve edge-triggered clock pulse is used for toggling purposes.
After every falling edge, when T = 1, the output state of Flip Flop will toggle.
 Initially Q3 = 0 , Q2= 0 , Q1= 0.
Case 1 : When M=0 ,then M’= 1
 T3 = M’Q2Q1 + MQ’2Q’1 = Q2Q1.
 T2 = M’Q1 + MQ’1= 1.Q1= Q1.
 T1= 1.

 Because T1= 1, therefore FF1 output state toggles for every falling edge. The
output state of FF2 will toggle when Q1 = 1 and the falling edge of the clock pulse
occurs. The output state of FF3 will toggle only when Q2.Q1= 1 and the falling
edge of the clock pulse occurs.
 In this way, after every falling edge, state transition takes place and we can get
our desired counting sequence.
Case 2 : When M=1 ,then M’ =0
 T3 = M’Q2Q1+MQ’2Q’1 = Q’2Q’1
 T2 = M’Q1+ MQ’1= 1.Q1= Q’1.
 T1= 1.
 Because T1= 1, therefore FF1 output state toggles for every falling edge. The
output state of FF2 will toggle when Q’1 = 1 and the falling edge of the clock pulse
occurs.
The output state of FF3 will toggle only when Q’2.Q’1= 1 and the falling edge of
the clock pulse occurs.
 In this way, after every falling edge, state transition takes place and we can get
our desired counting sequence.
PROCEDURE
1. Check the components for their working.

2. Rig up the circuit as shown in the circuit diagram.
3. Apply various input data to the logic circuit via the input logic switches.
4. Note down the corresponding output and verify the truth table.
RESULT/OBSERVATION
3-bit Synchronous Up/Down counter circuit was constructed using ICs and the truth table
was verified.

Experiment # 9
TITLE: DESIGN OF MOD- N COUNTER
AIM
To design and implement the circuit of MOD-8 asynchronous counter using J-K flip-flops.
IC 7476, Patch chords, and Trainer Kit.
THEORY
MOD Counters are cascaded counter circuits that count to a set modulus value before
resetting. Modulus Counters, or simply MOD counters, are defined based on the number
of states that the counter will sequence through before returning to its original value.
Mod-N counter is a counter which has states from 0 to N-1 (0 - 1 - 2 - 3- ……. N-1).
To construct a counter with any MOD number, the minimum number of flip-flops
required must satisfy Modulus ≤ 2n, where n is the number of flip-flops.
So for example, a 3 flip-flop counter will have a maximum count of 23 = 8. The number of
different output states a counter can produce is called the modulo of the counter. The
Modulus of a counter is the total number of unique states it passes through in one
complete counting cycle with a mod-n counter being described also as a divide-by-n
counter.
Asynchronous/ripple counters are constructed in such a way that the count pulses in
effect ripple through the FF chain. The output of the first FF is the clock input to the
second. Any state change in the 2nd FF occurs after the 1st FF changes its state. This
continues down the chain. A 3-bit (modulo-8) counter is shown below.
CIRCUIT DIAGRAM

TRUTH TABLE
No. of clock pulses

Q2 Q1 Q0
input to FF0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
TIMING DIAGRAM OF 3-BIT RIPPLE COUNTER
PROCEDURE
1. Make connections as shown in the circuit diagram. The JK FFs are converted to T
FFs by connecting J K inputs of all FFs to 1.
2. Apply clock pulse to clock input to flip-flop FF0. Q0 goes to the clock input of FF1
and Q1 goes to the clock input of FF2 and so on.
3. Put CL and PR high using logic input switches.
4. Verify the count sequences of the Truth Table.
RESULT/OBSERVATION
MOD-8 asynchronous counter circuit was constructed using FF ICs and the count
sequence for each clock input given in the Table was verified.

Experiment # 10
TITLE: STUDY OF DAC
AIM
To design and test a 3-bit R-2R ladder type DAC.

IC 741, Resistor (1 KΩ – 13 nos), Patch chords, Multimeter, and Trainer Kit.
THEORY
A Digital to Analog Converter (DAC) converts a digital input signal into an analog voltage
or current which is proportional to the digital value. The digital signal is represented with
a binary code, which is a combination of bits 0 and 1. It consists of several binary inputs
and a single output.
R-2R Digital-to-Analogue Converter, or DAC, is a data converter that uses two precision
resistors to convert a digital binary number into an analog output signal proportional to
the value of the digital number. A pair of R and 2R is used for one input bit. The digital
inputs are Vref (8 V) for input as 1 and GND for input 0.
CIRCUIT DIAGRAM
CALCULATION OF Vout
Vout = Voltage resolution X D

Where
D = Decimal equivalent of a given binary combination
V R 8 2R 8
Voltage resolution = X − = X − = X (−1) = −1
2 R 2 2R 8
R = Eqivalent resistance at Node N for all combination = 2R

PROCEDURE
1. Make the connection as shown in the circuit diagram

2. Connect the power supply to the board.
3. Connect the logic switches to the converter. The digital inputs will be Vref (8 V) for
input 1 and GND for input 0.
4. Switch the logic switches in binary progression, measure & record the output
voltage in correspondence to every combination of the input code
OBSERVATION TABLE FOR INPUT CODE AND OUTPUT VOLTAGE
Binary Input
Vout(Theoretical) = (-1) X D Vout(Practical)
A B C
0 0 0 (-1) X 0 = 0
0 0 1 (-1) X 1 = -1
0 1 0 (-1) X 2 = -2
0 1 1 (-1) X 3 = -3
1 0 0 (-1) X 4 = -4
1 0 1 (-1) X 5 = -5
1 1 0 (-1) X 6 = -6
1 1 1 (-1) X 7 = -7
RESULT
R-2R Digital-to-Analog Converter circuit was constructed and observations were recorded
in the observation table.

ESC-391 ADE Manual

Uploaded by

Copyright:

Available Formats

ESC-391 ADE Manual

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ESC-391 ADE Manual

Uploaded by

Copyright:

Available Formats

Analog & Digital

DEPARTMENT OF ELECTRONICS &

COLLEGE OF ENGINEERING AND

ESC-391: Analog & Digital Electronics Laboratory

Guidelines for Laboratory Note Book ii

Experiment # 1 Design a Class A amplifier 1-2

Experiment # 2 Design a Phase-Shift Oscillator 3-4

Experiment # 3 Design of a Schmitt Trigger using 555 timer 5-7

Experiment # 9 Design of MOD - 8 Counter 31 - 32

Experiment # 10 Study of DAC 33 - 34

Department of Electronics & Communication Engineering

ESC-391: Analog & Digital Electronics Laboratory

Page |i Department of Electronics & Communication Engineering

ESC-391: Analog & Digital Electronics Laboratory

GUIDELINES FOR LABORATORY NOTEBOOK

The laboratory notebook is a record of all work pertaining to the experiment.

1. Heading: The experiment identification (number) should be at the top of each

P a g e | ii Department of Electronics & Communication Engineering

Page |1 Department of Electronics & Communication Engineering

Data table for bandwidth

Page |2 Department of Electronics & Communication Engineering

Given frequency, f = 1 kHz. We have =

R1 = 10R = 6497Ω ≈ 6.5KΩ, Select nearest value of 6.8KΩ for R1

COMPONENTS / APPARATUS REQUIRED

 Op-Amp IC: LM741

Page |3 Department of Electronics & Communication Engineering

What is Phase and Phase Shift?

Phase is a full cycle period of a sinusoidal wave in a 360-degree reference. A complete

Page |4 Department of Electronics & Communication Engineering

Page |5 Department of Electronics & Communication Engineering

COMPONENTS / APPARATUS REQUIRED

Page |6 Department of Electronics & Communication Engineering

Page |7 Department of Electronics & Communication Engineering

Page |8 Department of Electronics & Communication Engineering

Boolean expression: SUM = A ⊕ B ⊕ C-IN

K-map Simplification for output SUM ‘S’:

The equation obtained is,

Page |9 Department of Electronics & Communication Engineering

Logical Expression for C-Out: = A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN = A B + B C-IN +

Boolean expression: C-Out = A B + B C-IN + A C-IN

K-map Simplification for output variable ‘C-Out‘

The equation obtained is,

P a g e | 10 Department of Electronics & Communication Engineering

Logical expression for difference (D):

Boolean expression: DIFFERENCE (D) = A ⊕ B ⊕ B-in

P a g e | 11 Department of Electronics & Communication Engineering

Logical expression for borrow:

Boolean expression: B-out = A’B-in + A’B + BB-in

 Check the components for their working

P a g e | 12 Department of Electronics & Communication Engineering

IC 7404, IC 7408, IC 7411, IC 4072, Patch chords, and Trainer Kit.

P a g e | 13 Department of Electronics & Communication Engineering

CIRCUIT DIAGRAM OF 2-TO-4 DECODER

TRUTH TABLE OF 2-TO-4 DECODER

P a g e | 14 Department of Electronics & Communication Engineering

P a g e | 15 Department of Electronics & Communication Engineering

CIRCUIT DIAGRAM OF 4:1 MULTIPLEXER

TRUTH TABLE OF 4:1 MULTIPLEXER

P a g e | 16 Department of Electronics & Communication Engineering

CIRCUIT DIAGRAM OF 2:1 MULTIPLEXER