Design and Analysis of Operational Transconductance Amplifier (Ota) Under 180Nm Technology Using Ltspice
Design and Analysis of Operational Transconductance Amplifier (Ota) Under 180Nm Technology Using Ltspice
Design and Analysis of Operational Transconductance Amplifier (Ota) Under 180Nm Technology Using Ltspice
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Abstract— This paper deals with the design and analysis of CMOS operational transconductance amplifier (OTA) under 180nm
technology. The circuit designed operates at ±0.9V power supply and the input relay on the bias current. In this paper, the device
parameters such as gain, phase margin, Gain Bandwidth, ICMR, Slew Rate and power dissipation are theoretically calculated and
analyzed through simulation for the given specifications. Here, the simulation is carried out using LTspice software. The circuit is
compensated by a simplest compensation technique called Miller compensation in which a capacitor is connected across high-gain
stage to improve the unity gain bandwidth under the same load condition. Both the theoretical calculations and the computer aided
simulation analysis are then compared with the given specifications.
Keywords— CMOS operational transconductance amplifier, circuit design, device parameters, LTspice and Miller compensation
I. INTRODUCTION
O ne-stage op amps allow the small-signal current produced by the input pair to flow directly through the output impedance, i.e., they
perform voltage to current conversion only once. The gain of this topology is therefore reduced to the product of the input pair
transconductance and the output impedance. It is also noted that cascoding in such circuits increases the gain while limiting the output
swings. In some implementations, the gain and the output swings given by cascode op amps are not sufficient. In such cases, CMOS op amps
use two or more stages of gain. One of the most popular op amps is OTA. OTA must be carefully examined because it is simple but robust
implementation of op amps and it can be used as the starting point for the development of other types of op amps.
The first stage provides high gain and the second stage provides large swings. In foil to cascode op amps, a two-stage op-amp configuration
separates the gain and swing requirements. The first stage can incorporate various amplifier topologies but the second stage is typically
configured as a simple common-source stage so as to allow maximum output swings. To attain a higher gain, the first stage can integrate
cascode devices.
An amplifier in which all nodes have low impedance excluding the input and output nodes is called as an operational transconductance
amplifier (OTA). An example of OTA is the differential amplifier with current mirror load. An OTA lacking buffer can only steer capacitive
loads. A resistive load will destroy the gain of the OTA.
In the below block diagram, the differential-transconductance stage forms the input of the op amp and sometimes provides the differential to
single-ended conversion. A good portion of the overall gain is provided by this stage and improves noise and offset performance.
The second stage is an inverter. If the differential-input stage does not execute the differential to single-ended conversion, then it is achieved in
the second-stage inverter. If the op amp has to steer a low-resistance load, then the second stage must be implemented by a buffer stage whose
aim is to reduce the output resistance and maintain a large signal swing. Bias circuits are presented to initiate the proper operating point for
each transistor in its quiescent state. Compensation circuitry is required to achieve stable closed-loop performance. The approach of
compensation is to preserve stability when negative feedback is applied around the op amp. The concept of compensation helps us to formulate
a design approach for OTA.
It is of primary important that the signal fed back to the input of the op amp should have such amplitude and phase so that it does not
regenerate itself around the loop. If regeneration occurs, it results in clamping of the output or oscillation. To avoid regeneration and to make
the feedback system stable (i.e., sustain oscillation does not occur), the following conditions must be met.
|L( )| = |A( ) F( )] = 1
The response of |A( ) F( )| & Arg [-A( ) F( )] as a function of frequency and phase can be illustrated using Bode plot
which is shown below
The system is said to be stable when |A( ) F( )| curve crosses 0dB point before Arg [-A ( ) F( )] reaches 0°. Stability
is measure when the phase of |A( ) F( )| curve is unity, 0dB. This is called as Phase Margin and is expressed as
ℎ ( ) = Arg [-A( ) F( )]
= Arg [L( )]
Response of second-order system with various phase margins as a function of time is given in Fig.6a. One can see that with large phase
margin “ringing” of the output signal is less. Too much ringing is undesirable, so it is important to have adequate phase margin. It is advised to
have a phase margin of at least 45°, with 60° is preferable in most situations. Now, consider an uncompensated op amp with negative feedback
and its frequency response is shown in Fig.5b.
Fig. 5a. Response of second-order system with various phase margins Fig. 5b. Open-loop frequency response of uncompensated op amp
with feedback factor F(s) = 1
In the above graph, the phase margin is significantly less than 45°, which means the op amp should be compensated. In common, Miller
compensation is used to compensate OTA’s.
By adding miller capacitor ( ) between the output and the input of the second transconductance stage produceses two results, they are
1. The effective capacitance shunting is increased by the additive amount of approximately ( )( ). This moves
which is the new location of and is closer to the origin of the complex frequency plane.
2. The pole which is the new location of is moved away from the origin of the complex frequency plane.
Note that the zero occurs of the positive-real axis of the complex frequency plane and is due to the feedforward path through . The difference
between uncompensated and compensated system is illustrated in Fig. 7b..
Fig. 7a. Location of poles and zeros Fig. 7b. Magnitude and phase response before and after compensation
From the above plot, note that the second pole does not affect the magnitude until |A( ) F( )| is less than unity. As said before,
the aim of the compensation is to attain phase margin greater than 45°. If the zero is place ten times higher than GB, then in order to achieve
45° phase margin, the pole must be placed atleast 1.22 times higher than GB. In order to achieve 60° of phase margin, must be placed
about 2.2 times higher than GB.
TABLE I
DESIGN SPECIFICATION
Requirements Specification
Gain 60DB
0.9
-0.9
GB 5MHz
10pF
SR 10V/µs
range ±5V
ICMR -0.1V to 0.5V
Power Dissipation ≤ 3mW
Following are the procedure for designing the circuit of Operational Transcondunce Amplifier (OTA) for the above specifications.
i. The design steps begin by choosing device length (L) which is taken as 1µm and is used throughout the circuit. This value will calculate
the channel length modulation parameter λ which is required to determine the amplifier gain.
ii. After choosing the device length, calculate the value of compensation capacitor which ig give as
.
>
.
> (10 )
> 2.2
=3
iii. Next, calculate the minimal value of tail current based on the slew rate requirements. The value of is calculated from the formula
= SR ∗ = (3*10 )(10*10 )
= 30µ
iv. Now, determine the aspect ratio of by following relation
=( / ) = ≥ 1
( ) |( ) ( )
∗
= = 60
( ∗ )[ . . . . ]
( / ) =( / ) = 60
v. The transconductance of the input transistor is determined from the eauation that follows
= ∗ = (5*10 )(2ℼ)(3*10 )
= 94.25 µ
vi. From the above equation, the aspect ratio of and can be directly obtained as
( . µ)
( / ) = ( / ) = =
( ∗ )( ∗ )
( / ) = ( / ) = 2.69 ≈ 3
( ) = ( ) − − − ( ) ≥ 100mV
30 ∗ 10
( ) = −0.1 + 0.9 − − 0.3
110 ∗ 10 ∗ 3
( ) = 0.499
Now,
(( ∗ )
= ( / ) = =
[ ( )] ∗ [ . ]
( / ) = 2.19 ≈ 2.2
= in which ≥ 10 ≥ 942.5µ
. µ
= = 60
µ
= 118.5
viii. Then, determine the value of the currentr through by the following equation
( . µ)
= = = 74.96µ
( ∗ )( . )
= 74.96µ
( / ) = 5.49
x. Finally determine the value of gain and power dissipation and check its specification.
To determine :-
= ( + )( +| |)
= (30µ + 74.96µ)(0.9 + 0.9)
= 0.000188
= 0.188mW
To determine :-
=2 ( ) ( )
( . µ)( . µ)
= 2 ∗ ( . . ) . ∗ ( . . )
= 9725.27V/V
= 79.74
TABLE II
ASPECT RATIO OF EACH TRANSISTOR
Transistor W(µm) L(µm) Aspect ratio (W/L)
, 3 1 3
, 60 1 60
2.2 1 2.2
118.5 1 118.5
5.49 1 5.49
V. SIMULATION RESULTS
To check if all the design specifications are met, we simulate the circuit of OTA. Here, the simulation is done using simulator software called
LTspice. The schematic of OTA is designed in LTspice simulator with = 0.9V and = −0.9V. The bias current of the circuit is 30µA.
The input voltage of ±5V is given to the circuit. The value of compensation capacitor, =3 and load capacitor. = 10 . The
schematic of OTA which is drawn in Ltspice is represented in the figure below.
A. Transient Analysis
The input applied to differential amplifier is 1mV and we are getting an output of 150mV.
B. AC Analysis
In, AC analysis we can determine the frequency response of a circuit in which Gain, Phase Margin and Gain Bandwidth product can be
noted.
Inference:
Gain= 70dB,
Phase Margin= 68°
GB=5.6MHz
C. Slew rate
Schematic: Resultant plot:
Inference:
From the above plot, the output signal slews at the rate of 12.5 V/μ S.
D. ICMR
Schematic: Resultant plot:
Inference:
E. Power dissipation
To determine the power dissipated, sum the currents supplied by the constant current sources and multiply the result by the sum of V and V .
Here, the current through M6 is 0.00012A and the current through M5 is 30µA. So, the total power dissipation is 0.26mW.
TABLE III
THEORETICAL VALUES VS SIMULATED VALUES
VI. CONCLUSIONS
The objective of this work is to present the design and analyse of operational transconductance amplifier (OTA) in LTspice software under
180nm technology. In this analysis, Miller Compensation technique is implemented, where this simplest frequency compensation technique
employs the Miller effect by connecting a compensation capacitor across the high-gain stage. Here, all the simulated design specifications are
met with the given specifications. Proper gain and phase margin are obtained. In this paper, high gain and low power dissipation is achieved
and also the designed circuit is stable.
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