DRV

DRV102
DRV 102
102

SBVS009A – JANUARY 1998 – REVISED OCTOBER 2003

PWM SOLENOID/VALVE DRIVER

FEATURES APPLICATIONS
● HIGH OUTPUT DRIVE: 2.7A ● ELECTROMECHANICAL DRIVER:
● WIDE SUPPLY RANGE: +8V to +60V Solenoids Positioners
Actuators High Power Relays/Contactors
● COMPLETE FUNCTION
Valves Clutches/Brakes
PWM Output
Internal 24kHz Oscillator ● SOLENOID OVERHEAT PROTECTORS
Digital Control Input ● FLUID AND GAS FLOW CONTROLLERS
Adjustable Delay and Duty Cycle ● PART HANDLERS
Over/Under Current Indicator
● ELECTRICAL HEATERS/COOLERS
● FULLY PROTECTED
● MOTOR SPEED CONTROLLERS
Thermal Shutdown with Indicator
Internal Current Limit ● INDUSTRIAL CONTROL
● POWER PACKAGES: 7-Lead TO-220 and ● FACTORY AUTOMATION
7-Lead Surface-Mount DDPAK ● MEDICAL ANALYSIS
● PHOTOGRAPHIC PROCESSING

DESCRIPTION The DRV102 can be set to provide a strong initial closure,

automatically switching to a “soft” hold mode for power
The DRV102 is a high-side power switch employing a savings. Duty cycle can be controlled by a resistor, analog
pulse-width modulated (PWM) output. Its rugged design is voltage, or digital-to-analog converter for versatility. A flag
optimized for driving electromechanical devices such as output indicates thermal shutdown and over/under current
valves, solenoids, relays, actuators, and positioners. The limit. A wide supply range allows use with a variety of
DRV102 is also ideal for driving thermal devices such as actuators.
heaters and lamps. PWM operation conserves power and
The DRV102 is available in 7-lead staggered TO-220 pack-
reduces heat rise in the device, resulting in higher reliability.
age and a 7-lead surface-mount DDPAK plastic power
In addition, adjustable PWM allows fine control of the
package. It operates from –55°C to +125°C.
power delivered to the load. Time from dc output to PWM
output is externally adjustable. Flag

7
DRV102
Thermal Shutdown
Over/Under Current 5
(+8V to +60V)
24kHz VS
Oscillator

Input 1
PWM
On (TTL-Compatible)
6
Delay
Off Out

2 3 Gnd(1) 4 Load

Delay Duty Cycle

Adjust Adjust
(Gnd electrically
connected to tab)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1998-2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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SPECIFICATIONS
At TC = +25°C, VS = +24V, load = series diode MUR415 and 100Ω, and 4.99kΩ Flag pull-up to +5V, unless otherwise noted.

DRV102T, F

PARAMETER CONDITIONS MIN TYP MAX UNITS

OUTPUT
Output Saturation Voltage, Source IO = 1A +1.7 +2.2 V
IO = 0.1A +1.3 +1.7 V
Current Limit 2 2.7 3.4 A
Under-Scale Current 16 mA
Leakage Current Output Transistor Off, VS = +60V, VO = 0V ±0.01 ±2 mA
DIGITAL CONTROL INPUT(1)
VCTR Low (output disabled) 0 +1.2 V
VCTR High (output enabled) +2.2 VS V
ICTR Low (output disabled) VCTR = 0V –80(2) µA
ICTR High (output enabled) VCTR = +5V 20(2) µA
Propagation Delay: On-to-Off 0.9 µs
Off-to-On 1.8 µs
DELAY TO PWM(3) dc to PWM Mode
Delay Equation(4) Delay to PWM ≈ CD • 106 (CD in F) s
Delay Time CD = 0.1µF 80 97 110 ms
Minimum Delay Time(5) CD = 0 15 µs
DUTY CYCLE ADJUST
Duty Cycle Range 10 to 90 %
Duty Cycle Accuracy 49% Duty Cycle, RPWM = 25.5kΩ ±1 ±7 %
vs Supply Voltage 49% Duty Cycle, VS = 8V to 60V ±1 ±5 %
Nonlinearity(6) 20% to 80% Duty Cycle ±2 % FSR
DYNAMIC RESPONSE
Output Voltage Rise Time VO = 10% to 90% of VS 0.25 2.5 µs
Output Voltage Fall Time VO = 90% to 10% of VS 0.25 2.5 µs
Oscillator Frequency 19 24 29 kHz
FLAG
Normal Operation 20kΩ Pull-Up to +5V, IO < 1.5A +4 +4.9 V
Fault(7) Sinking 1mA +0.2 +0.4 V
Sink Current VFLAG = 0.4V 2 mA
Under-Current Flag: Set 5.2 µs
Reset 11 µs
Over-Current Flag: Set 5.2 µs
Reset 11.5 µs
THERMAL SHUTDOWN
Junction Temperature
Shutdown +165 °C
Reset from Shutdown +150 °C
POWER SUPPLY
Specified Operating Voltage +24 V
Operating Voltage Range +8 +60 V
Quiescent Current IO = 0 6.5 9 mA
TEMPERATURE RANGE
Specified Range –55 +125 °C
Storage Range –55 +125 °C
Thermal Resistance, θJC
7-Lead DDPAK, 7-Lead TO-220 3 °C/W
Thermal Resistance, θJA
7-Lead DDPAK, 7-Lead TO-220 No Heat Sink 65 °C/W

NOTES: (1) Logic high enables output (normal operation). (2) Negative conventional current flows out of the terminals. (3) Constant dc output to PWM (pulse-width
modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust pin low corresponds to an infinite (continuous) delay.
(5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 3 to percent of duty cycle at pin 6. (7) A fault results from over-temperature,
over-current, or under-current conditions.

2
DRV102
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CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS(1)
Top Front View TO-220, DDPAK Supply Voltage, VS .............................................................................. 60V
Input Voltage .......................................................................... –0.2V to VS
PWM Adjust Input ................................................ –0.2V to VS (24V max)
Delay Adjust Input ................................................ –0.2V to VS (24V max)
7-Lead Operating Temperature Range ...................................... –55°C to +125°C
Stagger-Formed Storage Temperature Range ......................................... –55°C to +125°C
TO-220 Junction Temperature .................................................................... +150°C
7-Lead
Lead Temperature (soldering, 10s)(2) ........................................... +300°C
DDPAK
Surface-Mount NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may de-
grade device reliability. (2) Vapor-phase or IR reflow techniques are recom-
mended for soldering the DRV102F surface-mount package. Wave soldering
is not recommended due to excessive thermal shock and “shadowing” of
nearby devices.

1 2 3 4 5 6 7 1 2 3 4 5 6 7 ELECTROSTATIC
DISCHARGE SENSITIVITY
In PWM
This integrated circuit can be damaged by ESD. Texas Instruments
VS Flag
recommends that all integrated circuits be handled with
Delay Gnd Out
In VS
appropriate precautions. Failure to observe proper handling and
PWM Flag
installation procedures can cause damage.
Delay Gnd Out
ESD damage can range from subtle performance degradation to
NOTE: Tabs are electrically connected to ground (pin 4). complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.

DRV102 3
SBVS009A www.ti.com
PIN DESCRIPTIONS
PIN # NAME DESCRIPTION

Pin 1 Input The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above
the typical switching threshold, 1.7V. Below this level, the output is disabled. With no connection to the pin, the input level rises
to 3.4V. Input current is 20µA when driven high and 80µA with the input low. The input may be driven to the power supply (VS)
without damage.

Pin 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results
in a delay of approximately 15µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less
than 3µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 3V threshold comparator.
When the pin voltage is below 3V, the output device is 100% on. The PWM oscillator is not synchronized to the Input (pin 1),
so the first pulse may be extended by any portion of the programmed duty cycle.

Pin 3 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a 19kΩ resistor to ground. It is driven by a 200µA current source
(PWM) from VS. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage,
or output of a D/A converter. The active voltage range is from 0.55V to 3.7V to facilitate the use of single-supply control
electronics. At 0.56V (or RPWM = 4.4kΩ), duty cycle is near 90%. Swing to ground should be limited to no lower than 0.1V. PWM
frequency is a constant 24kHz.

Pin 4 Ground This pin is electrically connected to the package tab. It must be connected to system ground for the DRV102 to function. It
carries the 6.5mA quiescent current.

Pin 5 VS This is the power supply pin. Operating range is +8V to +60V.

Pin 6 Out The output is the emitter of a power npn with the collector connected to VS. Low power dissipation in the DRV102 is obtained
by low saturation voltage and fast switching transitions. Rise time is less than 250ns, fall time depends on load impedance.
A flyback diode is (D1) needed with inductive loads to conduct the load current during the off cycle. The external diode should
be selected for low forward voltage. The internal clamp diode provides protection but should not be used to conduct load
currents. An additional diode (D2), located in series with Out pin, is required for inductive loads.

Pin 7 Flag Normally high (active low), the Flag signals either an over-temperature, over-current, or under-current fault. The over/under-
current flags are true only when the output is on (constant dc output or the “on” portion of PWM mode). A thermal fault (thermal
shutdown) occurs when the die surface reaches approximately 165°C and latches until the die cools to 150°C. Its output
requires a pull-up resistor. It can typically sink two milliamps, sufficient to drive a low-current LED.

LOGIC BLOCK DIAGRAM

Flag

DRV102
Over/Under Current

Thermal 5
(+8V to +60V)
Shutdown VS

1 PWM
Input
On (2)
6
Delay Out D2
Off
D1 (1) Load
2 3 Gnd 4

CD RPWM

NOTES: (1) Schottky Power Rectifier for low

power dissipation. (2) Schottky or appropriately
rated silicon diode.

4
DRV102
www.ti.com SBVS009A
TYPICAL PERFORMANCE CURVES
At TC = +25°C and VS = +24V, unless otherwise noted.

DUTY CYCLE and DUTY CYCLE ERROR vs VOLTAGE DUTY CYCLE vs TEMPERATURE
90 8 54
RPWM = 25.5kΩ
80 6
Duty Cycle 53
VS = +8V
70 4

Duty Cycle Error (%)

IO = 0.1A
52

Duty Cycle (%)

Duty Cycle (%)

60 Error 2
VS = +24V
50 0 51

40 –2
IO = 1A 50
30 –4
IO = 0.1A to 1A 49
20 –6 VS = +60V

10 –8 48
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –75 –50 –25 0 25 50 75 100 125
VPWM (V) Temperature (°C)

OUTPUT SATURATION VOLTAGE vs TEMPERATURE CURRENT LIMIT vs TEMPERATURE

2.25 3.25
VS = +8V, Load = 1Ω
2
IO = 2A 3
Saturation Voltage (V)

Current Limit (mA)

IO = 1.5A
1.75
VS = +60V, Load = 5Ω
IO = 1A
2.75
1.5
2.5
1.25 IO = 0.1A
VS = +24V, Load = 5Ω
2.25
1

0.75 2
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

QUIESCENT CURRENT vs TEMPERATURE UNDER-SCALE CURRENT vs TEMPERATURE

8 20
VS = +8V to +60V

7.5 18
Under-Scale Current (mA)
Quiescent Current (mA)

VS = +60V
7 16

VS = +24V
6.5 14

6 12
VS = +8V

5.5 10
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

DRV102 5
SBVS009A www.ti.com
TYPICAL PERFORMANCE CURVES (CONT)
At TC = +25°C and VS = +24V, unless otherwise noted.

FLAG OPERATION FLAG OPERATION

OVER-CURRENT LIMIT UNDER-CURRENT
(VS = +60V, CD = 220pF, RPWM = 25.5kΩ, Load = 350mH || 47Ω) (VS = +60V, CD = 120pF, RPWM = 25.5kΩ, No Load)
Onset of current limit where
VOUT begins to drop
60V 60V
VOUT

VIN
40V 40V

20V 20V
Flag only on during constant output
0 0 or “ON” portion of PWM mode
Flag only set during
constant output mode 4V
4V
or “ON” portion of

VFLAG
VFLAG

PWM mode
2V 2V

0 0
Constant Output PWM Mode

50µs/div 50µs/div

DC TO PWM MODE
DRIVING INDUCTIVE LOAD TYPICAL SOLENOID CURRENT WAVEFORM
(VS = +60V, CD = 120pF, RPWM = 30.1kΩ, Load = 350mH) (VS = +60V, CD = 0.1µF, RPWM = 30.1kΩ, Load = 350mH)

60V 4V
VOUT

VIN

40V 0
Solenoid
20V Motion
Period
{
0
Solenoid Current

1A 1A

0.5A PWM Mode

ISUPPLY

0.5A

0 0
Inductive load ramp current Solenoid Closure

25ms/div
50µs/div

CURRENT LIMIT REPSONSE

(Load = 1Ω, 2kΩ pull-up to +5V on Flag pin) OSCILLATOR FREQUENCY vs TEMPERATURE
24.2
VFLAG

5V
Oscillator Frequency (kHz)

2.5V 24.0
VS = +8V
0

3A 23.8

2A
IOUT

1A 23.6

0 VS = +60V

23.4
–75 –55 –35 –15 5 25 45 65 85 105 125
10µs/div
Temperature (°C)

6
DRV102
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TYPICAL PERFORMANCE CURVES (CONT)
At TC = +25°C and VS = +24V, unless otherwise noted.

OUTPUT LEAKAGE CURRENT vs TEMPERATURE NOMINAL DELAY TIME TO PWM vs TEMPERATURE

–200 103
Output Transistor Off CD = 0.1µF
VS = +8V
VO = 0V
101
–175
Leakage Current (µA)

99
–150
VS = +24V

Delay (ms)
VS = +60V 97
–125
95
VS = +24V
VS = +60V
–100
93
VS = +8V
–75 91
–75 –55 –35 –15 5 25 45 65 85 105 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

CURRENT LIMIT DELAY TIME TO PWM

PRODUCTION DISTRIBUTION PRODUCTION DISTRIBUTION
40 60
Typical distribution CD = 0.1µF Typical distribution
35 of packaged units. of packaged units.
50
DRV102F and DRV102F and
30 DRV102T included. Percent of Units (%) DRV102T included.
Percent of Units (%)

40
25

20 30

15
20
10
10
5

0 0

2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110
Current Limit (A) Delay Time to PWM (ms)

DUTY CYCLE ACCURACY

PRODUCTION DISTRIBUTION
30
Nominal Duty Cycle = 49% Typical distribution
RPWM = 25.5kΩ of packaged units.
25
DRV102F and
DRV102T included.
Percent of Units (%)

20

15

10

–7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7
Duty Cycle Accuracy (%)

DRV102 7
SBVS009A www.ti.com
BASIC OPERATION pin connected to 0.1µF and duty cycle set for 25%. See the
“Delay Adjust” and “Duty Cycle Adjust” text for equations
The DRV102 is a high-side, bipolar power switch employ- and further explanation.
ing a pulse-width modulated (PWM) output for driving
Ground (pin 4) is electrically connected to the package tab.
electromechanical and thermal devices. Its design is opti-
This pin must be connected to system ground for the
mized for two types of applications: a two-state driver
DRV102 to function. This serves as the DRV102 reference
(open/close) for loads such as solenoids and actuators, and
ground.
a linear driver for valves, positioners, heaters, and lamps. Its
wide supply range, adjustable delay to PWM mode, and The load (solenoid, valve, etc.) is connected between the
adjustable duty cycle make it suitable for a wide range of output (pin 6) and ground. For an inductive load, an external
applications. Figure 1 shows the basic circuit connections to flyback diode (D1 in Figure 1a) across the output is required.
operate the DRV102. A 0.1µF bypass capacitor is shown The diode serves to maintain the hold force during PWM
connected to the power supply pin. operation. Depending on the application, the flyback diode
should be placed near the DRV102 or close to the solenoid
The Input (pin 1) is compatible with standard TTL levels.
(see “Flyback Diode” text). The device’s internal clamp
Input voltages between +2.2V and +5.5V turn the device
diode, connected between the output and ground, should not
output on, while pulling the pin low (0V to +1.2V), shuts the
be used to carry load current. When driving inductive loads,
DRV102 output off. Input current is typically 80µA.
an additional diode in series with the out pin, D2, is required
Delay Adjust (pin 2) and Duty Cycle Adjust (pin 3) allow (see “Series Diode” text).
external adjustment of the PWM output signal. The Delay
The Flag (pin 7) provides fault status for under-current,
Adjust pin can be left floating for minimum delay to PWM
over-current, and thermal shutdown conditions. This pin is
mode (typically 15µs) or a capacitor can be used to set the
active low with pin voltage typically +0.2V during a fault
delay time. Duty cycle of the PWM output can be controlled
condition. A small value capacitor may be needed between
by a resistor, analog voltage, or D/A converter. Figure 1b
Flag and ground for noisy applications.
provides an example timing diagram with the Delay Adjust

1a). Basic Circuit Connections

Flag

7 VS
(+8V to +60V)
DRV102
Thermal Shutdown 0.1µF
Over/Under Current

24kHz 5
Oscillator VS
1
PWM
Input D2
6
(TTL-Compatible) Delay
On Out
(1) Load
Off D1
2 3 Gnd 4 (Gnd electrically
Duty connected to tab)
CD Delay RPWM Cycle
Adjust
Adjust

NOTE: (1) External flyback diode required for inductive loads to conduct load current during the off cycle.
Flyback diode shown near DRV102. For some applications with remotely located load, it may be desirable
to place the diode near the solenoid—see “Flyback Diode” text. Motorola MSRS1100T3 (1A, 100V) or
MBRS360T3 (3A, 60V).

1b). Simplified Timing Diagram

CD = 0.1µF (92ms constant dc output before PWM)
RPWM = 90.9kΩ

+2.2V to +5.5V •••

INPUT
0V to +1.2V

VS
OUTPUT CD = 0.1µF
0 92ms •••
tON RPWM = 90.9kΩ
tON ≈ 10.4µs
tP tP ≈ 41.6µs (1/24kHz)
t
Duty Cycle = ON = 25%
tP
Initial dc Output PWM Mode
(set by value (resistor or voltage
of CD) controlled)

FIGURE 1. Basic Circuit Connections and Timing Diagram.

8
DRV102
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APPLICATIONS INFORMATION vidual situations may defy logic; if one location seems to
create noise problems, try the other.
POWER SUPPLY
The DRV102 operates from a single +8V to +60V supply SERIES DIODE FOR INDUCTIVE LOADS
with excellent performance. Most behavior remains un-
changed throughout the full operating voltage range. Param- An additional bias diode, located in series with the output, is
eters which vary significantly with operating voltage are required when driving inductive loads. Any silicon diode,
shown in the Typical Performance Curves. such as the 1N4002, appropriately rated for current will
work. The diode biases the emitter of the internal power
device such that it can be fully shut off during the “off”
CONNECTIONS TO LOAD portion of the PWM cycle. Note that the voltage at the load
The PWM switching voltage and currents can cause electro- drops below ground due to the flyback diode. If it is not used,
magnetic radiation. Proper physical layout of the load cur- apparent leakage current can rise to hundreds of milliamps,
rent will help minimize radiation. Load current flows from resulting in unpredictable operation and thermal shutdown.
the DRV102 output terminal to the load and returns through
the ground return path. This current path forms a loop. To ADJUSTABLE INITIAL 100% DUTY CYCLE
minimize radiation, make the area of the enclosed loop as
A unique feature of the DRV102 is its ability to provide an
small as possible. Twisted pair leading to the load is excel-
initial constant dc output (100% duty cycle) and then switch
lent. If the ground return current must flow through a chassis
to PWM mode to save power. This function is particularly
ground, route the output current line directly over the chassis
useful when driving solenoids which have a much higher
surface in the most direct path to the load.
pull-in current requirement than hold current requirement.

FLYBACK DIODE LOCATION The duration of this constant dc output (before PWM output
begins) can be externally and independently controlled with
Physical location of the flyback diode may affect electro- a capacitor connected from Delay Adjust (pin 2) to ground
magnetic radiation. With most solenoid loads, inductance is according to the following equation:
large enough that load current is virtually constant during
Delay Time ≈ CD • 106
PWM operation. When the switching transistor is off, load
(time in seconds, CD in Farads)
current flows though the flyback diode. If the flyback diode
is located near the DRV102 (Figure 2a), the current flowing Leaving the Delay Adjust pin open results in a constant
in long lines to the load is virtually constant. If the flyback output time of approximately 15µs. The duration of this
diode is, instead, located directly across the load (Figure 2b), initial output can be reduced to less than 3µs by connecting
pulses of current must flow from the DRV102 to the distant the pin to 5V. Table I provides examples of desired “delay”
load. While theory seems to favor placing the diode at the times (constant output before PWM mode) and the appropri-
DRV102 output (constant current in the long lines), indi- ate capacitor values or pin connection.
CONSTANT OUTPUT DURATION
2a) Flyback Diode Near DRV102 (Delay Time to PWM Mode) CD

3µs Pin Connected to 5V

DRV102
5 15µs Pin Open
VS 97µs 100pF
0.97ms 1nF
97ms 0.1µF
6
Out TABLE I. Delay Adjust Pin Connections.
Load
4 The internal Delay Adjust circuitry is composed of a 3µA
current source and a 3V comparator as shown in Figure 3.
Thus, when the pin voltage is less than 3V, the output device
is 100% on (dc output mode).
2b) Flyback Diode Near Load
DRV102
DRV102
5 3V Reference
VS VS

3µA
6
Out
Comparator
Load
4
2
Delay Adjust CD

FIGURE 2. Location of External Flyback Diode. FIGURE 3. Simplified Circuit Model of the Delay Adjust Pin.

DRV102 9
SBVS009A www.ti.com
ADJUSTABLE DUTY CYCLE Voltage-Controlled Duty Cycle
The DRV102’s externally adjustable duty cycle provides an Duty cycle can also be programmed with an analog voltage,
accurate means of controlling power delivered to the load. VPWM. With VPWM ≈ 0.5V, duty cycle is 100%. Increasing
Duty cycle can be set from 10% to 90% with an external this voltage results in decreased duty cycles. For 0% duty
resistor, analog voltage, or the output of a D/A converter. cycle, VPWM is approximately 4V. Table II provides VPWM
Reduced duty cycle results in reduced power dissipation. values for typical duty cycles. See the “Duty Cycle vs
This keeps the DRV102 and load cooler, resulting in in- Voltage” typical performance curve for additional duty cycle
creased reliability for both devices. PWM frequency is a values.
constant 24kHz.
The Duty Cycle Adjust pin should not be driven below 0.1V.
Resistor-Controlled Duty Cycle If the voltage source used can go between 0.1V and ground,
Duty cycle is independently programmed with a resistor a 1kΩ series resistor between the voltage source and the Duty
(RPWM) connected between the Duty Cycle Adjust pin and Cycle Adjust pin (Figure 5) is required to limit swing. If the
ground. Increased resistor values correspond to decreased pin is driven below 0.1V, the output will be unpredictable.
duty cycles. Table II provides resistor values for typical duty
cycles. Resistor values for additional duty cycles can be
obtained from Figure 4. For reference purposes, the equation
for calculating RPWM is included in Figure 4.
DRV102
5
VS
RESISTOR(1) VOLTAGE(2)
DUTY CYCLE RPWM (kΩ) VPWM (V)

10 536 3.67 PWM 6

20 137 3.31 Out
30 66.5 2.91
40 39.2 2.49 VPWM 3 Gnd 4
50 24.9 2.07 D/A
60 16.2 1.66 Converter
70 10.5 1.26
(or analog
80 6.65 0.88 1kΩ(1) voltage)
90 4.42 0.56

NOTES: (1) Resistor values listed are nearest 1% standard values. (2) Do not NOTE: (1) Required if voltage source can go below 0.1V.
drive pin below 0.1V. For additional values, see “Duty Cycle vs Voltage” typical
performance curve.

TABLE II. Duty Cycle Adjust. TA= +25°C, VS = +24V. FIGURE 5. Using a Voltage Source to Program Duty Cycle.

The DRV102’s internal 24kHz oscillator sets the PWM

1000 period. This frequency is not externally adjustable. Duty
Cycle Adjust (pin 3) is internally driven by a 200µA current
source and connects to the input of a comparator and a 19kΩ
resistor as shown in Figure 6. The DRV102’s PWM control
100
design is inherently monotonic. That is, a decreased voltage
RPWM (kΩ)

(or resistor value) always produces an increased duty cycle.

10

3.8V
f = 24kHz
1 0.7V
10 20 40 60 80 100
VS
Duty Cycle (%)
Comparator
200µA

RPWM = [ a + b (DC) + c (DC)2 + d (DC)3 + e (DC)4]–1

where: a = –4.9686 x 10–8 d = –5.4837 x 10–10 19kΩ

b = –5.9717 x 10–8 e = 5.9361 x 10–12
c = 2.9889 x 10–8 DRV102
3
DC = duty cycle in %
Resistor or
For 50% duty cycle: Duty Cycle Voltage Source(1)
RPWM = [–4.9686 x 10–8 + (–5.9717 x 10–8) (50) + (2.9889 x 10–8) (50)2 Adjust
+ (–5.4837 x 10–10) (50)3 + (5.9361 x 10–12) (50)4]–1
= 24.9kΩ NOTE: (1) Do not drive pin below 0.1V.

FIGURE 4. RPWM versus Duty Cycle. FIGURE 6. Simplified Circuit Model of the Duty Cycle
Adjust Pin.

10
DRV102
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STATUS FLAG
Flag (pin 7) provides fault indication for under-current,
over-current, and thermal shutdown conditions. During a +5V
fault condition, Flag output is driven low (pin voltage
typically drops to 0.2V). A pull-up resistor, as shown in
Figure 7, is required to interface with standard logic. A small 5kΩ
value capacitor may be needed between Flag and ground in
noisy applications. (LED)
HLMP-Q156
Figure 7 gives an example of a non-latching fault monitoring
circuit, while Figure 8 provides a latching version. The Flag Flag 7
pin can sink several milliamps, sufficient to drive external
logic circuitry or an LED (Figure 9) to indicate when a fault Thermal Shutdown
5
has occurred. In addition, the Flag pin can be used to turn off Over/Under Current VS

other DRV102’s in a system for chain fault protection.

6
DRV102 Out
Gnd 4
+5V

5kΩ
TTL or HCT
Pull-Up

FIGURE 9. LED to Indicate Fault Condition.

Flag 7

Thermal Shutdown
Over/Under Current Fault
Over/Under Current 5 An over-current fault occurs when the output current ex-
VS
ceeds the current limit. All units are guaranteed to drive 2A
without current limiting. Typically, units will limit at 2.7A.
6 The status flag is not latched. Since current during PWM
DRV102 Out
mode is switched on and off, the flag output will be modu-
Gnd 4
lated with PWM timing (see flag waveforms in the Typical
Performance Curves).
FIGURE 7. Non-Latching Fault Monitoring Circuit. An under-current fault occurs when the output current is
below the under-scale current threshold (typically 16mA).
For example, this function indicates when the load is discon-
+5V nected. Again, the flag output is not latched, so an under-
current condition during PWM mode will produce a flag
74XX76A output that is modulated by the PWM waveform. An initial,
VS brief under-current flag normally appears driving inductive
Flag Q J 20kΩ loads and may be avoided by adding a parallel resistor
Flag Q sufficient to move the initial current above the under-current
Flag Reset CLR CLK threshold. Avoid adding capacitance to pin 6 (Out) as it may
(1)
GND K cause momentary current limiting.
Over-Temperature Fault
A thermal fault occurs when the die reaches approximately
Flag
165°C, producing a similar effect as pulling the input low.
7
Internal shutdown circuitry disables the output and resets the
Thermal Shutdown
Delay Adjust pin. The Flag is latched in the low state (fault
5 condition) until the die has cooled to approximately 150°C.
Over/Under Current VS
A thermal fault can occur in any mode of operation. Recov-
ery from thermal fault will start in delay mode (constant dc
DRV102
6 output).
Out
Gnd 4

NOTE: (1) Small capacitor (10pF) may be required in noisy environments.

FIGURE 8. Latching Fault Monitoring Circuit.

DRV102 11
SBVS009A www.ti.com
PACKAGE MOUNTING For best thermal performance, the tab of the DDPAK sur-
Figure 10 provides recommended PCB layouts for both the face-mount version should be soldered directly to a circuit
TO-220 and DDPAK power packages. The tab of both board copper area. Increasing the copper area improves heat
packages is electrically connected to ground (pin 4). It may dissipation. Figure 12 shows typical thermal resistance from
be desirable to isolate the tab of TO-220 package from its junction-to-ambient as a function of the copper area.
mounting surface with a mica (or other film) insulator (see
Figure 11). For lowest overall thermal resistance, it is best to POWER DISSIPATION
isolate the entire heat sink/DRV102 structure from the
mounting surface rather than to use an insulator between the Power dissipation depends on power supply, signal, and load
semiconductor and heat sink. conditions. Power dissipation is equal to the product of

7-Lead TO-220 7-Lead DDPAK(1)

(Package Drawing #327) (Package Drawing #328)
0.51

0.45
0.335

0.15

0.085
0.04
0.05

0.2
0.035
0.05
0.105

Mean dimensions in inches. Refer to end of data sheet

or Appendix C of Burr-Brown Data Book for tolerances NOTE: (1) For improved thermal performance increase footprint area.
and detailed package drawings. For further information See Figure 12, “Thermal Resistance versus Circuit Board Copper Area”.
on solder pads for surface-mount devices consult
Application Bulletin AB-132.

FIGURE 10. TO-220 and DDPAK Solder Footprints.

THERMAL RESISTANCE
vs ALUMINUM PLATE AREA
18 Aluminum Plate Area
Vertically Mounted
Flat, Rectangular
Thermal Resistance θJA (°C/W)

in Free Air
16 Aluminum Plate

14
0.030

12

0.050
10
Aluminum Plate
Thickness (inches) 0.062
8 Optional mica or film insulator
0 1 2 3 4 5 6 7 8 for electrical isolation. Adds DRV102
Aluminum Plate Area (inches2) approximately 1°C/W. TO-220 Package

FIGURE 11. TO-220 Thermal Resistance versus Aluminum Plate Area.

12
DRV102
www.ti.com SBVS009A
 THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA
50
DRV102 Circuit Board Copper Area

Thermal Resistance, θJA (°C/W)

DDPAK
40
Surface-Mount Package
1oz. copper
30

20

10

0 DRV102
0 1 2 3 4 5 DDPAK
Copper Area (inches2) Surface-Mount Package

FIGURE 12. DDPAK Thermal Resistance versus Circuit Board Copper Area.

output current times the voltage across the conducting out- low as possible for increased reliability. Junction tempera-
put transistor times the duty cycle. Power dissipation can be ture can be determined according to the equation:
minimized by using the lowest possible duty cycle necessary TJ = TA + PDθJA (1)
to assure the required hold force.
where, θJA = θJC + θCH + θHA (2)
THERMAL PROTECTION
Power dissipated in the DRV102 will cause the junction TJ = Junction Temperature (°C)
temperature to rise. The DRV102 has thermal shutdown TA = Ambient Temperature (°C)
circuitry that protects the device from damage. The thermal PD = Power Dissipated (W)
protection circuitry disables the output when the junction θJC = Junction-to-Case Thermal Resistance (°C/W)
temperature reaches approximately +165°C, allowing the de- θCH = Case-to-Heat Sink Thermal Resistance (°C/W)
vice to cool. When the junction temperature cools to approxi-
θHA = Heat Sink-to-Ambient Thermal Resistance (°C/W)
mately +150°C, the output circuitry is again enabled. Depend-
ing on load and signal conditions, the thermal protection θJA = Junction-to-Air Thermal Resistance (°C/W)
circuit may cycle on and off. This limits the dissipation of the Figure 13 shows maximum power dissipation versus ambi-
driver but may have an undesirable effect on the load. ent temperature with and without the use of a heat sink.
Any tendency to activate the thermal protection circuit Using a heat sink significantly increases the maximum
indicates excessive power dissipation or an inadequate heat power dissipation at a given ambient temperature as shown.
sink. For reliable operation, junction temperature should be
limited to +125°C, maximum. To estimate the margin of
MAXIMUM POWER DISSIPATION
safety in a complete design (including heat sink), increase vs AMBIENT TEMPERATURE
the ambient temperature until the thermal protection is 10
triggered. Use worst-case load and signal conditions. For PD = (TJ (max) – TA) / θ JA
TO-220 with Thermalloy
TJ (max) = 125°C
good reliability, thermal protection should trigger more than 8
6030B Heat Sink
Power Dissipation (Watts)

θJA = 16.5°C/W
40°C above the maximum expected ambient condition of With infinite heat sink
your application. This produces a junction temperature of ( θJA = 3°C/W),
6
max PD = 33W
125°C at the maximum expected ambient condition.
at TA = 25°C
The internal protection circuitry of the DRV102 was designed 4
DDPAK
to protect against overload conditions. It was not intended to θJA = 26°C/W (3 in2 1 oz.
replace proper heat sinking. Continuously running the 2 copper mounting pad)

DRV102 into thermal shutdown will degrade reliability. DDPAK or TO-220

θJA = 65°C/W (no heat sink)
0
0 25 50 75 100 125
HEAT SINKING
Ambient Temperature (°C)
Most applications will not require a heat sink to assure that
the maximum operating junction temperature (125°C) is not
FIGURE 13. Maximum Power Dissipation versus Ambient
exceeded. However, junction temperature should be kept as
Temperature.

DRV102 13
SBVS009A www.ti.com
The difficulty in selecting the heat sink required lies in To maintain junction temperature below 125°C, the heat
determining the power dissipated by the DRV102. For dc sink selected must have a θHA less than 18.5°C/W. In other
output into a purely resistive load, power dissipation is simply words, the heat sink temperature rise above ambient must be
the load current times the voltage developed across the less than 37°C (18.5°C/W • 2W). For example, at 2 Watts
conducting output transistor times the duty cycle. Other loads Thermalloy model number 6030B has a heat sink
are not as simple. Once power dissipation for an application temperature rise of about 33°C above ambient, which is
is known, the proper heat sink can be selected. below the 37°C required in this example. Figure 13 shows
Heat Sink Selection Example power dissipation versus ambient temperature for a TO-220
package with a 6030B heat sink.
A TO-220 package’s maximum dissipation is 2 Watts. The
maximum expected ambient temperature is 80°C. Find the Another variable to consider is natural convection versus
proper heat sink to keep the junction temperature below forced convection air flow. Forced-air cooling by a small fan
125°C. can lower θCA (θCH + θHA) dramatically. Heat sink manufac-
turers provide thermal data for both of these cases. For
Combining Equations 1 and 2 gives: additional information on determining heat sink require-
TJ = TA + PD(θJC + θCH + θHA) (3) ments, consult Application Bulletin AB-038.
As mentioned earlier, once a heat sink has been selected, the
TJ, TA, and PD are given. θJC is provided in the Specifica- complete design should be tested under worst-case load and
tions table, 3°C/W. θCH can be obtained from the heat sink signal conditions to ensure proper thermal protection.
manufacturer. Its value depends on heat sink size, area, and
material used. Semiconductor package type, mounting screw
torque, insulating material used (if any), and thermal
joint compound used (if any) also affect θCH. A typical θCH
for a TO-220 mounted package is 1°C/W. Now we can solve
for θHA:

(4)
– (θ JC + θ CH )
TJ – TA
θ HA =
PD
125°C – 80°C
θ HA = – (3°C/ W + 1°C/ W ) = 18.5°C/ W
2W

14
DRV102
www.ti.com SBVS009A
APPLICATION CIRCUITS

+5V

5kΩ
Flag

Can drive most types

7 of solenoid-actuated
valves and actuators
5
Thermal Shutdown
VS
Over/Under Current VS
Pinch Valve
24kHz
Oscillator
Flexible Tube
Microprocessor TTL Control Input 1
PWM
6
On Plunger
Delay Out
Off DRV102
2 3 4 Gnd
Solenoid Coil
Delay Duty Cycle
CD RPWM Adjust(1)
Adjust
(10% to 90%)
NOTE: (1) Duty cycle can be programmed by
a resistor, analog voltage, or D/A converter.
Do not drive below 0.1V.

FIGURE 14. Fluid Flow Control System.

Brighter light results in

increased duty cycle
DRV102
DRV102 5
VS
5 Input 1
VS
(On/Off)
1
On/Off 6
Out
6 (1)
2 Coil
Out 3 4

Lamp Delay
2 3 4
Adjust
Delay
100Ω
Adjust
Duty Cycle Adjust
Aimed at Cadmium Sulfide
4-20mA
λ Optical Detector 187Ω
ambient
light (Clairex CL70SHL
or CLSP5M) Twisted Pair

10kΩ NOTE: (1) Rectifier diode required for inductive

loads to conduct load current during the off cycle.

FIGURE 15. Instrument Light Dimmer Circuit. FIGURE 16. 4-20mA Input to PWM Output.

DRV102 15
SBVS009A www.ti.com
 Reduced mechanical actuation delay with high voltage pull-in followed by low duty cycle

DRV102
5
+40V (max for TPIC6273)
1 VS
On/Off

6
Out
2 3 4

RPWM
150kΩ

(25% Duty Cycle)

CD
0.047µF

Full power pulse width is control

plus interval set by CD.

74LS05

+5V
4 5 6 7 14 15 16 17
20
TI TPIC6273
(Octal Power Switch)
11
••• •••
10 Control

2 3 8 9 12 13 18 19

TTL/CMOS Solenoid Selection Inputs

FIGURE 17. Improved Switching Time When Driving Multiple Loads.

16
DRV102
www.ti.com SBVS009A
 a)

VS

DRV102 5

1
On/Off
Higher temperature results
2 6
in lower duty cycle.
Delay Out
Adjust
3 4 Gnd Heating
Thermistor
Element
Duty
Cycle
Adjust R1

R2

b)
VS
10µF

1 DRV102 5
On/Off
0.1µF

2 REF200
Delay
6 7, 8
Adjust
Out
3 4 Gnd Heating 100µA 100µA
Element

1 2
2µF Film

0.1µF VS

7 10MΩ
2
1kΩ
Duty Cycle 6
OPA134
Adjust 3

4 Temperature
10kΩ Control
4.7V

or Higher temperature results

Thermistor IN4148(1) in lower duty cycle.
5kΩ at +25°C

Integrator improves accuracy

NOTE: (1) Or any common silicon diode suited

20kΩ
to the mechanical mounting requirements.

FIGURE 18. (a) Constant Temperature Controller. (b) Improved Accuracy Constant Temperature Controller.

DRV102 17
SBVS009A www.ti.com
 DRV102
5
+12V
Input 1
(On/Off)
dc Tachometer
6
Coupled to Motor
Out

2 3 4
M T
Delay
Adjust

R1 R2
Speed Control(1)

NOTE: (1) Select R1/R2 ratio based on tachometer output voltage.

FIGURE 19. Constant Speed Motor Control.

5
+40V
Open circuit will
provide 3.4V DRV102
“on” signal 1
6

2 3 4
40kΩ M
Speed Control Input
Delay Adjust
0V to +10V
+15V

0.5µF
1kΩ
+15V
22kΩ 470kΩ

1nF 100kΩ Frequency In

One-Shot VOUT
47kΩ
2N2222 10kΩ

AC
Tachometer
T
VFC32
Coupled to Motor
5nF
–15V NP0

FIGURE 20. DC Motor Speed Control Using AC Tachometer.

18
DRV102
www.ti.com SBVS009A
 +24V VZ
DRV102 2kΩ
5
VS
5.1V
25kΩ
Zener
1 100kΩ 0.1µF
On
6 1kΩ
Off Out Current Set VZ

2 3 4 Load
Duty Cycle
Delay 100kΩ OPA237
Adjust
Adjust

RSHUNT 0.1µF
0.1Ω

5kΩ

0.6V gives ~ 90% Duty Cycle

3.7V gives ~ 10% Duty Cycle

FIGURE 21. Constant Current Output Drive.

Only one DRV102 is

turned on at sequence time.
5 5
VS VS
Phase 2 Phase 3
Stepper DRV102 DRV102 Stepper
Logic In Logic In
6 6

Motor

5
VS
Phase 1
Stepper DRV102
Logic In
6

FIGURE 22. Three-Phase Stepper Motor Driver Provides High-Stepping Torque.

VS = +8V to +60V DRV102

5
VS
R1
1

R2 6
Out
2 3 4
Select R1 and R2 to divide
down VS to 5.5V max. Delay Adjust
For example: with VS = 60V R3 C1
R1 = 11kΩ, R2 = 1kΩ 4.87kΩ 20µF
Duty Cycle Adjust
1kΩ + after soft start
VIN = • 60V = 5V
1kΩ + 11kΩ 4.3V R4
DIN5229 4.87kΩ
Sets start-up
duty cycle

FIGURE 23. Soft-Start Circuit for Incandescent Lamps and Other Sensitive Loads.

DRV102 19
SBVS009A www.ti.com
 PACKAGE OPTION ADDENDUM
www.ti.com 27-Sep-2005

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
DRV102F OBSOLETE DDPAK KTW 7 TBD Call TI Call TI
DRV102F/500 ACTIVE DDPAK KTW 7 500 Green (RoHS & CU SNPB Level-2-260C-1 YEAR
no Sb/Br)
DRV102FKTWT ACTIVE DDPAK KTW 7 50 Green (RoHS & CU SNPB Level-2-260C-1 YEAR
no Sb/Br)
DRV102T ACTIVE TO-220 KV 7 49 TBD CU SNPB Level-NA-NA-NA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
 MECHANICAL DATA

MPSF015 – AUGUST 2001

KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT

0.410 (10,41) 0.304 (7,72)

–A–
0.385 (9,78) 0.006 0.296 (7,52)
–B–
0.303 (7,70) 0.300 (7,62)
0.0625 (1,587) H 0.297 (7,54) 0.055 (1,40) 0.252 (6,40)
0.064 (1,63)
0.0585 (1,485) 0.045 (1,14)
0.056 (1,42)

0.370 (9,40) 0.187 (4,75)

0.330 (8,38) 0.179 (4,55)
H A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C 0.000 (0,00)
0.104 (2,64)
0.019 (0,48) 0.096 (2,44) H
0.017 (0,43)

0.050 (1,27) 0.026 (0,66)

C
0.034 (0,86) 0.014 (0,36)
0°~3°
C F 0.022 (0,57)
0.010 (0,25) M B AM C M

0.183 (4,65)
0.170 (4,32)

4201284/A 08/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.

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