UNIT-2

Boolean Algebra

Boolean algebra is a type of algebra that is created by operating the binary system. In the year
1854, George Boole, an English mathematician, proposed this algebra. This is a variant of
Aristotle’s propositional logic that uses the symbols 0 and 1, or True and False. Boolean algebra
is concerned with binary variables and logic operations.
Boolean Algebra is fundamental in the development of digital electronics systems as they all use
the concept of Boolean Algebra to execute commands. Apart from digital electronics this
algebra also finds its application in Set Theory, Statistics, and other branches of mathematics.

Boolean Algebra Operations

Various operations are used in Boolean algebra but the basic operations that form the base of
Boolean Algebra are.
 Negation or NOT Operation
 Conjunction or AND Operation
 Disjunction or OR Operation

These operations have their own symbols and precedence and the table added below shows the
symbol and the precedence of these operators.
Operator Symbol Precedence

⇁
‘ (or)
NOT First

AND . (or) ∧ Second

∨
+ (or)
OR Third

We can easily define these operations using two boolean variables.

Let’s take two boolean variables A and B that can have any of the two values 0 or 1, i.e. they
can be either OFF or ON. Then these operations are explained as,

Negation or NOT Operation

Using the NOT operation reverse the value of the Boolean variable from 0 to 1 or vice-versa.
This can be understood as:
 If A = 1, then using NOT operation we have (A)’ = 0
 If A = 0, then using the NOT operation we have (A)’ = 1
 We also represent the negation operation as ~A, i.e if A = 1, ~A = 0

A A’
TRUE FALSE
FALSE TRUE

Conjunction or AND Operation

Using the AND operation satisfies the condition if both the value of the individual variables
are true and if any of the value is false then this operation gives the negative result. This can be
understood as,
 If A = True, B = True, then A . B = True
 If A = True, B = False, Or A = false, B = True, then A . B = False
 If A = False, B = False, then A . B = False

A B A.B
TRUE TRUE TRUE
TRUE FALSE FALSE
FALSE TRUE FALSE
FALSE FALSE FALSE

Disjunction (OR) Operation

Using the OR operation satisfies the condition if any value of the individual variables is true, it
only gives a negative result if both the values are false. This can be understood as,
 If A = True, B = True, then A + B = True
 If A = True, B = False, Or A = false, B = True, then A + B = True
 If A = False, B = False, then A + B = Falses

A B A+B
TRUE TRUE TRUE
TRUE FALSE TRUE
FALSE TRUE TRUE
FALSE FALSE FALSE

EX-OR Operation:
XOR is a bitwise operator, and it stands for "exclusive or." It performs logical operation. If input
bits are the same, then the output will be false(0) else true(1).
XOR table:

X Y X^Y
0 0 0
0 1 1
1 0 1
1 1 0

Example: 4^3 = 7
In binary:
0100
^ 0011
------
Result: 0111 => (7)
XOR with negative numbers

Let's understand with an example -4^-2 = 2 In the above example, we can see -4^-2output will
be 2 but the question arises how? Because if we represent both inputs in the binary form, then we
do XOR of bits, then the output will be 0000 0110 and in decimal, it will be 6 but as we know
output should be 2.
1000 0100 (-4)
^ 1000 0010 (-2)
------------------
0000 0110 => (6) // incorrect output
Note: Here, the leftmost bit position is reserved for the sign of the value (positive or negative)
and doesn't contribute towards the value of the number.

Let's understand how the XOR operation works with negative numbers.

How XOR operation works with negative numbers?

First, the XOR operation is to XOR each bit (the same is 0, the difference is 1), but you need to
convert the number into a complement first.

1. The complement of a positive number is itself

2. The complement of the negative number is reversed for each bit and then incremented by
1 (the highest is kept at 1)
3. // Lets take -4
4. In binary: 1000 0100
5. Reverse: 1111 1011
complement (Increment by 1): 1111 1100
// Now -2 In binary: 1000 0010 Reverse: 1111 1101 complement (Increment by 1): 1111 1110

Final result:
complement of -4 : 1111 1100
complement of -2 : 1111 1110
-----------
Result: 0000 0010 => 2

EX-NOR operation:

The XNOR, or Exclusive NOR, is a logical operation that is the complement of the Exclusive
OR (XOR) operation.

he XNOR operation takes two input values, which can be either 0 (false) or 1 (true), and
compares them. The result of the XNOR operation is true if both inputs are the same, and false if
the inputs are different. In other words, the XNOR outputs a true value when both inputs match
(both true or both false) and outputs a false value when the inputs do not match (one is true and
the other is false).

The truth table for the XNOR operation is as follows:

Input A Input B Output (A XNOR B)

0 0 1

0 1 0

1 0 0

1 1 1

As seen in the truth table, the XNOR operation only yields a true output when both inputs are
equal.

All Test Series
 Prev. Year Paper

 Practice




Demorgan’s Theorems:

\
Generating Boolean Expressions from truth table:

Using Sum of product(SOP)

A canonical sum of products is a boolean expression that entirely consists of minterms. The
Boolean function F is defined on two variables X and Y. The X and Y are the inputs of the
boolean function F whose output is true when any one of the inputs is set to true. The truth table
for Boolean expression F is as follows:

Inputs Output

X Y F
 0 0 0

0 1 1

1 0 1

1 1 1

In our previous section, we learned about how we can form the minterm from the variable's
value. Now, a column will be added for the minterm in the above table. The complement of the
variables is taken whose value is 0, and the variables whose value is 1 will remain the same.

Inputs Output Minterm

X Y F M

0 0 0 X'Y'

0 1 1 X'Y

1 0 1 XY'

1 1 1 XY

Now, we will add all the minterms for which the output is true to find the desired canonical
SOP(Sum of Product) expression.

F=X' Y+XY'+XY

Converting Sum of Products (SOP) to shorthand notation

The process of converting SOP form to shorthand notation is the same as the process of finding
shorthand notation for minterms. There are the following steps to find the shorthand notation of
the given SOP expression.

o Write the given SOP expression.

o Find the shorthand notation of all the minterms.
o Replace the minterms with their shorthand notations in the given expression.

Example: F = X'Y+XY'+XY
1. Firstly, we write the SOP expression:

F = X'Y+XY'+XY

2. Now, we find the shorthand notations of the minterms X'Y, XY', and XY.

X'Y = (01)2 = m1
XY' = (10)2 = m2
XY = (11)2 = m3

3. In the end, we replace all the minterms with their shorthand notations:

F=m1+m2+m3

Converting shorthand notation to SOP expression

The process of converting shorthand notation to SOP is the reverse process of converting SOP
expression to shorthand notation. Let's see an example to understand this conversion.

Example:

Let us assume that we have a boolean function F, which defined on two variables X and Y. The
minterms for the function F are expressed as shorthand notation is as follows:

F=∑(1,2,3)

Now, from this expression, we will find the SOP expression. The Boolean function F has two
input variables X and y and the output of F=1 for m1, m2, and m3, i.e., 1st, 2nd, and
3rd combinations. So,

F=∑(1,2,3)
F= m1 + m2 + m3
F= 01 + 10 + 11

Now, we replace zeros with either X' or Y' and ones with either X or Y. Simply, the complement
variable is used when the variable value is 1 otherwise the non-complement variable is used.

F = ∑(1,2,3)
F=01+10+11
F= A'B + AB' + AB

Using Product of Sum (POS):

A canonical product of sum is a boolean expression that entirely consists of maxterms. The
Boolean function F is defined on two variables X and Y. The X and Y are the inputs of the
boolean function F whose output is true when only one of the inputs is set to true. The truth table
for Boolean expression F is as follows:

Inputs Output

X Y F

0 0 0

0 1 1

1 0 1

1 1 0

In our minterm and maxterm section, we learned about how we can form the maxterm from the
variable's value. A column will be added for the maxterm in the above table. The complement of
the variables is taken whose value is 0, and the variables whose value is 1 will remain the same.

Inputs Output Minterm

X Y F M

0 0 0 X'+Y'

0 1 1 X'+Y

1 0 1 X+Y'

1 1 1 X+Y

Now, we will multiply all the minterms for which the output is false to find the desired canonical
POS(Product of sum) expression.

F=(X'+Y').(X+Y)
Converting Product of Sum (POS) to shorthand notation

The process of converting POS form to shorthand notation is the same as the process of finding
shorthand notation for maxterms. There are the following steps used to find the shorthand
notation of the given POS expression.

o Write the given POS expression.

o Find the shorthand notation of all the maxterms.
o Replace the minterms with their shorthand notations in the given expression.

Example: F = (X'+Y').(X+Y)

1. Firstly, we will write the POS expression:

F = (X'+Y').(X+Y)

2. Now, we will find the shorthand notations of the maxterms X'+Y' and X+Y.

X'+Y' = (00)2 = M0
X+Y = (11)2 = M3

3. In the end, we will replace all the minterms with their shorthand notations:

F=M0.M3

Converting shorthand notation to POS expression

The process of converting shorthand notation to POS is the reverse process of converting POS
expression to shorthand notation. Let's see an example to understand this conversion.

Example:

Let us assume that we have a boolean function F, defined on two variables X and Y. The
maxterms for the function F are expressed as shorthand notation is as follows:

F=∏(1,2,3)

Now, from this expression, we find the POS expression. The Boolean function F has two input
variables X and Y and the output of F=0 for M1, M2, and M3, i.e., 1st, 2nd, and 3rd combinations.
So,

F=∏(1,2,3)
F= M1.M2.M3
F= 01.10.11
Next, we replace zeros with either X or Y and ones with either X' or Y'. Simply, if the value of
the variable is 1, then we take the complement of that variable, and if the value of the variable is
0, then we take the variable "as is".

F = ∑(1,2,3)
F=01.10.11
F=(A+B').( A'+B).( A'+B')

Using K-Map to simplify Boolean expressions(upto 4 variables):

Minimization Of Boolean Expressions-

There are following two methods of minimizing or reducing the boolean expressions-

1. By using laws of Boolean Algebra

2. By using Karnaugh Maps also called as K Maps

Karnaugh Map-

The Karnaugh Map also called as K Map is a graphical representation

that provides a systematic method for simplifying the boolean expressions.

For a boolean expression consisting of n-variables, number of cells required in K Map = 2n cells.

Two Variable K Map-

Two variable K Map is drawn for a boolean expression consisting of two variables.
  The number of cells present in two variable K Map = 22 = 4 cells.
 So, for a boolean function consisting of two variables, we draw a 2 x 2 K Map.
Two variable K Map may be represented as-

Here, A and B are the two variables of the given boolean function.
Three Variable K Map-
Three variable K Map is drawn for a boolean expression consisting of three variables.
 The number of cells present in three variable K Map = 23 = 8 cells.
 So, for a boolean function consisting of three variables, we draw a 2 x 4 K Map.
Three variable K Map may be represented as-

Here, A, B and C are the three variables of the given boolean function.

Four Variable K Map-

  Four variable K Map is drawn for a boolean expression consisting of four variables.
 The number of cells present in four variable K Map = 24 = 16 cells.
 So, for a boolean function consisting of four variables, we draw a 4 x 4 K Map.

Four variable K Map may be represented as-

Here, A, B, C and D are the four variables of the given boolean function.

Karnaugh Map Simplification Rules-

To minimize the given boolean function,

 We draw a K Map according to the number of variables it contains.
 We fill the K Map with 0’s and 1’s according to its function.
 Then, we minimize the function in accordance with the following rules.

Rule-01:

 We can either group 0’s with 0’s or 1’s with 1’s but we can not group 0’s and 1’s
together.
 X representing don’t care can be grouped with 0’s as well as 1’s.
 NOTE
There is no need of separately grouping X’s i.e. they can be ignored if all 0’s and 1’s
are already grouped.

Rule-02:

 Groups may overlap each other.

Rule-03:

 We can only create a group whose number of cells can be represented in the power of 2.
 In other words, a group can only contain 2n i.e. 1, 2, 4, 8, 16 and so on number of cells.

Example-

Rule-04:

 Groups can be only either horizontal or vertical.

 We can not create groups of diagonal or any other shape.
Rule-05:

 Each group should be as large as possible.

Example-

Rule-06:

 Oppositegrouping and corner grouping are allowed.

 The example of opposite grouping is shown illustrated in Rule-05.
 The example of corner grouping is shown below.

Example-

Rule-07:

 There should be as few groups as possible.

PROBLEMS BASED ON KARNAUGH MAP-

Problem-01:

Minimize the following boolean function-

F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)

Solution-

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(A, B, C, D)
= (A’B + AB)(C’D + CD) + (A’B’ + A’B + AB + AB’)C’D + (A’B’ + AB’)(C’D’ + CD’)
= BD + C’D + B’D’

Thus, minimized boolean expression is-

F(A, B, C, D) = BD + C’D + B’D’
Problem-02:

Minimize the following boolean function-

F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)

Solution-

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(A, B, C, D)
= (A’B’ + A’B + AB + AB’)(C’D + CD) + (A’B’ + AB’)(C’D’ + C’D)
= D + B’C’

Thus, minimized boolean expression is-

F(A, B, C, D) = B’C’ + D
Problem-03:

Minimize the following boolean function-

F(A, B, C, D) = Σm(1, 3, 4, 6, 8, 9, 11, 13, 15) + Σd(0, 2, 14)

Solution-

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(A, B, C, D)
= (AB + AB’)(C’D + CD) + (A’B’ + AB’)(C’D + CD) + (A’B’ + AB’)(C’D’ + C’D) + (A’B’ +
A’B)(C’D’ + CD’)
= AD + B’D + B’C’ + A’D’

Thus, minimized boolean expression is-

F(A, B, C, D) = AD + B’D + B’C’ + A’D’
Problem-04:

Minimize the following boolean function-

F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 5)

Solution-

 Since the given boolean expression has 3 variables, so we draw a 2 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(A, B, C)
= A'(B’C’ + B’C) + A(BC + BC’)
= A’B’ + AB

Thus, minimized boolean expression is-

F(A, B, C) = AB + A’B’
Problem-05:

Minimize the following boolean function-

F(A, B, C) = Σm(1, 2, 5, 7) + Σd(0, 4, 6)

Solution-

 Since the given boolean expression has 3 variables, so we draw a 2 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(A, B, C)
= (A + A’)(B’C’ + B’C) + A(B’C’ + B’C + BC + BC’) + (A + A’)(B’C’ + BC’)
= B’ + A + C’

Thus, minimized boolean expression is-

F(A, B, C) = A + B’ + C’
Problem-06:

Minimize the following boolean function-

F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 4, 5)

Solution-

 Since the given boolean expression has 3 variables, so we draw a 2 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(A, B, C)
= (A + A’)(B’C’ + B’C) + A(B’C’ + B’C + BC + BC’)
= B’ + A

Thus, minimized boolean expression is-

F(A, B, C) = A + B’
Problem-07:

Minimize the following boolean function-

F(A, B, C, D) = Σm(0, 2, 8, 10, 14) + Σd(5, 15)

Solution-

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(A, B, C, D)
= (AB + AB’)CD’ + (A’B’ + AB’)(C’D’ + CD’)
= ACD’ + B’D’

Thus, minimized boolean expression is-

F(A, B, C, D) = ACD’ + B’D’
Problem-08:

Minimize the following boolean function-

F(A, B, C, D) = Σm(3, 4, 5, 7, 9, 13, 14, 15)

Solution-

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(A, B, C, D)
= A’B(C’D’ + C’D) + (A’B’ + A’B)(CD) + (AB + AB’)(C’D) + AB(CD + CD’)
= A’BC’ + A’CD + AC’D + ABC

Thus, minimized boolean expression is-

F(A, B, C, D) = A’BC’ + A’CD + AC’D + ABC

It is important to note that we are not considering the quad group because we have to consider
the duets anyhow.
Problem-09:

Consider the following boolean function-

F(W, X, Y, Z) = Σm(1, 3, 4, 6, 9, 11, 12, 14)

This function is independent ________ number of variables. Fill in the blank.

Solution-

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the above rules.

Then, we have-

Now,
F(W, X, Y, Z)
= (W’X + WX)(Y’Z’ + YZ’) + (W’X’ + WX’)(Y’Z + YZ)
= XZ’ + X’Z
=X⊕Z

Thus, minimized boolean expression is-

F(W, X, Y, Z) = X ⊕ Z

Clearly, the given boolean function depends on only two variables X and Z.
Hence, it is independent of other two variables W and Y.

Logic Gate:

Logic gates are the fundamental components of all digital circuits and systems. In digital
electronics, there are seven main types of logic gates used to perform various logical
operations. A logic gate is basically an electronic circuit designed by using components like
diodes, transistors, resistors, capacitors, etc., and capable of performing logical operations.

Types of Logic Gates

A logic gate is a digital gate that allows data to be manipulated. Logic gates, use logic to
determine whether or not to pass a signal. Logic gates, on the other hand, govern the flow of
information based on a set of rules.
The logic gates can be classified into the following major types:
1. Basic Logic Gates
There are three basic logic gates:
1. AND Gate
2. OR Gate
3. NOT Gate
2. Universal Logic Gates
In digital electronics, the following two logic gates are considered as universal logic gates:
1. NOR Gate
2. NAND Gate
3. Derived Logic Gates
The following two are the derived logic gates used in digital systems:
1. XOR Gate
2. XNOR Gate

OR Gate
In digital electronics, there is a type of basic logic gate which produces a low or logic 0 output
only when its all inputs are low or logic 0. For all other input combinations, the output of the
OR gate is high or logic 1. This logic gate is termed as OR gate. An OR gate can be designed
to have two or more inputs but only one output. The primary function of the OR gate is to
perform the logical sum operation.

Properties of OR Gate:
An OR gate have the following two properties:
 It can have two or more input lines at a time.
 When all of the inputs to the OR gate are low or logic 0, the output of it is low or logic 0.
The operation of an OR gate can be mathematically described through a mathematical
expression called Boolean expression of the OR gate.
The boolean expression for a two input OR gate is given by,
Z=A+B
The boolean expression for a three-input OR gate is,
Z=A+B+C
Here, A, B, and C are inputs and Z is the output variables. We can extend this boolean
expression to any number of input variables.

Truth Table of OR Gate:

The truth table of an OR gate describes the relationship between inputs and output. The
following is the truth table for the two-input OR gate:
Input Output

A B A OR B

0 0 0

0 1 1

1 0 1

1 1 1

Symbol of OR Gate:
The logic symbol of a two-input OR gate is shown in the following figure.

AND Gate
In digital electronics, the AND gate is one of the basic logic gate that performs the logical
multiplication of inputs applied to it. It generates a high or logic 1 output, only when all the
inputs applied to it are high or logic 1. Otherwise, the output of the AND gate is low or logic 0.

Properties of AND Gate:

The following are two main properties of the AND gate:
 AND gate can accept two or more than two input values at a time.
 When all of the inputs are logic 1, the output of this gate is logic 1.
The operation of an AND gate is described by a mathematical expression, which is called the
Boolean expression of the AND gate.
For two-input AND gate, the Boolean expression is given by,
Z=A.B
Where, A and B are inputs to the AND gate, while Z denotes the output of the AND gate.
We can extend this expression to any number of input variables, such as,
Z=A.B.C.D…

Truth Table of AND Gate:

The truth table of a two input AND gate is given below:
Input Output

A B A AND B
Input Output

0 0 0

0 1 0

1 0 0

1 1 1

Symbol of AND Gate:

The logic symbol of a two input AND gate is shown in the following figure.

NOT Gate
In digital electronics, the NOT gate is another basic logic gate used to perform complement of
an input signal applied to it. It takes only one input and one output. The output of the NOT
gate is complement of the input applied to it. Therefore, if we apply a low or logic 0 output to
the NOT gate is gives a high or logic 1 output and vice-versa. The NOT gate is also known as
inverter, as it performs the inversion operation.

Properties of NOT Gate:

 The output of a NOT gate is complement or inverse of the input applied to it.
 NOT gate takes only one output.
The logical operation of the NOT gate is described by its boolean expression, which is given
below.
Z=A
The bar over the input variable A represents the inversion operation.
Truth Table of OR Gate:
The truth table describes the relationship between input and output. The following is the truth
table for the NOT gate:

Input Output

A NOT A
Input Output

0 1

1 0

Symbol of NOT Gate

The logic circuit symbol of a NOT gate is shown in the following figure. Here, A is the input
line and Z is the output line.

Universal Gates
The universal gates are the logic gates that are versatile in that they can be programmed to
execute any Boolean function. The most popular types among them are NAND and NOR gates.

To explain it further, the input of the universal gates can be interconnected in one way or the
other while the inputs can also be inverted in one way or the other to get the AND, OR, NOT,
XOR and XNOR basic Boolean functions.
There are two universal gates.
1) NAND Gate
2) NOR Gate
NOR Gate
The NOR gate is a type of universal logic gate that can take two or more inputs but one output.
It is basically a combination of two basic logic gates i.e., OR gate and NOT gate. Thus, it can
be expressed as,
NOR Gate = OR Gate + NOT Gate
In other words, a NOR gate is an OR gate followed by a NOT gate.

Properties of NOR Gate:

The following are two important properties of NOR gate:
 A NOR gate can have two or more inputs and gives an output.
 A NOR gate gives a high or logic 1 output only when its all inputs are low or logic 0.
Similar to basic logic gates, we can describe the operation of a NOR gate using a mathematical
equation called boolean expression of the NOR gate.
The boolean expression of a two input NOR gate is given below:
C=A+B
We can extend this expression to any number of input variables.
In the above boolean expressions, the variables A and B are called input variables while the
variable C is called the output variable.
Truth Table of NOR Gate:
The following is the truth table of a two-input NOR gate showing the relationship between its
inputs and output:

Input Output

A B A NOR B

0 0 1

0 1 0

1 0 0

1 1 0

NAND Gate
In digital electronics, the NAND gate is another type of universal logic gate used to perform
logical operations. The NAND gate performs the inverted operation of the AND gate. Similar
to NOR gate, the NAND gate can also have two or more input lines but only one output line.
The NAND gate is also represented as a combination of two basic logic gates namely, AND
gate and NOT gate. Hence, it can be expressed as
NAND Gate = AND Gate + NOT Gate

Properties of NAND Gate:

The following are the two key properties of NAND gate:
 NAND gate can take two or more inputs at a time and produces one output based on the
combination of inputs applied.
 NAND gate produces a low or logic 0 output only when its all inputs are high or logic 1.
We can describe the expression of NAND gate through a mathematical equation called its
boolean expression. Here is the boolean expression of a two input NAND gate.
C=AB
In this expression, A and B are the input variables and C is the output variable. We can extend
this relation to any number of input variables like three, four, or more.

Truth Table of NAND Gate:

The truth table is a table of inputs and output that describes the operation of the NAND gate
and shows the logical relationship between them:
Input Output

A B A NAND B

0 0 1

0 1 1

1 0 1

1 1 0

Symbol of NAND Gate:

The logic symbol of a NAND gate is represented as a AND gate with a bubble on its output
end as depicted in the following figure. It is the symbol of a two-input NAND gate.

XOR Gate
In digital electronics, there is a specially designed logic gate named, XOR gate, which is used
in digital circuits to perform modulo sum. It is also referred to as Exclusive OR gate or Ex-
OR gate. The XOR gate can take only two inputs at a time and give an output. The output of
the XOR gate is high or logic 1 only when its two inputs are dissimilar.

Properties of XOR Gate:

The following two are the main properties of the XOR gate:
 It can accept only two inputs at a time. There is nothing like a three or more input XOR
gate.
 The output of the XOR gate is logic 1 or high, when its inputs are dissimilar.
The operation of the XOR gate can be described through a mathematical equation called its

Z=A⊕B
boolean expression. The following is the boolean expression for the output of the XOR gate.

Here, Z is the output variable, and A and B are the input variables.
This expression can also be written as follows:
Z=AB+AB
Truth Table of XOR Gate:
The truth table is a table of inputs and output that describe the relationship between them and
the operation of the XOR gate for different input combinations. The truth table of the XOR
gate is given below:
Input Output

A B A XOR B

0 0 0

0 1 1

1 0 1

1 1 0

Symbol of XOR Gate:

The logic symbol of an XOR gate is shown in the following figure.

XNOR Gate
The XNOR gate is another type of special purpose logic gate used to implement exclusive
operation in digital circuits. It is used to implement the Exclusive NOR operation in digital
circuits. It is also called the Ex-NOR or Exclusive NOR gate. It is a combination of two logic
gates namely, XOR gate and NOT gate. Thus, it can be expressed as,
XNOR Gate = XOR Gate + NOT Gate
The output of an XNOR gate is high or logic 1 when its both inputs are similar. Otherwise the
output is low or logic 0. Hence, the XNOR gate is used as a similarity detector circuit.

Properties of XNOR Gate:

The following are two key properties of XNOR gate:
 XNOR gate takes only two inputs and produces one output.
 The output of the XNOR gate is high or logic 1 only when it has similar inputs.
The operation of XNOR gate can be described through a mathematical equation called the

Y=A⊙B
boolean expression of XNOR gate. Here is the boolean expression of the XNOR gate.

We can also write this expression as follows:

Y=AB+AB
Here, the A and B are inputs and Y is the output.

Truth Table of XNOR Gate:

The truth table of the XNOR gate is given below. This truth table is describing the relationship
between inputs and output of the XNOR gate.
Input Output

A B A XNOR B

0 0 1

0 1 0

1 0 0

1 1 1

Symbol of XNOR Gate:

The logic symbol of XNOR gate is shown in the following figure. Here, A and B are inputs
and Y is the output.

Implementing NOT, OR, AND into NAND gate:

Implementing NOT gate using NAND gate:

(A.A)'=A' (Idempotent Law)

Implementing NOT Gate using NAND Gate

Implementing AND gate using NAND gate:

((AB)' (AB)')'= ((AB)')' (By Idempotent Law)

= AB (Involution Law)

Implementing AND Gate using NAND Gate

Implementing OR gate using NAND gate:

((AA)'(BB)')'= (A'B')' (By Idempotent Law)

= A''+B'' (By De Morgan’s Law)

= A+B ( By involution Law)

Implementing OR Gate using NAND Gate

Implementing NOT, OR, AND into NOR gate:

Implementing NOT gate using NOR gate:

(A+A)'=A' (By Idempotent Law)

Implementation of NOT Gate using NOR Gate

Implementing OR gate using NOR gate:

((A+A)'+(B+B)')'= (A'+B')' (By Idempotent Law)

= A''.B'' (By De Morgan’s Law)

= A.B ( By involution Law)

Implementing OR Gate using NOR Gate

Implementing AND gate using NOR gate:

((A+A)'(B+B)')'= (A'+B')' (By Idempotent Law)

= A''.B'' (By De Morgan’s Law)

= A.B ( By involution Law)

Implementing AND Gate using NOR Gate

Half Adder

The Half-Adder is a basic building block of adding two numbers as two inputs and produce out
two outputs. The adder is used to perform OR operation of two single bit binary numbers.
The augent and addent bits are two input states, and 'carry' and 'sum 'are two output states of
the half adder.
Block diagram

Truth Table

In the above table,

1. 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
2. The carry output is 0 in case where both the inputs are not 1.
3. The least significant bit of the sum is defined by the 'sum' bit.

The SOP form of the sum and carry are as follows:

Sum = x'y+xy'
Carry = xy

Construction of Half Adder Circuit:

In the block diagram, we have seen that it contains two inputs and two outputs.
The augent and addent bits are the input states, and carry and sum are the output states of the
half adder. The half adder is designed with the help of the following two logic gates:

1. 2-input AND Gate.

2. 2-input Exclusive-OR Gate or Ex-OR Gate

1. 2-input Exclusive-OR Gate or Ex-OR Gate

The Sum bit is generated with the help of the Exclusive-OR or Ex-OR Gate.
The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B' are the inputs, and
the 'SUMOUT' is the final outcome after performing the XOR operation of both numbers.

The truth table of the EX-OR gate is as follows:

From the above table, it is clear that the XOR gate gives the result 1 when both of the inputs are
different. When both of the inputs are the same, the XOR gives the result 0. To learn more about
the XOR gate, click here.

2. 2-input AND Gate:

The XOR gate is unable to generate the carry bit. For this purpose, we use another gate
called AND Gate. The AND gate gives the correct result of the carry.

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The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are the inputs, and
'OUT' is the final outcome after performing AND operation of both numbers.

There is the following truth table of AND Gate:

From the above table, it is clear that the AND gate gives the result 1 when both of the inputs are
1. When both of the inputs are different and 0, the AND gates gives the result 0. To learn more
about the AND gate, click here.

Half-Adder logical circuit:

So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and provide the sum
and carry.

There is the following Boolean expression of Half Adder circuit:

Sum= A XOR B (A+B)

Carry= A AND B (A.B)

Implementation of Half Adder using NAND Gates : Total 5 NAND gates are required to
Implement Half Adder

Implementation of Half Adder using NOR gates : Total 5 NOR gates are required to
implement Half Adder

Full Adder

The half adder is used to add only two numbers. To overcome this problem, the full adder was
developed. The full adder is used to add three 1-bit binary numbers A, B, and carry C. The full
adder has three input states and two output states i.e., sum and carry.
Block diagram

Truth Table

In the above table,

1. 'A' and' B' are the input variables. These variables represent the two significant bits which
are going to be added
2. 'Cin' is the third input which represents the carry. From the previous lower significant
position, the carry bit is fetched.
3. The 'Sum' and 'Carry' are the output variables that define the output values.
4. The eight rows under the input variable designate all possible combinations of 0 and 1
that can occur in these variables.

The SOP form can be obtained with the help of K-map as:
Sum = x' y' z+x' yz+xy' z'+xyz
Carry = xy+xz+yz

Construction of Half Adder Circuit:

The above block diagram describes the construction of the Full adder circuit. In the above
circuit, there are two half adder circuits that are combined using the OR gate. The first half adder
has two single-bit binary inputs A and B. As we know that, the half adder produces two outputs,
i.e., Sum and Carry. The 'Sum' output of the first adder will be the first input of the second half
adder, and the 'Carry' output of the first adder will be the second input of the second half adder.
The second half adder will again provide 'Sum' and 'Carry'. The final outcome of the Full adder
circuit is the 'Sum' bit. In order to find the final output of the 'Carry', we provide the 'Carry'
output of the first and the second adder into the OR gate. The outcome of the OR gate will be the
final carry out of the full adder circuit.

The MSB is represented by the final 'Carry' bit.

The full adder logic circuit can be constructed using the 'AND' and the 'XOR' gate with an OR
gate.

The actual logic circuit of the full adder is shown in the above diagram. The full adder circuit
construction can also be represented in a Boolean expression.

Sum:
o Perform the XOR operation of input A and B.
 o Perform the XOR operation of the outcome with carry. So, the sum is (A XOR B) XOR
Cin which is also represented as:
(A ⊕ B) ⊕ Cin

Carry:
1. Perform the 'AND' operation of input A and B.
2. Perform the 'XOR' operation of input A and B.
3. Perform the 'OR' operations of both the outputs that come from the previous two steps.
So the 'Carry' can be represented as:
A.B + (A ⊕ B)

Binary Addition
Binary addition works sane as a to regular addition, but it only uses two digits: 0 and 1.

Always remember this in your mind

0+0=0
0+1=1
1+0=1
1 + 1 = 10 (1 is a carry)

Example:
We are working on 13 = 1 1 0 1 and 11 = 1 0 1 1
1 1 0 1 + 1 0 1 1 ──────────── 1 1 0 0 0
So, the final answer is 11000, If we convert in a decimal so answer is 24.

Binary Adder

The registers play an important role in performing the micro-operations. The registers hold the
digital component and the data which performs the arithmetic operation. The Binary Adder is a
logical circuit which is used to perform the addition operation of two binary number of any
length.

The Binary Adder is formed with the help of the Full-Adder circuit. The Full-Adders are
connected in series, and the output carry of the first Adder will be treated as the input carry of the
next Full-Adder.

N-Bit Parallel Adder

The Full Adder is used to sum two single-bit binary numbers with carry input. In digital
calculation, we need to add two n-bit binary numbers rather than only single-bit binary numbers.
For this purpose, we need to use n-bit parallel Adder. In order to get N-bit parallel adder, we
cascade the n number of Full Adders. The carry output of the first Adder is treated as the carry
input of the second Adder.
4-bit Binary Adder

o The 'A' and 'B' are the augend, and addend bits are defined by the subscript numbers. The
subscripts start from right to left, and the lower-order bit is defined by subscript '0'.
o The C0, C1, C2, and C3 are the carry inputs which are connected together as a chain
using Full Adder. The C4 is the carry output produced by the last Full-Adder.
o The Cout of the first Adder is connected as the Cin of the next Full-Adder.
o The S0, S1, S2, and S3 are the sum outputs that produce the sum of augend and addend
bits.
o The inputs for the input variable 'A' and 'B' are fetched from different source registers.
For example, the bit for the input variable 'A' comes from register 'R1', and a bit for the
input variable 'B' comes from register 'R2'.
o The outcome produced by adding both input variables is stored into either third register
or to one of the source registers.

Binary Adder-Subtractor

A Binary Adder-Subtractor is a special type of circuit that is used to perform both operations,
i.e., Addition and Subtraction. The operation which is going to be used depends on the values
contained by the control signal. In Arithmetic Logical Unit, it is one of the most important
components.

To work with Binary Adder-Subtractor, it is required that we have knowledge of the XOR gate,
Full-Adder, Binary Addition, and subtraction.

For example, we will take two 4-bit binary numbers 'X' and 'Y' for the operation with digits.

X0 X1 X2 X3 for X
Y0 Y1 Y2 Y3 for Y

The Binary Adder-Subtractor is a combination of 4 Full-Adder, which is able to perform the

addition and subtraction of 4-bit binary numbers. The control line determines whether the
operation being performed is either subtraction or addition. This determination is done by the
binary values 0 and 1, which is hold by K.
In the above diagram, the control lines of the first Full-Adder is directly coming as its input(input
carry C0). The X0 is the least significant bit of A, which is directly inputted in the Full-Adder.
The result produced by performing the XOR operation of Y 0 and K is the third input of the
Binary Adder-Subtractor. The sum/difference(S0) and carry(C0) are the two outputs produced
from the First Full-adder.

When the value of K is set to true or 1, the Y 0⨁K produce the complement of Y0 as the output.
So the operation would be X+Y0', which is the 2's complement subtraction of X and Y. It means
when the value of K is 1; the subtraction operation is performed by the binary Adder-Subtractor.

In the same way, when the value of K is set to 0, the Y 0⨁K produce Y0 as the output. So the
operation would be X+Y0, which is the binary addition of X and Y. It means when the value of K
is 0; the addition operation is performed by the binary Adder-Subtractor.

The carry/borrow C0 is treated as the carry/borrow input for the second Full-Adder. The
sum/difference S0 defines the least significant bit of the sum/difference of numbers X and Y. Just
like X0, the X1, X2, and X3 are faded directly to the 2 nd, 3rd, and 4th Full-Adder as an input. The
outputs after performing the XOR operation of Y 1, Y2, and Y3 inputs with K are the third inputs
for 2nd, 3rd, and 4th Full-Adder. The carry C1, C2 are passed as the input to the Full-Adder. C out is
the output carry of the sum/difference. To form the final result, the S 1, S2, S3 are recorded with s0.
We will use n number of Full-Adder to design the n-bit binary Adder-Subtractor.

Example:

We assume that we have two 3 bit numbers, i.e., X=100 and Y=011, and feed them in Full-
Adder as an input.

X0 = 0 X1 = 0 X2 = 1

Y0 = 1 Y1 = 1 & Y2 = 0

For K=0:

Y0⨁K=Y0 and Cin=K=0

So, from first Full-Adder

S0 = X0+Y0+Cin

S0= 0+1+0

S0=1

C0=0

Similarly,

S1 = X1+Y1+C0
S1 = 0+1+0
S1=1 and C1=0

Similarly,

S2 = X2+Y2+C1
S2 = 1+0+0
S2=1 and C2=0

Thus,

X= 100 =4
Y = 011 = 3
Sum = 0111 = 7

For K=1

Y0⨁K=Y0' and Cin=k=1

So,

S0 = X0+Y0'+Cin
S0 = 0+0+1
S0=1 and C0=0

Similarly,

S1 = X1+Y1'+C0
S1 = 0+0+0
S1=0 and C1=0

Similarly,

S2 = X2+Y2'+C1
S2 = 1+1+0
S2=0 and C2=0

Thus,
X = 010 = 4
Y = 011 = 3

Difference = 001 = 1

Serial Binary Adder

Serial binary adder is a combinational logic circuit that performs the addition of two binary
numbers in serial form. Serial binary adder performs bit by bit addition. Two shift registers are
used to store the binary numbers that are to be added.
A single full adder is used to add one pair of bits at a time along with the carry. The carry output
from the full adder is applied to a D flip-flop. After that output is used as carry for next
significant bits. The sum bit from the output of the full adder can be transferred into a third shift
register.
Block diagram of Serial Binary Adder:

Shift Registers :
Shift Register is a group of flip flops used to store multiple bits of data. There are two shift
registers used in the serial binary adder. In one shift register augend is stored and in other shift
register addend is stored.

Full Adder :
Full adder is the combinational circuit which takes three inputs and gives two outputs as sum and
carry. The circuit adds one pair at a time with the help of it.

D Flip-flop :
the carry output from the full adder is applied on the D flip-flop. Further, the output of D flip-
flop is used as a carry input for the next pair of significant bits.

Working Process:
Following is the procedure of addition using serial binary adder:
 Step-1:
The two shift registers A and B are used to store the numbers to be added.
 Step-2:
A single full adder is used too add one pair of bits at a time along with the carry.
 Step-3:
The contents of the shift registers shift from left to right and their output starting from a and b
 are fed into a single full adder along with the output of the carry flip-flop upon application of
each clock pulse.
 Step-4:
The sum output of the full adder is fed to the most significant bit of the sum register.
 Step-5:
The content of sum register is also shifted to right when clock pulse is applied.
 Step-6:
After applying four clock pulse the addition of two registers (A & B) contents are stored in
sum register.

ADVANTAGES AND DISADVANTAGES OF SERIAL ADDER:

ADVANTAGES:

1.It uses only one full adder to add two n-bit numbers.

2.It uses less hardware resulting in cost saving and less power comsumption.

3.It involves less complexity in hardware implementation.

4.Its implementation is easy due to its sequential nature.

5.It is used in applications where data has to be processed sequentially.

6.It requires small physical area on an integrated circuit.

DISADVANTAGES:

1.The operating speed of serial adder is slower compared to parallel adder.

2.Computation time increases as number of bits increase.

3.It is not suitable for applications where speed is critical.

4.It is not suitable for applications where parallel processing is needed.

ADVANTAGES AND DISADVANTAGES OF PARALLEL ADDER:

ADVANTAGES:

1.It adds two n-bit numbers simultaneously or parallelly.

2.Its operating speed is significantly higher than serial adder.

3.The computation time of addition is considerably reduced.

4.It is used when high speed arithmetic operations are to be done rapidly.

5.It is used in applications where parallel processing of data is reduced.

DISADVANTAGES:

1.It requires n full adders to add two n-bit binary numbers.

2.Number of full adders increases as number of bits increase.

3.Hardware complexity is considerably higher than serial adder.

4.Cost of hardware increases as number of bits increase.

5.It requires larger physical area on an integrated circuit.

DISTINGUISH BETWEEN SERIAL ADDER AND PARALLEL ADDER:

PARALLEL ADDER SERIAL ADDER

Adds all bits simultaneously at a time. Adds one bit at a time after another in
sequential order.
Operating speed is faster. Operating speed is slower.
n no.of full adders are needed for adding n bits. One full added is enough to add n no.of.bits.
Hardware complexity is more. Hardware complexity is less.
Cost is more. Cost is less.
Time taken for addition is not affected by Time taken for addition increases as number of
no.of.bits in two numbers. bits increases in two numbers.
Covers larger physical area in an integrated Covers smaller physical area on an integrated
circuit. circuit
Can be implemented using shift registers. Can be implemented using registers with
parallel load capacity.
Suitable for applicqations where speed is the Suitable for applications where speed is not a
crucial factor for arithmetic operations. crucial factor for arithmetic operations.
Digital comparator/Magnitude Comparator:
Magnitude comparator is a type of Combinational circuit , It Basically compares two binary
numbers and determines their relative magnitude. It gives output whether one number is
greater than the other, or less than or equal. These comparators are used in digital systems,
such as for sorting networks, and decision-making circuits to handle numerical comparisons
perfectly without any error.

The circuit works by comparing the bits of the two numbers starting from the most significant
bit (MSB) and moving toward the least significant bit (LSB) . At each bit position, the two
corresponding bits of the numbers are compared. If the bit in the first number is greater than
the corresponding bit in the second number, the A>B output is set to 1, and the circuit
immediately determines that the first number is greater than the second. Similarly, if the bit in
the second number is greater than the corresponding bit in the first number, the A<B output is
set to 1, and the circuit immediately determines that the first number is less than the second.

If the two corresponding bits are equal, the circuit moves to the next bit position and compares
the next pair of bits. This process continues until all the bits have been compared. If at any
point in the comparison, the circuit determines that the first number is greater or less than the
second number, the comparison is terminated, and the appropriate output is generated.

If all the bits are equal, the circuit generates an A=B output, indicating that the two numbers
are equal.

1-Bit Magnitude Comparator

A comparator used to compare two bits is called a single-bit comparator. It consists of two
inputs each for two single-bit numbers and three outputs to generate less than, equal to, and
greater than between two binary numbers.
The truth table for a 1-bit comparator is given below.

From the above truth table logical expressions for each output can be expressed as follows.
A>B: AB’
A<B: A’B
A=B: A’B’ + AB
By using these Boolean expressions, we can implement a logic circuit for this comparator as
given below.

2-Bit Magnitude Comparator

A comparator used to compare two binary numbers each of two bits is called a 2-bit
Magnitude comparator. It consists of four inputs and three outputs to generate less
than, equal to, and greater than between two binary numbers.
The truth table for a 2-bit comparator is given below.
INPUT OUTPUT

A1 A0 B1 B0 A<B A=B A>B

0 0 0 0 0 1 0

0 0 0 1 1 0 0

0 0 1 0 1 0 0

0 0 1 1 1 0 0
INPUT OUTPUT

0 1 0 0 0 0 1

0 1 0 1 0 1 0

0 1 1 0 1 0 0

0 1 1 1 1 0 0

1 0 0 0 0 0 1

1 0 0 1 0 0 1

1 0 1 0 0 1 0

1 0 1 1 1 0 0

1 1 0 0 0 0 1

1 1 0 1 0 0 1

1 1 1 0 0 0 1

1 1 1 1 0 1 0

From the above truth table, K-map for each output can be drawn as follows.
From the above K-maps logical expressions for each output can be expressed as
follows.

A>B:A1B1’ + A0B1’B0’ + A1A0B0’

A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’

: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)

A<B:A1’B1 + A0’B1B0 + A1’A0’B0

By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below.

4-Bit Magnitude Comparator

A comparator used to compare two binary numbers each of four bits is called a 4-bit
magnitude comparator. It consists of eight inputs each for two four-bit numbers and
three outputs to generate less than, equal to, and greater than between two binary
numbers.
In a 4-bit comparator, the condition of A>B can be possible in the following four
cases.
1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
Similarly, the condition for A<B can be possible in the following four cases.
1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1
The condition of A=B is possible only when all the individual bits of one number
exactly coincide with the corresponding bits of another number.
From the above statements, logical expressions for each output can be expressed as
follows.

A=B

(A3 Ex-Nor B3) (A2 Ex-Nor 82) (A1 Ex-Nor B1) (A0 Ex-Nor B0)
A>B

A<B

By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below.