Unit- 5

Semiconductor Memories
and VLSI Design
Methodology

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 VLSI DESIGN METHODOLOGIES
Using the full-custom design style (where the geometry and the placement of every transistor can be optimized individually) requires a longer
time until design maturity can be reached, yet the inherent flexibility of adjusting almost every aspect of circuit design allows far more opportunity
for circuit performance improvement during the design cycle. The final product typically has a high level of performance (e.g. high processing speed,
low power dissipation) and the silicon area is relatively small because of better area utilization. But this comes at a larger cost in terms of design
time. In contrast, using a semi-custom design style (such as standard-cell based design or FPGA) will allow a shorter design time until design
maturity can be achieved. In the early design phase, the circuit performance can be even higher than that of a full-custom design, since some of the
components used in semi-custom design are already optimized.

Impact of different VLSI design styles upon the design cycle time and the achievable circuit performance.
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Progressive performance improvement of a VLSI product for each new generation
of manufacturing technology. Shorter design cycle times are essential for economic viability.
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 VLSI Design Flow

The Y-chart (first introduced by D. Gajski) shown

in Fig. illustrates a design flow for most logic
chips, using design activities on three different
axes (domains) which resemble the letter "Y.

Typical VLSI design flow in three domains (Y-chart representation)

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The Y-chart consists of three domains of representation, namely (i) behavioral domain, (ii) structural domain,
and (iii) geometrical layout domain. The design flow starts from the algorithm that describes the behavior of the
target chip. The corresponding architecture of the processor is first defined. It is mapped onto the chip surface
by floor planning. The next design evolution in the behavioral domain defines finite state machines (FSMs)
which are structurally implemented with functional modules such as registers and arithmetic logic units (ALUs).
These modules are then geometrically placed onto the chip surface using CAD tools for automatic module
placement followed by routing, with a goal of minimizing the interconnects area and signal delays. The third
evolution starts with a behavioral module description. Individual modules are then implemented with leaf cells.
At this stage the chip is described in terms of logic gates (leaf cells), which can be placed and interconnected by
using a cell placement and routing program.

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Design Hierarchy
The use of the hierarchy, or "divide and conquer"
technique involves dividing a module into sub-
modules and then repeating this operation on the
sub-modules until the complexity of the smaller
parts becomes manageable. This approach is very
similar to software development wherein large
programs are split into smaller and smaller
sections until simple subroutines, with well-
defined functions and interfaces, can be written.
In Section, we have seen that the design of a
VLSI chip can be represented in three domains.
Correspondingly, a hierarchy structure can be
described in each domain separately. However, it
is important for the simplicity of design that the
hierarchies in different domains be mapped into
each other easily.

Structural decomposition of a 4-bit adder, showing the levels of

hierarchy.
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Concepts of Regularity, Modularity and Locality
The hierarchical design approach reduces the design complexity by dividing the large system into several
sub-modules. Usually, other design concepts and design approaches are also needed to simplify the
process.

Regularity means that the hierarchical decomposition of a large system should result in not only simple,
but also similar blocks, as much as possible. A good example of regularity is the design of array structures
consisting of identical cells - such as a parallel multiplication array. Regularity can exist at all levels of
abstraction. Regularity usually reduces the number of different modules that need to be designed and
verified, at all levels of abstraction. For example, at the transistor level, uniformly sized transistors
simplify the design and at the logic level, identical gate structures can be used.

Modularity in design means that the various functional blocks which make up the larger system must
have well-defined functions and interfaces. Modularity allows that each block or module can be designed
relatively independently from each other, since there is no ambiguity about the function and the signal
interface of these blocks. All of the blocks can be combined with ease at the end of the design process, to
form the large system. The concept of modularity enables the parallelization of the design process. The
well-defined functionality and signal interface also allow the use of generic modules in various designs.

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By defining well-characterized interfaces for each module in the system, we effectively ensure that the internals
of each module become unimportant to the exterior modules. Internal details remain at the local level. The
concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-
distance connections as much as possible. This last point is extremely important for avoiding long interconnect
delays. Time-critical operations should be performed locally, without the need to access distant modules or
signals. If necessary, the replication of some logic may solve this problem in large system architectures.

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VLSI Design Styles
Several design styles can be considered for chip implementation of specified algorithms or logic functions. Each
design style has its own merits and shortcomings, and thus a proper choice has to be made by designers in order
to provide the specified functionality at low cost and in a timely manner.
Field Programmable Gate Array (FPGA)

General architecture of Xilinx FPGAs.

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Detailed view of switch matrices and interconnection routing between CLBs

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Gate Array Design
In terms of fast prototyping capability, the gate array (GA) ranks second after the FPGA with a typical turn-
around time of a few days. While user programming is central to the design implementation of the FPGA chip,
metal mask design and processing is used for GA. Gate array implementation requires a two-step manufacturing
process: The first phase, which is based on generic (standard) masks, results in an array of uncommitted
transistors on each GA chip. These uncommitted chips can be stored for later customization, which is completed
by defining the metal interconnects between the transistors of the array.

Basic processing steps required for gate array implementation.

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Standard-Cells Based Design
The standard-cells based design is one of the most prevalent full custom design styles which require
development of a full custom mask set. The standard cell is also called the polycell. In this design style, all of
the commonly used logic cells are developed, characterized, and stored in a standard cell library. A typical
library may contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates,
D-latches, and flip-flops.
Each cell is characterized according to several different characterization categories, including
 Delay time versus load capacitance
 Circuit simulation model
 Timing simulation model
 Fault simulation model
 Cell data for place-and-route
 Mask data

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A simplified floorplan of standard-cell-based design.

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Simplified floorplan of a standard-cell-based design, consisting
of two separate blocks and a common signal bus

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Full Custom Design
In a truly full-custom design, the entire mask design is done a new without use of any library. However, the
development cost of such a design style is becoming prohibitively high. Thus, the concept of design reuse is
becoming popular in order to reduce design cycle time and development cost. The most rigorous full custom
design can be the design of a memory cell, be it static or dynamic. Since the same layout design is replicated,
there would not be any alternative to high density memory chip design. For logic chip design, a good
compromise can be achieved by using a combination of different design styles on the same chip, such as
standard cells, data-path cells and programmable logic arrays (PLAs). In real full-custom layout in which the
geometry, orientation and placement of every transistor is done individually by the designer, design productivity
is usually very low - typically a few tens of transistors per day, per designer.

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Design Quality
It is desirable to measure the quality of design in order to improve the chip design. Although no universally
accepted metric exists to measure the design quality, the following criteria are' considered to be important:
 Testability
 Yield and manufacturability
 Reliability
 Technology updateability

Testability
Developed chips are eventually inserted into printed circuit boards or multichip modules for system applications.
The correct functionality of the system hinges upon the correct functionality of the chips used. Therefore,
fabricated chips should be fully testable to ensure that all the chips passing the specified chip test can be inserted
into the system, either in packaged or in bare die form, without causing failures. Such a goal requires

Generation of good test vectors

Availability of reliable test fixture at speed

Design of testable chip

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Yield and Manufacturability
The chip yield can be calculated by dividing the number of good tested chips by the total number of
tested chips. However, this calculation may not correctly reflect the quality of the design or the
processing. The most strict definition of the yield can be the number of good tested chips divided by
the total number of chip sites available at the start of the wafer processing. However, since some
wafers may be scrapped in the process line due to mishandling or for other reasons, such a metric
may not reflect the design quality. Also, poor design of the wafer array for chips may cause some
chips to fail routinely due to uncontrollable process variations and handling problems. On the other
hand, poor chip design can cause processing problems and, therefore, drop-outs during the
processing. In such a case, the first yield metric will overestimate the design quality. The chip yield
can be further divided into the following subcategories:
Functional yield
Parametric yield
The functional yield is obtained by testing the functionality of the chip at a speed usually lower than
the required chip speed. The functional test weeds out the problems of shorts, opens and leakage
current, and can detect logic and circuit design faults.
The parametric test is usually performed at the required speed on chips that passed the functional test.
All the delay testing is performed at this stage. Poor design that failed to consider uncontrollable
process variations which cause significant variations in chip performance may cause poor parametric
yield, thus, significant manufacturing problems.

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Reliability
The reliability of the chip depends on the design and process conditions. The major causes for chip reliability
problems can be characterized into the following:
 Electrostatic discharge (ESD) and electrical overstress (EOS)
 Electromigration
 Latch-up in CMOS I/O and internal circuits
 Hot-carrier induced aging

 Oxide breakdown
 Single event upset
 Power and ground bouncing

 On-chip noise and crosstalk

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Technology Updateability
Process technology development has progressed rapidly and as a result, the lifespan of a given technology
generation has remained almost constant even for submicron technologies. Yet, the time pressure to develop
increasingly more complex chips in a shorter time is constantly increasing. Under such circumstances, the chip
products often have to be technology-updated to new design rules. Even without any change in the chip's
functionality, the task of updating the mask to new design rules is very formidable. The so-called "dumb shrink"
method whereby mask dimensions are scaled uniformly, is rarely practiced due to nonideal scaling of device
feature sizes and technology parameters. Thus, the design style should be chosen such that the technology
update of the chip,or functional modules for design reuse can be achieved quickly with minimal cost.

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Computer-Aided Design Technology
Computer-aided design (CAD) tools are essential for timely development of integrated circuits. Although CAD
tools cannot replace the creative and inventive parts of the design activities, the majority of time-consuming and
computation intensive mechanistic parts of the design can be executed by using CAD tools. The CAD
technology for VLSI chip design can be categorized into the following areas:
*High level synthesis
*Logic synthesis
*Circuit optimization
*Layout
*Simulation
*Design rules checking

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Synthesis Tools
The high-level synthesis tools using hardware description languages (HDLs), such as VHDL or Verilog, address
the automation of the design phase in the top level of the design hierarchy. With an accurate estimation of lower
level design features, such as chip area and signal delay, it can very effectively determining the types and
quantities of modules to be included in the chip design. Many tools have also been developed for logic synthesis
and optimization, and have been customized for particular design needs, especially for area minimization, low
power, high speed, or their weighted combination.

Layout Tools
The tools for circuit optimization are concerned with transistor sizing for minimization of delays and with
process variations, noise, and reliability hazards. The layout CAD tools include floor planning, place-and-route
and module generation. Sophisticated layout tools are goal driven and include some degree of optimization
functions. For example, timing-driven layout tools are intended to produce layouts which meet timing
specifications.

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Simulation and Verification Tools

The simulation category, which is the most mature area of VLSI CAD, includes many tools ranging from circuit-
level simulation (SPICE or its derivatives, such as HSPICE), timing level simulation, logic level simulation, and
behavioral simulation. Many other simulation tools have also been developed for device-level simulation and
process simulation for technology development. The aim of all simulation CAD tools is to determine if the
designed circuit meets the required specifications, at all stages of the design process.

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