Chapter 8

Next Generation Current Sense

Interfaces for the IoT Era

Paul Walsh, Oleksandr Kaprin, Andriy Maharyta, and Mark Healy

Abstract Key differentiators in today’s MCU market are capabilities like low
power, security, and sensor interface support. An on-chip voltage ADC is no longer
enough to support sensor peripherals in the IoT era. Flexible sensor interfaces
provide the opportunity for higher system level integration with a small form factor
at lower cost.
This paper provides an overview of current sensing interfaces for multi-sense
applications. A versatile ratio-metric current sensing front end that supports capac-
itance, resistance, photoelectric, and pyroelectric sensing is presented. In the
capacitive sensing configuration, it can achieve 17.5-ENOB for a wide capacitance
range up to 200 pF. The converter consists of an incremental zoom ADC that is
front-end configurable to support multi-sense operation.

1 Introduction

The Internet of things (IoT) offers an environment where devices provide “smart”
interfaces that can sense the world around them and coordinate a response without
human interaction [1]. An example of an IoT connected device is shown in Fig. 8.1.
The “intelligent” edge device is a PSoC™ (Programmable System On-a Chip)
microcontroller which connects to a variety of sensors and is capable of relaying
information securely to a cloud device for further data analytics.
To serve the uncoordinated and exponential growth of the IoT a flexible sensor
interface becomes critical for highly integrated low-cost solutions. This flexibility
needs to be in the form of multi-sensing capability (e.g. touch, temperature,

P. Walsh () · M. Healy

Cypress Semiconductor, Cork, Ireland
e-mail: paul.walsh@infineon.com
O. Kaprin · A. Maharyta
Cypress Semiconductor, Lviv, Ukraine

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 115
P. Harpe et al. (eds.), Analog Circuits for Machine Learning,
Current/Voltage/Temperature Sensors, and High-speed Communication,
https://doi.org/10.1007/978-3-030-91741-8_8
116 P. Walsh et al.

LIGHT INTENSITY LIGHT INTENSITY

(PHOTORESISTOR) (PHOTODIODE) APPS

TOUCH/
PROXIMITY

DATA ANALYTICS
TEMPERATURE

FORCE PSoC ® IoT Device Cloud

WiFi SECURITY SECURITY

MACHINE LEARNING
PRESSURE

PYROELECTRIC ELECTET
(MOTION) MICROPHONE
(SOUND)

Fig. 8.1 Example microcontroller sensor interface in the IoT

pressure, and proximity) and dynamic configurability to optimize sampling speed,

resolution, and power.
In the current chapter we examine the requirements of current sensing front
ends in the IoT and present a flexible interface that supports current, capacitance,
inductive, and resistive sensing.

2 Sensing Interfaces for IoT

2.1 Current Sensing

Examples of current sensors can be found in Fig. 8.2. A photodiode can measure
both light intensity (Fig. 8.2a) and optical proximity (Fig. 8.2b). Optical proximity
detection uses an infrared (IR) LED to drive a signal onto the object being detected.
The magnitude of the reflected signal determines the proximity of the object.
Ambient light can be 100 times greater than the reflected signal, so the front
end needs a large dynamic range. Figure 8.2c shows an example schematic of
a photodiode sensing system. The output current is fed into a transimpedance
amplifier (TIA) converted to a voltage and processed by a voltage mode ADC.
A pyroelectric infrared (PIR) sensor detects infrared radiation. Certain wave-
lengths are sensitive to the human body (6–14 μm) and can be used to sense motion
(Fig. 8.2d). A PIR sensor schematic with its signal conditioning circuitry is found in
Fig. 8.2e. A 100 k resistor converts the sensor output current to a voltage which is
filtered, amplified, and then converted by an ADC. The signal transfers from charge
to current to voltage before conversion by the ADC.
8 Next Generation Current Sense Interfaces for the IoT Era 117

Reflecve Surface

Rf

100x - Ph1
Rλ ADC Dout
+

I→V→D
Photodiode IR LED
Photodiode Photodiode

(a) Light intensity monitor (b) Proximity Sensor (c) Photodetector operaon with an ADC

VDD

IR radiaon
Warm Body VS
IR radiaon Gain ADC Dout
BPF
Rs

Q →I→V→D
PIR Detector PIR DETECTOR

(e) PIR sensing with an ADC

(d) PIR sensor performing moon detecon of a warm body

Fig. 8.2 Current sensing. (a) Light intensity; (b) optical proximity; (c) photodiode sensing
circuitry; (d) motion sensing; (e) PIR sensing circuit

2.2 Capacitive Sensing

Capacitive sensing is commonly used in human-machine interfaces (HMI). It is of

lower power than alternative human-interfaces like voice [2] and robust for HMI
applications such as buttons, sliders, and touch screens. Figure 8.3a shows a self-
capacitance button where one terminal of the capacitor is sensed. Figure 8.3b shows
a mutual capacitive touchscreen where both terminals of the capacitance are sensed
by driving a transmit signal onto one and receiving it on the other.
Other capacitive sense applications include non-contact liquid level sensing
(Fig. 8.3c) as well as interfaces to MEMS based sensors that use capacitive sensing
to sense quantities such as pressure [3], humidity [4], and sound [5].
Capacitive proximity sensing can also be used in IoT radios for specific
absorption rate (SAR) detection. The SAR standard defines how much RF radiation
can be absorbed by human tissue. The FCC specifies 1.6 W/kg [6]. Phone vendors
set requirements to detect human proximity to the antenna (e.g. 15 mm from an
antenna in 1 mm displacements). A phone’s antenna can be small (<100 mm2 ) with
up to 200 pF of filter capacitance to decouple it from the capacitive front end. SAR
requires detection of signals as low as 1 fF out of 200 pF necessitating a 23-bit
conversion.
A typical capacitive sensing front end is shown in Fig. 8.3e. The capacitor is
switched to behave like a switched capacitor (SC) resistor. The current from this SC
resistor is converted to a voltage by an active integrator and digitized by an ADC.
118 P. Walsh et al.

TX1

TX2 CM

TX3

RX1 RX2 RX3 RX4

CS CS
CF CM
TX RX
GND SENSOR GND

(a) Self-Cap. Buon (b) Mutual Cap. Touchscreen (c) Liquid Level

TOV TOV TOV

20mm
Ph0

Ph1

15mm Ph2
Rst Rst

10mm CINT VS
2mm

Ph1
50mm VS Ph2
-
5mm ADC Dout<15:0>

SCR =
CSE NS E Ph0 VR EF +

0mm ANTENNA C→I→V→D

CS 200pF

(d) Specific Absorpon Rate (e) Capacitance-digital Converter

(Capacive Proximity)

Fig. 8.3 Capacitive touch sensing. (a) Self-capacitance button; (b) mutual capacitance touch
screen; (c) liquid level; (d) specific absorption rate; (e) capacitance-digital convertor (CDC)
example

2.3 Inductive Sensing

While capacitive sensing relies on detecting a change in an electric field, inductive

sensing [7] detects a change in magnetic field. When an AC signal is applied to a coil
a magnetic field is generated. When metal comes in contact with the field it induces
eddy currents in the coil which oppose the magnetic field and can be detected as a
change in coil inductance.
Figure 8.4a shows the metal proximity detection. Figure 8.4b illustrates inductive
linear encoding where either the sensor or target is shaped to detect position
changes. Figure 8.4c is a metal over touch button use case. When force is applied
to the metal it deflects and the displacement is detected by the inductive sensor.
8 Next Generation Current Sense Interfaces for the IoT Era 119

Metal Target

LINEAR
Planar spiral coil DISPLACEMEN SENSOR
T ADOPTS
TRIANGULAR
SHAPE
PCB INSTEAD OF
TARGET

(a) Inducve Metal Proximity Sensing (b) Inducve Linear Encoders under Metal

Metal Overlay
Rf

Sensor MIXER
Spacer
-
+
L OSC ADC Dout
PCB + -

Force Rf
Metal Overlay
Spacer L→ F→V→D C
PCB
Sensor

(c) Metal Over Touch Inducve sensor (d) Inductance-Digital-Conversion

Fig. 8.4 Inductive sensing with: (a) metal proximity; (b) linear encoder; (c) metal over touch
button; (d) inductance-digital-conversion

Displacements as low as 6 nm-rms are possible at 0.5 mm stand-off from a 5 mm

diameter coil [8]. A typical inductive sense circuit is shown in Fig. 8.4d where the
inductive sensor forms an LC oscillator, the output of which is demodulated and
processed by an ADC.

2.4 Resistive Sensing

The ability to accurately measure resistance is important. Common resistive sensing

applications include resistive touch screens, resistive temperature sensing, and
circuit calibration.
A temperature measurement circuit is shown in Fig. 8.5a where an external
resistor forms a resistive divider with a thermistor to create a voltage that is fed
to an ADC. Downsides to this approach are that the measurement is single ended,
ADC dynamic range is lost by having a resistor divider and static current is wasted
in the bridge. For example, a thermistor with a 4–25 k using a Rref = 10 k
from a 1.8 V supply requires an ADC input range of 0.5 V to 1.3 V and consumes
120 P. Walsh et al.

VDD VDD

Rref Rref Rsens

VR VRP
ADC Dout<9:0>
VRN ADC Dout<9:0>

Rsens Rsens Rref

T→R → V→D T→R → V→D

(a) (b)

Fig. 8.5 Resistive sensing with: (a) single ended resistive bridge; (b) differential resistive bridge

128 μA in the bridge. An improved approach in Fig. 8.5b uses a resistive bridge
which is both differential and ratio-metric. While it provides high common mode
noise rejection the resistive bridge still burns static current.
Dynamic bridges in [9] coupled with an ultra-low power asynchronous 10-bit
SAR ADC [10] have demonstrated power as low as 174 pW at 1 S/s with an rms
resolution of 0.61 ◦ C. It was shown that the energy consumed during resistive bridge
duty cycling was proportional to the bridge parasitic capacitance and not on the
resistance of the bridge.

3 Multi-sense Interfaces

Table 8.1 shows the examples of current sensing applications highlighting the
dynamic range and resolution required by each. Capacitive sensing applications
have a dynamic range from 10 pF to 500 pF with resolution requirements from
10 to 23-bits [11–13]. Direct current sensing applications (PIR and proximity)
detect current up to 10 μA with 10 to 12-bit ADC resolution. In resistive sensing
applications, the resistance varies from 50 to 1 M and 12-bit resolution is
required. Supporting all of these sense applications requires a versatile multi-sense
interface.
Multi-mode sensor interfaces have been growing in popularity. An interface that
supports temperature and capacitive sensing has been presented in [3] to target
MEMS pressure sensing applications. Capacitive MEMS pressure sensors have
strong temperature dependencies [14] and on-chip temperature compensation is
used to improve accuracy and robustness. Sanjurjo [14] achieves 15-bit performance
with a capacitance range up to 10.8 pF while only consuming 570 nW of power.
An interface has been demonstrated in [15] that supports temperature, capac-
itance, and voltage sensing. It uses a shared zoom ADC based on a SAR and
incremental  achieving 18.7 ENOB for input capacitances of up to 3.8 pF
consuming just over 8 μWs of power.
8 Next Generation Current Sense Interfaces for the IoT Era 121

Table 8.1 Range/resolution requirements for different current sense applications

Application Method Range Resolution
Humidity sensing Capacitive 180 pF ± 50 pF 12-bit
Proximity sensing Capacitive <500 pF 10–16-bit
Proximity sensing Current 5 nA–10 uA 12-bit
Specific absorption rate Capacitive 200 pF 23-bit
Pressure sensing Capacitive 10 pF 17-bit
Touch screens Capacitive (mutual) <3 pF 10-bit
Buttons/sliders Capacitive (self) <50 pF 16-bit
Metal over touch button Inductive <10 μH 15-bit
Temperature sensing Resistive RTDResistive NTC 50 –2 k 1 k –1 M 12-bit
Motion sensing (PIR) Current 10 nA–1 uA 10-bit
Photodetection Resistor (photocell) 100 –1 M 12-bit

A dynamic and versatile interface is shown in [16] that supports capacitive,

temperature, and resistive sensing with state-of-the-art FoMs for each sense method.
It consists of a reconfigurable front end followed by an ultra-low power 10-bit
asynchronous voltage mode SAR ADC. All the circuits consume dynamic power, so
oversampling can be used for power scaling versus speed and resolution. It achieves
resolutions from 8.4 to 10.74 bits depending on the sense method with a capacitive
range of up to 7.85 pF consuming 256 nW. While this solution offers high energy
efficiency and supports many sense modes, it doesn’t provide the high resolution
required for precision IoT applications.
Most microcontrollers have voltage ADCs in the 10 to 12-bit range. Current is
converted to a voltage by adding a transimpedance amplifier or an integrator and
the ADC reused. Removing the intermediate voltage generation step and using
a current sensing ADC can remove components (active integrators, TIAs, and
passives) and relax the requirements on the ADC. Figure 8.6 illustrates how the
current, capacitance, inductive, and resistive sensing circuitry from Figs. 8.2, 8.3,
8.4, and 8.5 can be simplified by using a current sensing ADC (CI-ADC).

4 Choosing a Current Sensing ADC

Specific absorption rate detection using capacitive sensing is the most sensitive
use case from Table 8.1 requiring up to 200 pF capacitance and 23-bit resolution.
The signal lies within a reduced range, so offset cancellation can limit the required
resolution to ~19-bits. Let us examine ADCs that support large dynamic range and
power efficiency for capacitive sensing.
A successive approximation register (SAR) topology [17, 18] is ultra-low power
(<160 nW) but only suited to low-medium resolution (~14-bit) applications with
resolution dominated by DAC matching. To achieve high resolution, it requires a
122 P. Walsh et al.

VDD
IR P
Ph0 Rs L IL P
CI-ADC Dout<12:0>
Rλ CI-ADC Dout<15:0>
Ph1

I→D L→I→D

(b) Inductive sensing with a current input ADC (CI-

(a) Current sensing with a current input ADC (CI-ADC) ADC)
VDD

Ph0
Rref
Ph1
VS IR P Ph0, Ph1
CI-ADC Dout<15:0> Ph1
CSE NS E VDD
SCR =
Ph0
IR P
Ph0
CI-ADC Dout<9:0>
IR N
C→I→D
Ph1 Rsens

R→I→D
(c) Self Capacitance sensing with an ADC (d) Photodetector operaon with a current input ADC (C-ADC)

Fig. 8.6 Multi-sense interface with current ADC (C-ADC); (a) resistance sensing; (b) PIR
sensing; (c) capacitance sensing; (d) photodiode sensing

low noise comparator [19] or active charge transfer OTA [17] but degrades power
efficiency. State of the art for a Zoom SAR is 14-bit resolution (0.29 fF step size)
with 16 fJ/conversion step energy efficiency [20] but the dynamic range is only 5 pF.
To enhance the dynamic range and resolution an incremental ADC is examined
in [21]. It achieves 13-bit resolution through oversampling and noise shaping. The
high oversampling ratio (OSR) leads to long conversion cycles and penalizes power
efficiency.
Two-step incremental ADCs have been examined for high resolution and energy
efficiency, [15, 22]. The zoom capacitance-digital converter (C-D-C) in [22]
achieves 15.4-bit resolution with only one time charging of the capacitance but its
energy efficiency is still limited by the presence of OTAs. An incremental zoom-
ADC in [23] achieves 20-bit resolution although power consumption suffers because
of use of an inverter based integrator.
Two-step ADCs consisting of either incremental  ADCs or a combination of
incremental  + SAR can achieve high resolution with high power efficiency.

4.1 Two-Step ADCs

A high-level description of a two-step ADC is shown in Fig. 8.7. The first stage is
a low resolution ADC that performs a coarse conversion (M) on an input (X). A
DAC removes the coarse result (M) from X and passes the quantization noise of the
coarse converter (QCOARSE ) to the second stage. The DAC provides the references
for the second stage to relax the dynamic range and resolution of the fine ADC.
8 Next Generation Current Sense Interfaces for the IoT Era 123

Two-step ADC block diagram Two-step ADC Operaon

Coarse Fine
ADC (M) ADC (N)
Coarse M = X+QCOARSE
I1000
ADC I1111
11 11
I1100 I0111
DAC
+ Y= M+N
I1000
10
I0110
10
Y = X + QFINE
- -QCOARSE
Fine
X 01 QCOARSE 01
X
+ ADC
N = -QCOARSE + QFINE
I0100
00
I0101
00
I0000 I0100
M=<01> N=<01>

Result = <0101>

Fig. 8.7 Block diagram and operation of a two-step ADC

Offset Incremental Fine

(P-1).QFINE
Cancellaon ADC
1111
X
DAC DAC 1st order ΔΣ 1100

- -P.C
- - 1 Offset
1000
Result = <0101>
X + + + Z-1
Y = P.X + QFINE -P.C
0100

0000

Fig. 8.8 Block diagram and operation of an offset cancelling incremental  ADC

A  can be used as the fine converter in a two-step ADC where the residue from
the first stage is passed to the second stage for conversion. The linearity of the coarse
ADC must meet the linearity demands of the overall ADC which is dominated by
component matching. A one-bit quantizer is inherently linear and is suitable for the
fine  ADC. Replacing the coarse converter with an offset cancelling input stage
relaxes matching constraints. An offset cancelling incremental  is illustrated in
Fig. 8.8. The first conversion stage removes the offset and adjusts the references
to the second stage for fine conversion. The ADC then performs P incremental
conversions of the input after offset removal. A two-step ADC with both coarse
ADC and offset cancellation provides the most flexibility. The DAC of the coarse
ADC can be reused for offset removal.

4.2 Current Mode Incremental ADC (CI-ADC)

A first-order incremental  is composed an integrator, a DAC, and a comparator

(Fig. 8.9(a)).
During a sub-conversion the input current (IIN ) is sampled onto the integrator
(during Ph1) and converted to a voltage (VINT ). The comparator outputs a logic
high if VINT is below the reference, in which case it pulls CREF low to remove
charge from the integrator, and this process is called “balancing.” The residue from
124 P. Walsh et al.

VDD VDD VDD VDD

CR EF Ph1 Ph0 CR EF Ph0
Ph1
Ph0 Ph1 Ph1
Ph0

CINT

Fb Fb
IIN Logic IIN Logic
- VINT + Ph0 +
Ph1
Sinc Filter + Sinc Filter +
+ DFF Dout DFF Dout
- Decimator - Decimator
Fmod Fmod

(a) (b)

Fig. 8.9 Block diagram of a current input first-order incremental  (CI-ADC); (a) with active
integrator; (b) with passive integrator

each balancing phase is stored on CINT for the next sub-conversion. A conversion
is composed of N sub-conversions. The comparator bitstream is passed to a SINC
filter and decimator to get the conversion result, Dout.
To reduce power the active integrator can be replaced by a passive integrator (a
capacitor in Fig. 8.9b) at the expense of linearity. Linearity can be improved by
increasing the order of the modulator or adding dither. A disadvantage of the single
ended CI-ADC in Fig. 8.9b is that VDD noise can be rectified onto the integrator.
Addition of a second integrator, as shown in Fig. 8.11, ensures VDD noise becomes
common mode and cancels at the comparator input.

5 Incremental  Design Considerations

This section touches on design considerations when building a two-step incremental

ADC. First the choice of coarse and fine ADC resolution is addressed, and then
noise and linearity considerations are considered before reviewing decimation filter
design.

5.1 Choosing Both Coarse and Fine ADC Order

The signal-to-quantization-noise ratio (SQNR) of a  depends on order of the

modulator (O), the resolution of the quantizer, and the over sampling ratio (OSR) of
the conversion. A 1-bit quantizer is a good choice because of its inherent linearity.
Figure 8.10 shows the ideal SQNR of a 1-bit  versus the OSR for different
modulator orders. The trend shows that the OSR required to hit a target SQNR can
be increased with the modulator order but at the expense of modulator dynamic
range [23]. Addition of Coarse Quantizer (M) shows the improvement offered by a
two-step architecture.
8 Next Generation Current Sense Interfaces for the IoT Era 125

Fig. 8.10 Delta sigma SNR versus over sampling ratio (OSR), O = filter order, M = coarse ADC
resolution for a 1-bit quantizer [24]

Rejected by Filtered by Filtered by

Baseline HP Chopping Decimator
Filter 1/f Noise
Thermal Noise
Quantization noise CDAC
Total Noise
Ph1
IINP +
+
Ph0 Dout
1/f Corner
-
PSD(f) IINN -

+20db/dec Chop
Dither

CINT2

f
frequency

(a) (b)

Fig. 8.11 (a) Power spectral density (PSD) profile of the ADC; (b) first-order differential 
with passive integrators, comparator chopping, and dither DAC

5.2 Understanding Noise

The power spectral density (PSD) profile of a first-order  converter is illustrated

in Fig. 8.11a. There are three main noise elements: 1/f noise, thermal noise, and
quantization noise. The 1/f noise comes from active devices in the modulator (e.g.,
comparator), thermal noise from both passive and active devices, and quantization
noise from the architecture.
The presence of a microcontroller means firmware filtering can be used to reduce
low frequency 1/f noise. A baseline firmware filter can be used to track slow changes
in the ADC output over time and act as a high pass filter with a low (<1 Hz) cut-off.
In capacitance sensing applications, for example, where the signal is 10–120 Hz,
baseline filtering is effective. 1/f noise can be suppressed in hardware by system
level chopping at the comparator (Fig. 8.11b). Thermal noise is white and gets
averaged by the number of conversion cycles.
126 P. Walsh et al.

Non-Linearity - 1st order , Cs sweep: 0-35pF Non-Linearity - 1st order , Cs sweep: 0-35pF
(Without Dither) (With Dither)

100fF
Non-Linearity Magnitude (fF)

Non-Linearity Magnitude (fF)

< 3fF

Cs Sweep: Percentage of Cs (%) Cs Sweep: Percentage of Cs (%)

(a) (b)

Fig. 8.12 Nonlinearity of first-order  (a) without dither; (b) with dither

A first-order  pushes quantization noise to high frequency where it rises at

+20 dB per decade. This can be suppressed by a decimation filter. For best results,
the decimation filter should be at least one order of magnitude larger than the
converter order. A second-order decimation filter will have a −40 dB/decade roll-off
filtering quantization noise from the first-order modulator.

5.3 Incremental ΔΣ Linearity with Passive Integrators

Integrators introduce nonlinearity in a  converter. For example, the nonlinearity

of a first-order  converter with passive integrators and a SINC2 filter is illustrated
in Fig. 8.12a. The input capacitance is swept from 0.1 pF to 35 pF. In the absence
of dithering the nonlinearity, also known as “flat spots,” is as large as 100 fF, giving
only 8.5-bit linearity, which is insufficient for precision applications. Figure 8.12b
shows the same converter with dithering applied to reduce the nonlinearity. The flat
spots are reduced to levels close to the quantization noise floor level of the converter
(<3 fF), improving linearity to 13.5-bits in this example.

5.4 Capacitor Sizing

The CINT capacitors act as both input sampling capacitors and integrators, and their
size determines the converter noise and linearity. By using off chip capacitors a large
range of input current can be supported and CINT can be suitably scaled for each
application. A large CINT capacitor (e.g., 30 nF) means the integrator approaches
an ideal integrator and linearity improves. This is at the cost of noise performance
because the comparator input referred noise appears as noise charge on the large
8 Next Generation Current Sense Interfaces for the IoT Era 127

CINT capacitor. CINT sizing becomes a trade-off between input range, noise, and
linearity.
The size of the coarse capacitor DAC in the two-step conversion is determined by
matching requirements. The coarse ADC provides the references for the fine ADC
and must match the linearity requirements of the system. In [3] dynamic element
matching (DEM) is employed to achieve the target accuracy of the feedback DAC
and not degrade resolution. Data weighted averaging (DWA) is used to suppress
mismatch errors. DWA is a fast DEM method with first-order noise shaping.
Where OTAs are required for high linearity, the coarse converter can relax the
output swing requirement on the integrator OTA [23], making the use of inverter
based OTAs possible for subsequent stages of higher order modulators.

5.5 Decimation Filter

A decimation filter is a low pass filter and down sampler that filters the output
bitstream from a  modulator. A SINC filter is an ideal low pass filter that is
commonly used for decimation. An economical implementation of a SINC filter is a
CIC filter because it contains adders and subtractors and no multipliers. Equation [1]
shows the CIC filter transfer function, where N is the decimation (down-sampling)
rate and L is the order of the CIC filter.
   L  2
1 1 − z−N 1 1 − z−N
I C2 T F = ·   = 2·  2 (8.1)
N 1 − z−1 N 1 − z−1

Next, we can calculate the CIC filter resolution. For a CIC filter the resolution is
defined by equation [9]:

CI C2 Output Resolution = N L = N 2 (8.2)

The number of samples from a CIC filter is dependent on the scan time (2M ) and
decimation rate (N), as per equation [2]:

2M
CI C2 Samples = (8.3)
N
The filter has notches at fs/N, so periodic noise can be suppressed by setting the
appropriate sampling frequency (fs) and decimation ratio (N). Figure 8.13a shows a
SINC2 filter frequency response with varying N, and Fig. 8.13b shows the notches
in the transfer function for SINC, SINC2 , and SINC3 filters for N = 64.
For a CIC2 filter you need to discard the first conversion, so the number of ADC
cycles increases by a factor 2 as defined by equation [3]:
128 P. Walsh et al.

(a) SINC2 filter for different N

(b)
1
SINC1 v SINC2 v SINC3, N=64
n=2
0
n=4 SINC1
n=8 SINC2
n=16 SINC3
n=32
0.8 n=64 –10
n=128

Magnitude (dB)
n=256
Magnitude

0.6 –20

0.4 –30

0.2
–40

0 –50
103 104 105 106 107 108 500000 1e+06 1.5e+06 2e+06 2.5e+06 3e+06
Frequency (Hz) Frequency (Hz)

Fig. 8.13 (a) CIC2 decimation filter; (b) SINC2 filter frequency response

Time for 1st valid CI C2 sample = L.N = 2N (8.4)

While the CIC2 filter reduces the quantization noise floor, the linearity is still
limited by the CI-ADC as discussed in Sect. 5.3.

6 Multi-Sense with a CI-ADC

6.1 Current Sensing with a CI-ADC

Figure 8.14 shows a simplified block diagram of a CI-ADC connected to a

pyroelectric sensor. In this case the capacitor (CREF ) is controlled by the Ph0 and
Ph1 clocks and behaves as a current inverted SC resistor. The PIR current (IPIR ) is
integrated onto CINT1 and is cancelled by the SC resistor current (IBAL ). The ADC
Bitstream is fed to the SINC filter for the conversion result, Dout.
Figure 8.15a shows the current sensing configuration used for photodiode sensing
in light detection applications. During Ph0 the diode current is integrated onto CINT2
(Fig. 8.15b). During Ph1 the diode current is integrated onto CINT1 (Fig. 8.15c).
The SC-resistor formed by CREF develops opposite phase currents and maintains
the polarity of the current through the diode.
A photodiode transmitter and receiver are required for optical proximity sensing.
The ambient light creates a DC current (Iphoto) which is larger than the signal
current (IREFL ). Removal of this photodiode DC current can relax the dynamic range
required by the front end. Figure 8.16b shows a front-end configuration that can
remove the DC current. The Tx current and ambient light are indicated. The TX
is an IR LED in series with a switch and resistor to VDD as shown in Fig. 8.16a.
Figure 8.16c shows the configuration of the front end during each clock phase (Ph0,
Ph1, Ph2, and Ph3).
8 Next Generation Current Sense Interfaces for the IoT Era 129

SC resistor & Current Phs

Inverter
TOV
VDD
Ph1 CR EF Ph0
Ph0
VDD
Ph1
Ph1

VCINT1
IR radiation
Raw Count

IPIR IBAL <15:0>

Phs
CI-ADC Dout<15:0>

IPIR
Dout ~
PIR DETECTOR VDD·CREF·FADC

CINT1

Fig. 8.14 Pyroelectric current sensing with a CI-ADC

SC resistor & Current

VDD
Inverter VDD
CREF Ph0 Ph0

Ph1
Ph0 Ph1 Ph1 IPh1
VDD
Ambient light Photo
Ph0
IBAL_Ph0 IBAL_ph1
IPh1
Ph1
Ph0
CI-ADC Dout
Photo
Ph0
IPh0
Photo
Ph1 IPh0
CINT2
Ph1
CINT2

(a) (b) (c)

Fig. 8.15 (a) Full wave photodiode current sensing with CI-ADC; (b) Ph0 photodiode config; (c)
Ph1 photodiode config

Ambient light
Tx Photons
VDD VDD VDD

VDD Ph0 Ph1

Rref
IREFL_Ph2
Ph0|Ph1
Ph3 IBAL_Ph0 Ph2 Ph3

Ph2

Photo Photo Iphoto CI-ADC Dout Photo Photo

Transmier Receiver
Ph1
Ph0 Ph1
Photo Photo
Ph1|Ph2 Ph0
Ph2|Ph3 CINT2 CINT1
CINT2
IREFL_Ph2 Ph2 Ph3
Iphoto IBAL_Ph0
Dout ~
VDD·CFINE ·FADC

(a) (b) (c)

Fig. 8.16 Photodiode proximity sensing; (a) transmit; (b) receive with first-order CI-ADC; (c)
proximity sensing configurations during each clock phase

Operation is as follows:
• The TX in Fig. 8.16a is only switched during Ph1 and Ph2, so the reflected light
consisting of Tx photons is only available during Ph1 and Ph2.
• During Ph0 the ambient light current (Iphoto) is sampled onto CINT2 .
• During Ph2 both the ambient and reflected light is sampled onto CINT2 in opposite
polarity, cancelling the ambient light and leaving the Tx reflected light signal.
130 P. Walsh et al.

VDD
IINP IINP
VDD Ph0
IR P Ph0 IR P Ph1
CM
Ph0
CI-ADC CI-ADC Dout
Ph1
IR N Ph1 IR N Ph3
CS Ph2
IINN IINN
CM CINT2 CINT2
Dout ~
CFINE CS
Dout ~
CFINE

(a) (b)

Fig. 8.17 (a) Mutual-capacitive sensing with a first-order CI-ADC; (b) self-capacitive sensing
with a first-order CI-ADC

• During Ph1 the ambient light current (Iphoto) is sampled onto CINT1 .
• During Ph3 both the ambient and reflected light are sampled onto CINT1 in
opposite polarity, cancelling the ambient light and leaving the Tx reflected light
signal.

6.2 Capacitive Sensing with a CI-ADC

The circuit of Fig. 8.17a can modulate and demodulate a mutual capacitance.
Operation is as follows:
• During Ph0 the capacitor is charged to VDD and current INP, INN is integrated
onto CINT1/ CINT2 and then processed by the CI-ADC.
• During Ph1 the CM capacitor is then pulled to ground and current INN is
integrated onto CINT2 for conversion by the CI-ADC.
The ADC Bitstream is fed to a SINC filter for the conversion result, Dout.
Self-capacitance sensing with a first-order CI-ADC is shown in Fig. 8.17b. The
charge and integration phase of the capacitor CS is split over four clock cycles.
Operation is as follows:
• Ph0 phase is used to pull-up Cs.
• Ph1 transfers the positive current onto the integrator for conversion.
• Ph2 phase is used to pull-down Cs.
• Ph3 transfers the negative current onto the integrator for conversion.
For both capacitive sensing methods the output is ratio metric and proportional
to the CREF capacitor.
8 Next Generation Current Sense Interfaces for the IoT Era 131

Sensor Coil
VDD
ILSENS Sensor Coil
Ph0 Rs L VDD
CI-ADC Dout<15:0> ILSENS
Ph1a|Ph1b Ph0|Ph1b Ph0 Rs L
Ph0|Ph1b
Ph0 CINT1
CINT1
Ph1a
Inductor energy accumulaon
Ph1b

(a) (b)

Sensor Coil Sensor Coil

ILSENS
Rs L Rs L
Ph1a
CINT1 CINT1

CI-ADC current accumulaon Idle Time

(c) (d)

Fig. 8.18 Inductive sensing; (a) block diagram; (b) Ph0 energy accumulation phase; (c) CI-ADC
current accumulation phase; (d) idle time

6.3 Inductive Sensing with a CI-ADC

Inductive sensing with a CI-ADC is illustrated in Fig. 8.18a. The L and Rs represent
the inductive sensor. Three clock phases are used for the conversion (Ph0, Ph1a, and
Ph1b). Figure 8.18b shows the Ph0 phase (or energy accumulation phase) where
a current is established in the inductor. Figure 8.18c shows the Ph1a (or current
accumulation) phase where current is integrated onto the CI-ADC capacitor. Figure
8.18d shows the Ph1b (or Idle) phase where the inductor current is dissipated before
the next Ph0 phase.

6.4 Resistive Sensing with a CI-ADC

Resistive sensing with an ADC required one off-chip resistor (Fig. 8.5d). When
using a CI-ADC an external resistor can be used as a reference (Rref) (Fig. 8.19a).
The resistors are dynamically switched to save power.
The sensor resistance (Rsens) gets balanced by the converter instead of Rref.
This ensures the converter output code is now linearly proportional to Rsens, see
the transfer function in Fig. 8.20b. Rref must be greater than Rsens_max which
reduces the consumed current and the impact of switch resistance in series with the
measured resistor.
132 P. Walsh et al.

VDD

Ph0
Rref

Duty Cycle (Dx)

IBAL_Ph0
Ph1 IPh0
Ph0
IRP
Ph1
1
Dx = · Rsens
IRN
Ph0
CI-ADC Dout Rref
VDD Ph1

Ph0
Rsens Rsens_min Rsens_max
CINT2 IBAL_Ph1
Resistance
Ph1 IPh1
(Rsens+Rsw)
Dout ~ Rref > Rsens_max
(Rref+Rsw)

(a) (b)

Fig. 8.19 (a) Ratio metric resistance sensing with a CI-ADC using an external reference resistor
(Rref); (b) duty cycle vs resistance curve

7 Measurement Results

A prototype CI-ADC was built using a PSoC™ microcontroller.

7.1 Optical Proximity Results

The prototype was used for optical proximity sensing. It was programmed for a
resolution of 16.5 bits and a refresh rate of 61 Hz. Results in Fig. 8.20 show
SNR > 15 for an object at 100 mm. The background light suppression ratio was
>70 dB.

7.2 Capacitance Sensing Results

The prototype CI-ADC was used to sense capacitance proximity for specific
absorption rate detection in cellphones. The signal from a 100 mm2 antenna can
be found in Fig. 8.21a. Above 15 mm distance the signal is <1 fF.
The antenna was loaded with a 200 pF capacitance and a metal object moved
away from it in 1 mm steps up to a distance of 15 mm. The filtered and unfiltered
raw counts from the CI-ADC are shown in Fig. 8.21b.
8 Next Generation Current Sense Interfaces for the IoT Era 133

Proxi Object @100mm rawData0

rawData1
1350 rawData2
rawData3
1330 rawData4
rawData5
rawData6
1310 rawData7
rawData8
rawData9
1290
rawData10
rawData11
1270 rawData12
rawData13
rawData14
1250

1230

1210

1190

1170

1150

1130

1110

1090

1070
No Object Linear
1050
Log10

1030 cnts
0 80 160 240 320 400 480 560 640 720 800 880 960 1040 1120 1200 1280

Fig. 8.20 Optical proximity sensing with the prototype giving SNR >15:1
Capacitance signal from 100mm 2 antenna at 1mm step changes up to 20mm Raw Count signal from 100mm 2 antenna at 1mm step changes up to 15mm with 200pF load capacitance.

3
10 Unfiltered Raw Count 1 mm
Filtered Raw Count

2
10

2 mm
dCs Step, f F

1
10

3 mm

0 4 mm
10
5 mm

6 mm
7 mm
-1 8 mm
10 9 mm
10 mm
0 5 10 15 20 11 mm
Distance, mm 14 mm 13 mm 12 mm
15 mm

(a) (b)

Fig. 8.21 SAR application. (a) Capacitance signal with 100 mm2 antenna versus proximity
distance; (b) raw count signal over proximity distance

7.3 Inductive Sensing Results

The prototype inductive force sensor is shown in Fig. 8.22. The raw count is plotted
versus distance of the metal target from a 20 mm coil. A resolution of <20 nm is
seen. Nonlinearities can be seen in the transfer function as outlined in Sect. 5.3 but
these can be handled by setting appropriate thresholds in the MCU firmware as the
converter has lots of measurement resolution.

7.4 Resistance Sensing

Figure 8.23a shows a resistance sweep at room temperature for the resistance
sensing configuration in Fig. 8.19. The resistance is swept from 1 K to 16 K
and shows an absolute tolerance between −150 and 300 (or −0.9% to 1.9%).
134 P. Walsh et al.

Fig. 8.22 Inductive sensing prototype with 15 mm and 20 mm coils. Raw count versus coil
distance is plotted

Absolute Resistance Measurement Absolute Resistance Delta

18000 350

16000 300

250
Measured Resistance, Ohm

14000
200
12000
150
10000
ΔR, Ohm

100
8000 Measured ΔR
50
Ideal Linear (ΔR)
6000
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
4000 -50

2000 -100

0 -150
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-200
Sense Resistance, kOhm Sense Resistance, kOhm

Fig. 8.23 (a) Actual resistance versus sensed resistance; (b) resistance delta

8 Conclusions

A dynamic, scalable, current input ADC provides the flexibility to address the
existing needs of IoT applications, as well as solve the problems that we haven’t
thought of, or encountered, yet. Broad market microcontrollers need versatile
multi-sense interfaces. Use of a CI-ADC can remove the need for intermediate
voltage generation stages such as active integrators and TIAs used in traditional
microcontrollers to convert sensor signals to voltages before ADC conversion. Two-
step incremental ADCs can achieve high-power efficiency and high resolution.
Use of dynamic switching in the front end has demonstrated the capability to
support current, capacitance, inductance, and resistance sensing with a single ADC.
Replacing active integrators with passive off-chip components can provide a low
power, scalable front end.
8 Next Generation Current Sense Interfaces for the IoT Era 135

While the trend in MCUs is toward versatile broad market sense solutions they
don’t mitigate the need for bespoke solutions. For example, in [25] a state-of-the-
art capacitance-digital-converter demonstrates wake on touch sensing consuming
only 15 nW of power per touch sensor. Combining both flexible and bespoke sense
solutions that operate independent of the MCU offers the best trade-offs for future
IoT solutions.

References

1. S. Vashi et al, Internet of things: A vision, architectural elements and security issues, in
Proceedings of the international conference on I-SMAC, IEEE, (2017), pp. 492–496
2. J. Chen, X. Ran, Deep learning with edge computing: A review, in Proceedings of the IEEE
(2019)
3. T.-T. Zhang, Nano-watt energy-efficient capacitive sensor interface with on-chip temperature
drift compensation. IEEE Sensors J. 18(1), 2870–2882 (2018)
4. Z. Tan et al., A 1.2V 8.3nJ energy-efficient CMOS humidity sensor for RFID applications.
IEEE JSSC 48(3), 2469–2477 (2013)
5. L. Crespi et al, Low power microphone front-ends, in Low power analog techniques, sensors
for mobile devices and energy efficient amplifiers, Advances in Analog Circuit Design (AACD)
(Springer, 2018), pp. 353–380
6. https://www.fcc.gov/general/specific-absorption-rate-sar-cellular-telephones
7. Cypress Semiconductor. https://www.cypress.com/products/32-bit-arm-cortex-m0-psoc-4700-
mcus
8. M. Pimenta et al, A 200μW interface for high-resolution eddy-current displacement sensors,
IEEE JSSC, 56(4) (2021)
9. H. Xin et al., A 174pW-488.3nW 1S/s-100Ks/s all-dynamic resistive temperature sensor with
speed/resolution/resistance adaptability. IEEE Solid State Circuit Letters 1(3), 70–73 (2018)
10. P. Harpe et al., A 0.2 mm2 3 nW signal acquisition IC for miniature sensor nodes in 65 nm
CMOS. IEEE J. Solid State CCS 51(1), 240–248 (2016)
11. Smartec Capacitive Humidity Sensor HS08A datasheet
12. Cypress Semiconductor, Proximity Sensing with CapSense, Application Note AN92239
13. H. Klein et al, Advanced capacitive sensing for mobile devices, in Low power analog
techniques, sensors for mobile devices and energy efficient amplifiers, Advances in Analog
Circuit Design (AACD) (Springer, 2018), pp. 131–154
14. J.P. Sanjurjo, An Energy Efficient 17-Bit Noise-Shaping Dual-Slope Capacitance-to-Digital
Converter for MEMS Sensors, (ESSCIRC 2016), pp. 389–392
15. B. Yousefzadeh et al, A compact sensor readout circuit with combined temperature, capac-
itance and voltage sensing functionality, in IEEE symposium on VLSI circuits (2017), pp.
C78–C79
16. H. Xin et al, A 0.34-517nW all-dynamic versatile sensor interface for simultaneous tempera-
ture, capacitance and resistance sensing, in IEEE ESSCIRC (2019)
17. H. Ha et al, A 160 nW 63.9 fJ/conversion-step capacitance-to-digital converter for ultra-low-
power wireless sensor nodes, in ISSCC (2014), pp. 220–221
18. M.M. Ghanbari et al., An energy-efficient miniaturized intracranial pressure monitoring
system. IEEE, JSSC 51(3), 720–734 (2017)
19. H. Omran et al, A 35 fJ/step differential successive approximation capacitive sensor readout
circuit with quasi-dynamic operation, IEE Symp. VLSI Circuits (2016), pp. 1–2
20. X. Tang et al, A 16 fJ/conversion-step time-domain two-step capacitance-to-digital converter,
in ISSCC (2019), pp. 296–298
136 P. Walsh et al.

21. B. Li et al., A high-linearity capacitance-to-digital converter suppressing charge errors from

bottom plate switches. IEEE Trans. Circuits Systems 61(7), 1928–1941 (2014)
22. S. Oh et al, 15.4b incremental Sigma-Delta capacitance-to-digital converter with zoom-in 9b
asynchronous SAR, in IEE Symp. VLSI Circuits (2014), pp. 1–2
23. Y. Chae et al., A 6.3 uW 20 bit incremental zoom-ADC with 6 ppm INL and 1 μV offset. IEEE
JSSC 48(12), 3019–3027 (2013)
24. J.D. Reiss, Understanding Sigma-Delta Modulation: The Solved and Unsolved Issues, pp. 49–
54
25. S. Hussaini et al., A 15-nW per sensor interference-immune readout IC for capacitive touch
sensors. IEEE JSSC 54(7), 1874–1882 (2019)