Program : B.

Tech
Subject Name: Digital Systems
Subject Code: CS-304
Semester: 3rd
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Subject Name: Digital Systems Subject Code: CS303

Subject
Notes UNIT-
IV
Introduction to A/D & D/A convertors & their types, sample and hold circuits, Voltage to
Frequency & Frequency to Voltage conversion. Multivibrators :Bistable, Monostable,
Astable, Schmitt trigger, IC 555 & Its applications. TTL, PMOS, CMOS and NMOS logic.
Interfacing between TTL to MOS.

ANALOG TO DIGITAL CONVERTER (ADC):

Figure 4.1 shows the general block diagram of ADC. An ADC takes an analog input voltage
and after a certain amount of time produces a digital output code that represents the analog
input.
Analog Timing for operation is provided by
Input Start the input clock signal.
CNTL Control (CNTL) unit contains the
VA Clock
UNIT logic circuitry for generating the
Comparator proper sequence of operations in
End of
conversion response to the start command,
which initiates the conversion
D/A Regist process.
VAX Conve er OPAMP comparator has two analog
rter inputs and a digital output that
switches states, depending upon
which analog input is greater.
Digital result
Figure 4.1: General block diagram of
ADC START command pulse initiates the operation. At a rate determined by the clock,
Operation:
the control unit continually modifies the binary number that is stored in register. The binary
number in register is converted into analog voltage, VAX, by DAC. The comparator compares
VAX with VA. When VAX < VA, comparator output stays HIGH. When VAX > VA, by atleast an
amount equal to threshold voltage, the comparator output goes LOW and stops the process
of modifying the register number. At this point VAX is close approximation with VA.
The digital number in the register, which is the digital equivalent of VAX, is also the digital
equivalent of VA, within the resolution and accuracy of the system. The control logic activates
the end of conversion signal, when the conversion is complete.

DIGITAL RAMP ADC (COUNTER TYPE ADC):

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Figure 4.2 shows the diagram of digital ramp ADC.

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Analog
Input Clock
EOC
VA Start VA
Comparator Conversion
Reset VAX complete.
Counter
D/A Count stops
counting.
VAX Conve er
rter EOC
(DAC)
Time
Digital result Start
Figure 4.2: Digital Ramp ADC

Operation: Assume that VA is positive. START pulse is applied to RESET the counter to 0 and
AND gate is disabled. With all 0s as its input, DAC output will be VAX = 0v. Since VAX < VA,
comparator output, (EOC)’, is HIGH. When START is LOW, AND gate is enabled and clock
pulses get through to the counter. As the counter advances, DAC output, VAX, increases one
step at a time. This continues until VAX > VA by an amount equal or greater than threshold
voltage (typically 10 to 100μv). At this point comparator output, (EOC)’, goes LOW and
counter stop counting. The conversion process is now complete and the contents of the
counter are the digital representation of VA. Counter will hold the digital value until the next
START pulse initiates a new conversion.
Conversion time, Tc, is the interval between the end of the START pulse and the activation of
the (EOC)’ output. Tc depends upon VA .
For N-bit converter: Tc(max) = (2N – 1) clock cycles. Tc(avg) = Tc(max) / 2 clock cycles.
Major disadvantage of digital ramp ADC is that it is not suitable for where the repetitive A/D
conversion of a fast changing analog signal occurs. In this method the conversion time
essentially doubles for each bit that is added to the counter.

SUCCESSIVE-APPROXIMATION ADC (SAC):

Analog Figure 4.3 shows the general block
Input Start diagram of SAC. Basic arrangement is
CNTL similar to digital ramp ADC except that,
VA UNIT Clock
instead of counter SAC uses a control
Comparator register. The control logic modifies the
End of
contents of the register bit by bit until
conversion
the register data are the digital
D/A Control equivalent of the analog input VA within
VAX Conve Registe the resolution of the converter.
rter r Most widely used ADC. Circuitry is more
complex but much shorter conversion
time
Digital result
Figure 4.3: General block diagram of
SAC

Operation of 4-bit SAC using DAC step size of 1Volt and VA = 10.4 Volts:

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MSB VAX
From Q4 DAC 12
CNTL Regis Q3 Step Conversion
logic ter Q2 size=1v VAX 11
completed
10
Q1
LSB 9
VA=
To CNTL logic
T0 T1 T2 T3 T4 T5 T6 Time
Figure 4.4: 4-bit SAC using step size
1V
Operation: Figure 4.4 shows the 4-bit SAC using DAC step size of 1Volt. Let assume that the
analog input is VA=10.4V.
At time T0, VAX = 0V, i.e VA > VAX, comparator output is HIGH. Control logic clearing all bits so,
Q3=Q2=Q1=Q0=0 ie [Q]= 0000.
At time T1, control logic (CNTL) sets MSB = 1. So [Q]= 1000. This produces VAX = 8V. Since, VA
> VAX, comparator output is HIGH. This HIGH tells the CNTL logic that the setting of MSB did
not make VAX exceeds VA, so that MSB is kept at 1.
Now, CNTL logic proceeds to next lower bit, Q2. Q2=1 to produce [Q] = 1100 and VAX = 12V at
time T2. Since VAX > VA, comparator output goes LOW. The value of VAX is too large, so CNTL
logic then clears register contents back to 1000 ie VAX = 8V. Thus, at T3, VAX = 8V.
At time T4, CNTL logic sets the next lower bit Q1 = 1, ie [Q] = 1010 and VAX = 10V.
With VA > VAX, comparator output is HIGH and tells the CNTL logic to keep Q1 set at 1.
Final step, time T5, CNTL logic sets the next lower bit Q0 =1 ie [Q] = 1011 and VAX = 11V.
Since VAX > VA, comparator goes LOW to signal that VAX is too large, and the CNTL logic clears
back Q0 to 0 at time T6.
At this point, all of the register bits have been processed, the conversion is complete and the
CNTL logic activates (EOC)’ output to signal that is digital equivalent of VA is now in the
register. So, digital output for VA = 10.4V is [Q] = 1010.
Conversion time,Tc, for SAC: The control logic goes to each register bit, set it to 1, decides
whether or not to keep it at 1, and goes on to the next bit. The processing of each bit takes
one clock cycle, so that the total conversion time for an N-bit SAC will be N-clock cycles.
Tc = N x 1 clock cycles

FLASH ADC: It is the highest speed ADC, but its circuitry requires much more than other

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types ADC. Example: 6-bit flash ADC requires 63 analog comparators; 8-bit requires 255
comparators.

3-Bit Flash Converter:

Figure 4.5 shows the 4-bit flash converter.

10V

3KΩ
C7

1KΩ 7V MSB
C6 C

1KΩ 6V
Priority
C5 Encoder
5V Digital
1KΩ B output
C4
1KΩ 4V

C3
A
3V
1KΩ
C2

1KΩ 2V

C1
1V
1KΩ
Analog
Input
VA
Figure 4.5: 4-bit Flash Converter

Operation: 3-bit flash converter has a resolution (step size) of 1V. Voltage divider set up a
reference levels for each comparator, so that there are seven levels corresponding to 1V
(weight of LSB), 2V, 3V, 4V, 5V, 6V and 7V (Full Scale). Analog input is connected to other
input of each comparator. 3-bit flash converter ADC operation table is shown below:

Analog In Comparator outputs Digital Outputs

(VA) C1 C2 C3 C4 C5 C6 C7 C B A
0V -1V 1 1 1 1 1 1 1 0 0 0
1V - 2V 0 1 1 1 1 1 1 0 0 1
2V - 3V 0 0 1 1 1 1 1 0 1 0
3 V- 4V 0 0 0 1 1 1 1 0 1 1
4V - 5V 0 0 0 0 1 1 1 1 0 0
5V - 6V 0 0 0 0 0 1 1 1 0 1
6V - 7V 0 0 0 0 0 0 1 1 1 0
>7V 0 0 0 0 0 0 0 1 1 1
TABLE of 3-bit Flash Converter ADC
With VA < 1V, all comparator output is HIGH. With VA > 1V, one or more comparators output

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will be LOW. Comparator output is feed into active low priority encoder that generates a
binary output corresponding to the highest numbered comparator output, that is LOW. For
example, if VA is between 3V – 4V, output C1, C2 and C3 will be LOW and all others are HIGH.
Priority encoder will respond only to the LOW at C3 and will produce binary output CBA =
011. Conversion Time, Tc of flash converter: Flash converter uses no clock signals.
Conversion time depends only on the propagation delays of the comparators and encoder
logic. So, flash converter has extremely short conversion times.

ADC USING VOLTAGE TO FREQUENCY CONVERTER:

Figure 4.6 shows the ADC using voltage to frequency converter.

S
Monostable
Multivibrator
C
R N-bit
Vout
Vc count Display
Vin
er
-Vref VEN

V-F Converter
Figure 4.6: ADC using V-F converter

Voltage to frequency ADC does not require DAC. Instead it uses a linear voltage controlled
oscillator (VCO), that produces an output frequency that is proportional to its input voltage.
The analog input (Vin) that is to be converted, is applied to the VCO to generate the output
frequency. This frequency is fed to the counter to be counted for a fixed time interval (VEN).
The final count is proportional to the value of the analog voltage. Circuit diagram of ADC
using V-F converter shown in figure.
Operation: The Vin is applied to an integrator whose output is applied at the inverting
terminal of a comparator. Non-inverting terminal is connected to –Vref. When switch S is
open, Voltage Vout decreases linearly with time. Thus AND gate is disabled as long as Vout <
Vref. As soon as Vout = Vref, the output Vc becomes positive, enabiling AND gate and hence
counter starts counting. When the switch S is closed, the capacitor discharges and thereby
returning the integrator output, Vout, to zero. After the delay time of multivibrator the switch
S is again open and Vout starts decreasing again and ADC repeats its function.

FREQUENCY TO VOLATGE CONVERTER (INTEGRATING TYPE):

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Block diagram of a voltage to frequency converter is shown in figure4.7 . The analog input is
applied to an integrator. The integrator produces a ramp signal whose slope is proportional
to the input voltage signal.
C

R
Comparator Counter
Input Digital Output
Voltage Integrator

Pulse
Generator
Pulse Trigger O/P
Output of Integrator, a ramp Signal
Zero Level

Trigger Level

Time between two

threshold levels
Figure 4.7: Frequency to Volatge converter

When this ramp signal reaches a preset threshold voltage level, a trigger pulse is produced.
Also a current pulse is produced which discharges the capacitor of the integrator, after which
a new ramp is initiated. The time between successive threshold level crossings is inversely
proportional to the slope of the ramp. Since the slope of the ramp is proportional to the
input analog voltage, hence the frequency of output pulses from the comparator is directly
proportional to input voltage. The output frequency can be measured with the help of digital
frequency meter.

SAMPLE AND HOLD CIRCUIT:

When an analog voltage is connected directly to the input of an ADC, the conversion process
can be affected if the analog voltage is changing during the conversion time. This stability of
conversion process can be improved by using a sample-and-hold circuit to hold the analog
voltage constant while the A/D conversion is taking place.
Digital control CNTL = 1, S closed= sample
(CNTL)input mode CNTL=0, S open+ hold
mode

Analog To ADC input

A1
S Input A2

VA
Ch

Figure4.8: Sample and Hold Circuit

Sample and hold circuit as shown in figure4.8, contains a unity gain buffer amplifier A1 that
presents a high impedance to the analog signal and low output impedance that can rapidly
charge the hold capacitor, Ch . Capacitor Ch is connected to output of A1 when digitally
controlled switch is closed. This is called sample operation. The switch is closed long enough
for Ch to charge to the current value of the analog input.
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 When switch opens, Ch will hold this voltage so that the output of A2 will apply this voltage
to the ADC. The unity gain buffer amplifier A2 presents high input impedance that will
not

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discharge the capacitor voltage during the conversion time of the ADC.
DIGITAL TO ANALOG CONVERSION (DAC):
DAC is the process of taking digital code as input and converting it to a voltage or current
that is proportional to digital value.
Vref = 15V TABLE of 4-bit DAC:
Inputs Output
MSB D C B A Vout
Digital D DAC 0 0 0 0 0
Vout
Inputs C 0 0 0 1 1
Analog
O/P 0 0 1 0 2
B 0 0 1 1 3
A LSB 0 1 0 0 4
0 1 0 1 5
Figure 4.9:Block diagram 4-bit DAC 0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15

From the block diagram as shown in figure 4.9 of 4-bit DAC ,Vref as input is used to
determine the full scale output or maximum value that DAC can produce. For each input
number, DAC output voltage is unique value. In general, Analog output (Vout) = K x Digital
Input; Where, K is proportionality constant. In above block , DAC has K=1, so that, Vout = 1 x
Digital Input.
Example: For digital input (1100)2 = (12)10 , we obtain Vout = 1 x 12 = 12V.
RESOLUTION OR STEP SIZE OF DAC: Resolution of DAC is defined as the smallest change that
can occur in the analog output as a result of a change in the digital input. Resolution is
always equal to the weight of the LSB and also referred to as step size, since it is the amount
that Vout will change as the digital input value is changed from one step to the next.
Resolution= K = AFS / (2n – 1) where, AFS is analog full scale output; n is the number of bits
% Resolution = (Step size / AFS ) x 100 OR % Resolution = (1 / Total no. of steps ) x
100

DAC USING OP-AMP SUMMING AMPLIFIER WITH BINARY WEIGHTED

RESISTOR:
Resistor R1 = 1KΩ
RF
Resistor R2 =
MSB 2KΩ Resistor R3
Digital D R1
= 4KΩ Resistor RF
input 0V C R2 = 8KΩ
or 5V B R3 Vout
A R4
LSB

Figure4.10: OP-AMP as Summing Amplifier

From the figure4.10 , opamp as summing amplifier, inputs A, B, C and D are binary inputs that

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are assumed to have a values either 0V or 5V. OP-AMP as summing amplifier, which
produces the weighted sum of the input voltages. So that, Vout = ─(VD + 1/2 VC + 1/4 VB +
1/8 VA)
So, the summing amplifier output is the analog voltage which represents a weighted sum
of the digital inputs. The resolution of this DAC using opamp as summing amplifier using
binary weighted resistor, is equal to the weighting of the LSB, which is 1 / 8 x 5 = 0.625V.

DAC USING R / 2R LADDER CIRCUIT:

In R/2R ladder circuit, the resistor values span a range of only 2 to 1.

+Vref

2R 2R 2R 2R
2R
2R

R R R Iout
Vout
B3 B2 B1 B0
(MS B) (LSB)

Figure 4.11: R/2R Ladder Circuit

In R/2R ladder network as shown in figure 4.11, only two different values are used, R and 2R.
Current Iout depends on the positions of the 4- switches and the binary inputs B3, B2, B1 and
B0, which controls the states of the switches.
Vout = (─Vref / 8) x B where “B” value of binary input from 0000 to 1111.

Example: Assume the Vref = 5V. What are the resolution and full scale output of this R/2R
converter?
Solution: Resolution is equal to weight of LSB. Suppose, [B] = 0001 = (1)10
Resolution = (-5V x 1)/ 8 = -0.625V. The full scale output occur for [B]=1111 =
(15)10 So, full scale output = (-5V x 15)/ 8 = -9.375V.
BISTABLE MULTIVIBRATOR:
If both the states of a multivibrator are stable i.e. the circuit which is in a particular state
continues to remain in that state until it is triggered from an external source to change the
state. Flip Flops are bistable multivibrator circuits as shown in figure 4.12.

Vcc
Input S
C2 C1 0
RC RC
Q’ Q
R1 R1 Vcc Output
T1 T2 of T1
-VBB R2 0
R2
Vcc
Output
S R 0 of T2
Trigger input 1 Trigger input 2

Figure4.12: Bistable Multivibrator

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Transistor T1 and T2 are npn transistors and are resistively crosscoupled with each other. Q
and Q’ are outputs. Rc is the collector resistance. C 1 and C2 are commutating capacitors, to
fast turn OFF and ON of two transistors (C1 for T2 and C2 for T1). Supply –VBB and resistor R2
are used to keep the base of the transistors at negative in one state and in other state
provides large base current to drive the transistor into saturation.
Operation: When supply is ON, say T1 is ON, so, Vc1 = 0v, the base of T2 is connected to Vc1,
so T2 is OFF. This makes Vc2 = Vcc, since base of T1 is connected to Vc2, so T1 is ON. This is the
first stable state (ie. T1=ON and T2=OFF ie. Q=1 and Q’=0).
To change the state of transistor T2, a positive pulse is applied at the base of T2. The OFF
transistor T2 will be forced to turn ON (tp > ton ie. Pulse width should be greater than turn ON
time of transistor). Thus Vc2 is forced to 0v. Since base of T1 is connected to Vc2, so T1 is OFF.
This is the second stable state (ie. T1=OFF and T2=ON ie. Q=0 and Q’=1).

MONOSTABLE MULTIVIBRATOR:
Monostable multivibrator as shown in figure 4.13 has one stable state and the other one is
not stable (quasi stable).It is also called as one-shot multivibrator. Transition from stable
state to quasi stable state is done by an external trigger pulse. After transition from stable to
quasi stable state, the multivibrator remains in the quasi stable state for a definite period of
time, decided by comoponents R and C, and then returns to the stable state automatically.

Vcc Trigger
I/P
0
RC C R RC
Q’ Q
R1 Vcc tp Output
T1 T2 of T1
-VBB 0
R2
Vcc Output
of T2
0
Trigger input
Figure4.13: Monostable Multivibrator

In this circuit the base of transistor T2 is capacitively coupled to the collector of T1, while the
base of T1 is resistively coupled to the collector of T2.

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Operation: When no trigger pulse applied, T2 is ON, a proper base drive through Vcc and R to
the base of T2. So, Vc2 = 0v. T1 is OFF, because of resistively coupled of base T1 with Vc2(Vc1 =
Vcc). At the instant when T2 is ON, capacitor C charged towards Vcc through Rc. This is the
stable state of multivibrator.
When a sufficient positive trigger pulse is applied to the base of T1, T1 is ON, so Vc1 = 0v.
Now the capacitor discharges through T1 and R. Thus discharge current through R creates a
negative potential at the base of T2. Thus T2 is OFF as long as the voltage drop across R is
negative. This condition is quasi stable state. When the capacitor fully discharges the
negative voltage at the base of T2 reduces to zero and Vcc now drives the T2 ON, so Vc2 = 0v.
So, T1=OFF and Vc1=Vcc. This is the stable state and circuit remains in the stable state until the
next trigger pulse is applied.
Time duration of quasi stable state or the pulse width: tp = 0.693(R.C)

ASTABLE MULTIVIBRATOR:
Astable multivibrator as shown in figure 4.14, has no stable states but has two quasi stable
states. The output oscillates between two quasi stable states without any external
triggering ,therefore this circuit is also called as free running multivibrator. The output at the
collector of transistors is a square wave, therefore also called as square wave generator.

Vcc

RC1 C1 R1 R2 RC2
C2
Q’ Q Vcc Output
T1 T2 of T2
0

Vcc Output
Figure4.14: Astable Multivibrator
0 of T1

Operation: Initially assume that T1 is ON and T2 is OFF due to circuit unbalance. So, Vc1 = 0v
and Vc2 = Vcc. Since T1 is ON, C2 charges towards Vcc through Rc2. Meanwhile C1 which was
charged to Vcc when T2 was ON will discharge through T1 and R1. This makes the potential at
VB2 negative and causes T2 to turn OFF. T1 is kept ON by the base current provided by Vcc
through R2. The charging current of C2 through Rc2 has reduced to zero. The time duration for
which T2 is held OFF is determined by the R1.C1. Once T2 turns ON due to the base drive from
Vcc through R1, then C1 gets charged through Rc1 and T2. At the same time C2 discharges
through T2 and R2 making VB1 negative so that T1 is turned OFF, thus Vc1 = Vcc. T1 is held OFF
by the discharging current for the time duration R2.C2. After this T1 turns ON and allow C1 to
discharge through T1 and then C2 recharges through T1.
SCHMITT TRIGGER:
In digital circuits, fast waveforms are required so that the circuit remans in the active region
for a very short time (of order of nano seconds) to eliminate the effects of noise or undesired
parasitic oscillations causing malfunction of the circuit. Also if the rise time of the input
waveform is long, it requires a large oupling capacitor. Therefore circuits which ca convert a

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slow-changing waveform (long rise time) into a fast-changing waveform (small rie time) are

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required. The circuit which performs this waveform is known as Schmitt trigger.
In a Schmitt trigger circuit, the output is in one of the two levels, LOW or HIGH. From the
figure 4.15,when the input voltage is rising, the level of the output changes when the input
passes through a specific voltage VT+ (upper triggering level). Similarly, when the input
voltage is falling, the level of the output changes when the input passes through a specific
voltage VT – (lower triggering level), the level of the output changes. VT+ (upper triggering
level) is always greater than VT – (lower triggering level). The difference of these two voltages
is known as hysteresis as shown in figure 4.16.

VT+ +Vo
+Vo(sat.)
0
Input
VT─
─Vi +Vi
+Vo
Output ─Vo(sat.)
0
─Vo LTL UTL
─Vo
Figure4.16: Hysteresis Loop
Figure4.15: Schmitt Trigger I/P & O/P Waveform

Schmitt Trigger circuits:

From the figure 4.17 of transistor
Vcc Schmitt trigger, resistor R1 and R2 are
voltage divider resistors.
RC1 RC2
R1
Vc1 Vc2
T1 T2

RE
Vi R2

Figure4.17: Transistor Schmitt Trigger

Operation: When Vi = 0V, when circuit is ON, T2 is ON (Vc2 = 0V). As T2 is ON, there is a
voltage drop across R2. This drop acts as a reverse bias across emitter-base junction of T1,
due to which T1 is OFF (Vc1 = Vcc). This Vcc is coupled to base of T2 through R1. So T2 is ON ie.
In saturation(Vc2 = VCE(sat) = 0V).
When Vi = applied AC input, and approaches till it crosses VT+ (upper triggering level). Now, Vi
> VT+ (upper triggering level), T1 conducts. So, Vc1 = 0V. This fall of voltage is coupled through
resistor R1 to the base of T2, which reduces its forward bias voltage. So, T1 = ON and T2 = OFF
ie. Vc1 = VCE(sat) and Vc2 = Vcc. The T1 continues to conduct till the input voltage falls below VT –
(lower triggering level). When Vi > VT – (lower triggering level), base-emitter junction of T1 is
reverse biased. So, T1 is OFF. So, Vc1 = Vcc and Vc2 = VCE(sat).

IC-555 TIMER:
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Figure 4.18 shows the

Control functional block
VCC Discharge Threshold Voltage
5 diagram of IC-555
8 7 6
timer. It consists of a
voltage divider
network, which
Q1 provides bias voltage
5kΩ +
Comparator-1 of (2/3)Vcc to the
– inverting input of the
(2/3)VC comparator-1 and
5kΩ R Q’
F/F (1/3)Vcc to the
(1/3)VC S
+ Q2 non-inverting input of
Comparator-2 the comparator-2.
5kΩ – These two voltages fix
Vref
the comparator
Output threshold voltage and
also determine the
1 2 3 4 timing interval.
Ground Trigger Output Reset Electronically, possible
to vary time by
Figure 4.18: Functional block diagram of IC-555 Timer applying a modulation
voltage to the control
voltage input (pin-5).
If no such modulation is proposed, a 0.01μF capacitor is connected between control voltage
and ground to bypass noise and ripple from supply. The other two inputs to the comparator
are threshold and trigger inputs. The output of these two comparators, SET or RESET the flip
flop, whose Q’output is fed to base of transistor Q1. When Q’ = high, Q1 is ON and capacitor
(externally connected between pin 7 and ground) will discharge.
The output stage is basically an inverting buffer stage used to provide a low output resistance
and also to invert the flip flop output. Output stage has a capability of sourcing and sinking
200mA current. Q2 (PNP transistor) whose emitter is connected to an internal reference
voltage which is less than Vcc. When Vref > Vcc (Pin-4 potential is less than Vcc), Q2 is ON,
which causes Q1 to turn ON and output at pin-3 is brought to ground level.
Applications include oscillator, pulse generator, ramp and square wave generator, voltage
monitor and may more applications.

IC-555 AS MONOSTABLE MULTIVIBRATOR:

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Figure 4.19 (a) shows the circuit diagram of IC-555 as monostable multivibrator and (b)
shows the waveform of trigger pulse, capacitor voltage and output pulse. Since it has only
one stable state (output low), hence name monostable.
VCC
VCC Trigger
R
8 4 0
7 VCC t

555 2/3VCC Capacitor

VC 3
6 VO Voltage (VC)
C 0 t

2 tP Output
1 5
Pulse (VO)
C 0 t
Figure 4.19(b): Waveforms
Figure 4.19(a): Monostable Multivibrator
It is also called as one-shot multivibrator. From the circuit diagram, Pin-8 is connected to Vcc
and pin-4 (reset pin) also connected to Vcc so that reset condition is disabled. The time
interval for which the output remains high (tP, pulse width) is decided by the external RC
network. The capacitor C is connected between pin 7 and 1 so that it charges through the
resistance R when the transistor Q1 is OFF.
Operation: Initially, trigger pulse is high (Vcc), this drives the output of comparator-2 to low
condition. As the capacitor C is in discharged state, pin-6 and 7 are at ground potential. The
inputs to the flip flop will be S=R=0, hence Q’ = high, so, Q1 is ON, and C discharges to 0V ie.
Vc
= 0V. Since Q’ = 1, output pin-3 = 0 is actually the stable state of multivibrator.
When the trigger input (negative trigger pulse) goes low (from Vcc to 0), comparator-2 output
= high ie. S = 1. The comparator-1 output continue to be 0 ie. R=0, hence the flip flop is in set
condition ie. Q’ = 0, pin-3 = 1(High state). Since Q’ = 0, transistor Q1 is OFF and the capacitor C
starts charging exponentially towards Vcc through the resistor R. When Vc becomes greater
than ((2/3) Vcc), comparator-1 output changes form low to high ie. R = 1. Since the trigger
input has returned back to Vcc from 0, comparator-2 output is equal to zero ie. S =0. So, S =
0 and R= 1, RS flip flop get RESET and Q’ = 1. AS Q’ = 1, transistor Q1 = ON and capacitor C
starts discharging towards zero through the transistor Q1 and capacitor voltage Vc becomes
zero. While discharging, when Vc < ((2/3) Vcc), the comparator-1 output goes to zero ie. R=0.
Since the trigger input = Vcc, the comparator-2 output will be = 0 ie. S=0. Hence, S=0 and
R=0, so no change in the Q’ output condition and hence continuous to be High. Thus, pin-3
output = LOW (0-state).
The monostable multivibrator, thus goes from stable state into quasistable state and then
returns back to the stable state after a time, tP = (1.1)R.C
The output remains to be in LOW state until the next trigger pulse is applied to change the
state.

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 IC-555 AS ASTABLE MULTIVIBRATOR:

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Figure 4.20 (a) shows the circuit diagram of IC-555 as astable multivibrator and (b) shows the
waveform of capacitor voltage and output pulse. Since no stable state, hence name astable.
VCC

RA VCC Output
8 4
Voltage
7 TON TOFF
RB 0
555 3 T t
6 VO
VCC
2/3VC Capacitor
C 2 1 5
C Voltage
1/3VCC
C t
Figure 4.20(a): Waveforms
Figure 4.20(a): Astable Multivibrator
Astable multivibrator does not requires an external trigger pluse to change the output state,
hence called as free-running multivibrator. The time duration for which the output will
remain high or low is decided by the externally connected two resistors (RA and RB) and a
capacitor (C).
Operation: Initially, when output is high (pin-3 = High), Flip flop output Q’ = 0, hence
transistor Q1 is OFF. Now the capacitor C starts charging towards Vcc through RA and RB. As
soon as the voltage across the capacitor Vc, becomes equal to[ (2/3)Vcc], the comparator-1
output is high and will RESET the flip flop ie. Q’ = 1. Hence the output = 0. As, Q’ =1 , transistor
Q1 = ON and the capacitor C starts discharging through resistor RB and transistor Q1. During
discharging mode of capacitor C, as soon as the voltage across the capacitor C becomes equal
to [(1/3)Vcc], comparator-2 output will SET the flip flop, Q’ = 0, and output = high. Then the
cycle repeats.
Charging time duration of the capacitor C, is equal to the time the output is high is given by
the expression: tC = TON = 0.69(RA + RB )C
Discharging time duration of the capacitor C, is equal to the time the output is low is given by
the expression: td = TOFF = 0.69(RB )C
Hence the total time period of output waveform: T = tC + td = TON + TOFF = 0.69(RA + 2RB )C

Hence, the frequency of oscillation is, fO = 1/T =

From the equation of frequency of oscillation fo, frequency is independent of the supply
voltage Vcc.
Duty Cycle: Duty cycle is the ratio of the time during which the output is high (TON) to the
total time period T.

% duty cycle = [TON / T] x 100 =

Applications: Astable multivibrator can be used to produce a square wave output. It can be
used as a free running ramp generator.

DIGITAL IC LOGIC FAMILIES:

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1. RTL- Resistor Transistor Logic 2.DTL-Diode Transistor Logic

3.TTL- Transistor Transistor Logic 4.ECL-Emitter Coupled Logic
5.I2L- Integrated Injection Logic 6.PMOS- P-Channel Metal Oxide Semiconductor
7.NMOS- N-Channel Metal Oxide Semiconductor
8.CMOS- Complementary Metal Oxide Semiconductor

Characteristics of Digital IC’s:

1. FAN-IN: Number of inputs connected to gate, without the degradation in the voltage levels.
2. FAN-OUT: Number of standard loads that the output of the gate can drive without
degrading the normal operation.
3. POWER DISSIPATION: Power consumed by the gate, available from power supply.
4.PROPAGATION DELAY: Average transition time for the signal to propagate from input to
output.
5. NOISE MARGIN: Noise margin is the limit of noise voltage which may be present without
imparing or degrading the proper operation of the circuit.

TTL- Transistor Transistor Logic:

A) TTL-2 input NAND gate having totem pole (active pull-up) output stage:-
The circuit diagram of a 2-input TTL
Vcc NAND gate having an active pull-up
(totem-pole) output stage is shown in
R1 R4 figure 4.21. In this circuit, if one or both
R2
of the inputs are at logic 0, the
P T4 corresponding B-E junction of T1 will be
Inputs T2 forward biased, and the voltage at point
T1 +
VD0 D0 P will become nearly equal to 0.7V
D1 D Output which will keep the T2 and T3 OFF. ( The
2 R3
– voltage at P must be at least equal to
T3
1.8V for turning T2 and T3 ON.)
Figure 4.21: TTL- 2-Input NAND Gate(Totem Pole O/P) Therefore, the output voltage will be at
logic 1, equal to Vcc – (drop across R4)-
(VCE of T4) – VD0, which is nearly equal to
3.5V.
If both the inputs are held at logic 1 level, the B-E junctions of T1 will be reverse biased, and
the current flowing through R1 and the C-B junction of T1 will turn ON the transistors T2 and
T3. Hence, the output voltage will be at logic 0, equal to VCEsat of T3. When the voltage at the
input terminal corresponds to 1 level, the gate sinks an input current (reverse saturation
current of the B-E junction of T1), whereas when the voltage at the input terminal
corresponds to 0 level, the gate sources an input current(forward current of the B-E junction
of T1).
Advantages: 1)when T4 is OFF and T3 is ON, Disadvantage: T3 turns OFFmore slowly than
no current through R4, so, no power T4 turns ON. So, before T3 completely turns
dissipation. OFF, T4 comes into conduction. So, for a very
2)If output is high, T4 is ON and T3 is OFF, short duration of time both T3 and T4 are ON.
hence T4 is acting in the emitter follower This is called cross conduction and draws
mode, its output impedance is low. Therefore large current.
output time constant for charging of any
capacitive load is very short.

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 B) TTL- 2 input open-collector TTL NAND gate :

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The circuit diagram of a 2-input open collector TTL NAND gate is shown in figure 4.23 and
TTL-logic symbol (open collector) is shown in figure 4.22. Note that the collector of the
transistor T3 is floating. For the proper functioning of the device, this open collector terminal
of T3 must be tied to Vcc through resistor R, known as pull-up resistor (passive pull-up). Once
a suitable pull-up resistor is connected, the characteristic of open collector and totem pole
will be almost same.
Vcc
Indicates open collector
R1 R2
Inputs Output

Figure 4.22: TTL- Logic Symbol Inputs T1 T2

(Open Collector)
D1 D2 R3 Output
T3

Figure 4.23: TTL- 2-Input NAND Gate(Open Collector

O/P)
Advantage of open collector output is that wired ANDing becomes possible.
Wired ANDing as shown in figure 4.24, means tieing the outputs of gates together to obtain
AND function.
Vcc It is possible to connect the outputs of two or
more gates together.
A
Y = (A.B)’.(C.D)’
B
Y= (A.B + C.D)’
C
D
Figure 4.24: Wired ANDing of NAND gate O/P

Comparision of Totem-Pole and Open-Collector outputs:

Parameters Totem-Pole Open-collector
Circuit components on T4 (pull up transistor), T3 Only T3 (pull down transistor)
output side (pull down transistor) and
diode D0.
Wired ANDing NO Yes
External pull up resistor Not required Required
Power Dissipation Low due to Pull up transistor. High due to current flowing
through external pull up resistor.
Speed High Low

C) TTL- TRI-STATE TTL Gate:

In a normal logic circuits there are two states of the output- LOW and HIGH. When a
number of such outputs are connected to a common line, there are loading problems. To
avoid this, tri-state outputs are used. In tri-state output circuits, there are three distinct
states of which two are the logic 0 and logic 1 states and third is a high impedance state. In
the figure
4.25 of a tri-state TTL inverter circuit, when control input is LOW, the drive is removed from
T1 and T2 and the output is in the third state (High impedance). When the control input is
high, the output is 1 or 0 depending on the input. Figure 4.26 logic symbol of tristate TTL
inverter.
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Vcc

Control Data Input Data

R1 R4
R2 Output
Control
T5
T3 Data Figure 4.26 : Tri-state TTL
T4 T1
Output inverter logic symbol
Data Input
R3
T2

Figure4.25: Tri-state TTL

inverter

PMOS, NMOS, and CMOS logic:

A NMOS switch is closed when controlling signal is HIGH.

DRAIN An arrow indicates the direction of positive current flow
GATE from drain (D) to source (S) in NMOS.
SOURCE
Logic Symbol of NMOS

A PMOS switch is closed when controlling signal is LOW.

SOURCE
An arrow indicates the direction of positive current flow
GATE DRAIN from source (S) to drain (D) in PMOS.

Logic Symbol of PMOS

Realization of logic gates using MOS logic family:

VDD VDD
D
D
G S
G S
D Output (A.B)’
Input A D Output A’ Input A
G S
G S
D
Input B
G S
Inverter using NMOS
NAND using NMOS

VDD VDD
PMOS S
G D
Input A Output A’
Input A Input B Output (A+B)’ D
G
NMOS S
NOR using NMOS
Inverter using CMOS

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VDD VDD
PMOS PMOS S Input PMOS S
S
A
G D G D Output (A.B)’ G D
D Input S
Input A G S B G D
D
Input B G S D D Output (A+B)’
NMOS G S G S
NAND using CMOS
NOR using CMOS
Advantages of MOS logic: 1)Low power dissipation. 2)Excellent noise immunity.
3)High packing density. 4)Wide range of supply voltages (+3V to +18V)

INTERFACING BETWEEN TTL to MOS:

Interfacing refers the way a driving device is connected to a loading device. Here TTL is the
driving device and CMOS is the loading device. TTL device needs a supply voltage of 5V and
CMOS needs of +3V to +15V.
5V 5V
TTL High CMOS High
2.4V 3.5V
Intermediate Intermediate
state state
0.4V 1.5V
TTL Low CMOS Low
0V 0V
TTL output profile CMOS output profile
Figure 4.26: Outprofile of TTL and CMOS
Figure 4.26 shows the output profile of TTL and CMOS, a TTL low fits inside the CMOS low ie.
CMOS load always interprets the TTL low state drive as a low. The problem is with TTL high
state ie. there is indeterminate action ie. no reliable operation. So, the standard solution is to
use a pull up resistor between TTL driver and CMOS load. It raises the high state to
approximate 15V.
In figure 4.27, When TTL output is low, 3.3K
5V resistor is grounded, therefore TTL driver sink
3.3KΩ current of 1.52mA. when TTL output is high, pull
up resistor, output raises above +2.4V ie. The
supply voltage is pulling up the output upto +5V
TTL driver CMOS load (1.52mAx3.3K). If more than one TTL chip is
being interfaced to the CMOS load, connect each
Figure 4.27:TTL driver & CMOS interface
TTL driver to a separate pull-up resistor.
If CMOS IC is operated with VDD greater than 5V
5V 10V then the TTL driving high voltage CMOS design is
R used as shown in figure 4.28. Buffer is used to
interface between TTL and CMOS. IC7406 as
Buffer inverting buffer has an output voltage rating of
TTL driver CMOS load 30V.
Figure4.28:TTL driving high voltage CMOS

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