Multiple Choice Questions (Digital Logic)

1. What is the output state of an OR gate if the inputs are 0 and 1?

a. 0 b. 1
c. 2 d. 3
2. A logic circuit that provides a high output for both inputs high or both inputs low is
a. OR gate b. NAND gate
c. Ex-OR gate d. Ex-NOR gate
3. Identify the type of gate below from the equation.
Y = A+B = A̅B + AB̅ = A’.B + AB’
a. Ex-NOR gate b. OR gate
c. Ex-OR gate d. NAND gate
4. When an input electrical signal A = 10100 is applied to a NOT gate, its output signal is
a. 01011 b. 10101
c. 10100 d. 00101
5. The digital equivalent of an electric series circuit is the ……….. gate.
a. NOR b. NAND
c. OR d. AND
6. Which of the following represents analog data?
a. ON and OFF states b. 0 and 1
c. 0V and 5V d. 1.5, 3.2, 4 and 5V
7. Which logic gate does this truth table describe?

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

a. AND b. OR
c. NAND d. NOR
8. Identify the logic function as shown below.
 a. AND b. NAND
c. NOR d. OR
9. Which of the following figures given below represent a NOT gate?

a.

b.

c.

d.

10. Which of the figures given below represent a NAND gate?

a.

b.

c.

d.

11. The basic DTL configuration is ………. Gate.

 a. OR b. NOT
c. NAND d. AND
12. The basic circuit configuration for TTL resembles that of a ………. Gate.
a. OR b. NOR
c. AND d. NAND
13. NAND operation is
a. X +Y b. X . Y

c. (X ¿+ Y )( X +Y )¿ d. X +Y

14. In a certain logic gate, the output is always in logic ‘1’ state except for one input
combination when all inputs are in logic ‘1’ state. Name the gate.
a. NAND b. NOR
c. EX-OR d. AND
15. One of the following logic gates can be called a universal gate.
a. AND b. NOR
c. EX-OR d. AND
16. Minimum number of two-input AND gates required to implement a four-input AND gate
would be
a. 3 b. 2
c. 4 d. 5
17. Logic gates with associated hysteresis are called
a. INHIBIT gates b. Schmitt gates
c. Universal gates d. None of these
18. What is the minimum number of two-input EX-OR gates needed to implement a three-
input EX-OR gate?
a. 3 b. 2
c. 4 d. 5
19. What is the minimum number of two-input NAND gates required to implement a three
input NAND?
a. 2 b. 3
c. 4 d. 5
20. How many two-input EX-OR gates can be used to implement one three-input EX-NOR
gate function?
a. 2 b. 3
c. 4 d. 5
21. The logic gate shown in the following figure is an X-wide, Y-input OR-AND-INVERT gate.
What is the value of Y?

a. 2 b. 3
c. 4 d. 5
22. In the logic arrangement shown in the following figure, how many minterms will the
logic expression for the output, Y, have?

a. 2 b. 3
c. 4 d. 5
23. What is the only input combination that will produce logic ‘0’ at the output of a four-
input NAND gate?
 a. 1111 b. 1110
c. 0000 d. 1100
24. What is minimum number of two-input NAND gates required to implement two-input
OR gate?
a. 2 b. 3
c. 4 d. 5
25. The input to a four-input EX-OR logic function is 1001. The output would be
a. Logic ‘1’ b. logic ‘0’
c. indeterminate from given data d. there cannot be a four-input EX-OR logic function
26. It is proposed to construct an eight-input NAND gate using only two-input AND gates and
two-input NAND gates. What is the least number of gates required to do it?
a. 2 b. 4
c. 3 d. 7
27. An AND gate in positive logic system is a
a. NOR gate in negative logic system
b. NAND gate in negative logic system
c. AND gate in negative logic system
d. OR gate in negative logic system
28. The LOW level input and output currents of standard TTL family devices are specified as
1.6 mA and 16 mA, respectively. When the output of a NAND gate belonging to standard
TTL family is in logic ‘0’ state and is driving the two shorted inputs of a NOR gate of the
same family, what will be the current drawn by the input of the driven gate in mA?
a. 2.2 mA b. 3.2 mA
c. 4.2 mA d. 5.2 mA
29. How many possible input combinations can a four-input logic gate have?
a. 12 b. 14
c. 16 d. 18
30. Two types of bipolar logic families, one saturated and the other non-saturated, have
propagation delays of 100 ns and2 ns. What can possibly be the propagation delay (in ns)
of non-saturated logic family?
a. 2 ns b. 3 ns
c. 4 ns d. 5 ns
31. Refer to the logic circuit shown in the following figure. What is the logic status of the
output, 0 or 1, for A = logic ‘0’ and B = logic ‘1’?

a. Logic ‘1’ b. logic ‘0’

c. indeterminate d. none of these
32. How many NAND gates the TTL IC 7400 have?
a. 2 b. 3
c. 4 d. 5
33. A logic family has a HIGH state fan-out of 20 and LOW state fan-out of 10. Which of the
two values would be considered while deciding the driving capability of a logic gate of
this family?
a. 10 b. 20
c. both (a) and (b) d. none of these
34. The point P in the following figure is struck at 1. The output f will be

a. ABC b. A
c. ABC d. A
35. Refer to the following figure. Which of the following Boolean Expressions correctly
represents the relation between P, Q, R and M1?
 a. M1 = (P OR Q) XOR R b. M1 = (P AND Q) XOR R
c. M1 = (P NOR Q) XOR R d. M1 = (P XOR Q) XOR R
36. For the output F to be 1 in the logic circuit shown in the following figure, the input
combination should be

a. A = 1, B = 1, C = 0 b. A = 1, B = 0, C = 0
c. A = 0, B = 1, C = 0 d. A = 0, B = 0, C = 1
37. The output Y in the circuit shown in the following figure is always “1” when

a. Two or more of the inputs P, Q, R are “0”

b. Two or more of the inputs P, Q, R are “1”
 c. Any odd number of the inputs P, Q, R is “0”
d. Any odd number of the inputs P, Q, R is “1”
38. A bulb in a staircase has two switches, one switch being at the ground floor and the
other one at the first floor. The bulb can be turned ON and also can be turned OFF by
any one of the switches irrespective of the state of the other switch. The logic of
switching of the bulb resembles
a. An AND gate b. an OR gate
c. an XOR gate d. a NAND gate
39. In the circuit shown in the figure, if C = 0, the expression for Y is

a. Y = A B+ A B b. Y = A +B
c. Y = A +B d. Y = AB
40. The output F in the digital logic circuit shown in the figure is

a. F = X̅ Y Z + X Y̅ Z b. F = X̅ Y Z̅ + X Y̅ Z̅
c. F = X̅ Y̅ Z + X Y Z d. F = X̅ Y̅ Z̅ + X Y Z
41. In the figure shown, the output Y is required to be Y = AB + C̅D̅. The gates G1 and G2 must
be, respectively?
 a. NOR, OR b. OR, NAND
c. NAND, OR d. AND, NAND
42. A 3-input majority gate is defined by the logic function M (a , b , c )=ab+ bc+ ca. Which
one of the following gates is represented by the function M ¿ ¿, M ¿), c)?
a. 3-input NAND gate b. 3-input XOR gate
c. 3-input NOR gate d. 3-input XNOR gate
43. A universal logic gate can be implement any Boolean function by connecting sufficient
number of them appropriately. Three gates are shown.

a. Gate 1 is a universal gate b. Gate 2 is a universal gate

c. Gate 3 is a universal gate d. None of the gates shown is a universal gate
44. A decoder is nothing but a demultiplexer without
a. Control inputs b. data inputs
c. enable input d. None of these
45. Identify the product-of-sums Boolean function represented by logic diagram shown in
the following figure.
 a. F (A, B, C) = ∏1, 2, 5
b. F (A, B, C) = ∏0, 3, 4, 6, 7
c. F (A, B, C) = ∏0, 3, 4, 6
d. F (A, B, C) = ∑0, 3, 4, 6, 7
46. The following figure shown below depicts the logic diagram and truth table of a 10-line
decimal to 4-line BCD priority encoder. Which decimal digit or digits in this have priority
encoding?
a. 0 has priority encoding b. has priority encoding
c. 0 and 9 have priority encoding d. higher order digits have priority encoding
47. In the case of subtraction of two bits, what will be the DIFFERENCE output when
minuend and subtrahend bits respectively are 0 and 1?
a. 1 b. 2
c. 3 d. 4
48. In the basic logic circuit shown in the following figure, determine the status of X for A =
0, B = 1 and C = 0.

b. 1 b. 2
c. 3 d. 4
49. A multiplexer has X data inputs, three control inputs and one output. What is X?
a. 2 b. 4
c. 6 d. 8
50. Identify the logic status of F output for I 0 = I2 = 0, I1 = I3 = 1, S0 = 1 and S1 = 0. Function
performed by the logic diagram shown in the following figure.

a. 0 b. 1
c. 2 d. 3
51. An 8-to-1 multiplexer is used to generate the CARRY output of a full-adder. If the three
control inputs are used as the two input bits to be added and the CARRY IN bit; how
many numbers of data bits would need to be tied to logic ‘1’ status?
a. 2 b. 4
c. 6 d. 8
52. In a decoder, n is the number of input lines and m is the number of output lines. One of
the following equation is valid.
a. m = 2n b. n = 2m
c. m ≤ 2n d. n ≤ 2m
53. The 10-input bits to a 10-line decimal to four-line BCD priority encoder corresponding to
0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 respectively, are 1, 0, 0, 0, 1, 1, 0, 1, 0 and 0. What will be the
corresponding BCD output if all inputs and outputs are active HIGH? The encoder has
priority for higher order bits.
a. 0111 b. 1000
c. 1001 d. 0110
54. The logic circuit given below converts the binary code y1, y2, y3 into (given that y1 = 0)

a. Excess-3 code b. Gray code

c. BCD code d. Hamming code
55. Determine the number of data outputs in a 1-to-32 demultiplexer.
a. 1 b. 2
c. 3 d. 4
56. What is the least number of input lines in a multiplexer capable of implementing the
following Boolean function: ∑1, 13?
a. 2 b. 4
c. 6 d. 8
57. What is the least number of input lines in a multiplexer capable of implementing the
following Boolean function: ∏9, 9, 10, 11, 12, 13, 14, 15?
a. 2 b. 4
c. 6 d. 8
58. How many two-input EX-OR gates would be required to generate the SUM output of
addition of three bits?
a. 2 b. 4
c. 6 d. 8
59. Without any additional circuitry, an 8:1 MUX can be used to obtain
a. Some but not all Boolean functions of three variables
b. All functions of three variables, but none of four variables
c. All functions of three variables and some but not all of four variables
d. All functions of 4 variables
60. The minimum number of 2-to-1 multiplexers required to realize a 4-to-1 multiplexer is
a. 1 b. 2
c. 3 d. 4
61. The Boolean function f implemented in the following figure using two input multiplexers
is

a. AB’C + ABC’ b. ABC + AB’C’

c. A’BC + A’B’C’ d. A’B’C + A’ B C’
62. In the circuit shown in the following figure, X is given by

a. X = AB̅C̅ + A̅BC̅ + A̅B̅C + ABC b. X = A̅BC + AB̅C + ABC̅ + A̅B̅C̅

c. X = AB + BC +AC d. X = A̅B̅ + B̅C̅ + A̅C̅
63. What are the minimum number of NOT gates and two-input OR gates required for
designing the logic of the driver for this seven-segment display?
a. 3 NOT and 4 OR b. 2 NOT and 4 OR
 c. 1 NOT and 3 OR d. 2 NOT and 3 OR
64. What are the minimum number of 2-to-1 multiplexers required to generate a two-input
AND gate and a two-input EX-OR gate?
a. 1 and 2 b. 1 and 3
c. 1 and 1 d. 2 and 2
65. The Boolean function realize by the logic circuit shown in the following figure is

a. F = ∑ m (0, 1, 3, 5, 9, 10, 14) b. F = ∑ m (2, 3, 5, 7, 8, 12, 13)

c. F = ∑ m (1, 2, 4, 5, 11, 14, 15) d. F = ∑ m (2, 3, 5, 7, 8, 9, 12)
66. The logic function implemented by the circuit shown in the following figure is (ground
implies a logic ‘0’)
 a. F = AND (P, Q) b. F = OR (P, Q)
c. F = XNOR (P, Q) d. F = XOR (P, Q)

67. Consider the multiplexer-based logic circuit shown in the figure.

b. F=W S1 S 2 b. F=W S1 +W S 2 +S 1 S 2

c. F=W + S1 + S2 d. F=W ⊕ S1 ⊕ S 2

68. In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by

a. F = W X̅ + W̅ X +Y̅ Z̅ b. F = W X̅ + W̅ X +Y̅ Z
c. F = W X̅ Y̅ + W̅ X Y̅ d. F = (W̅ + X̅) Y̅ Z
69. An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure.
The output Y is given by
 a. Y = A B̅ C + A C̅ D b. Y = A̅ B C + A B̅ D
c. Y = A B C̅ + A̅ C D d. Y = A̅ B̅ D + A B̅ C
70. A 10 KHz clock signal having a duty cycle of 25% is used to clock a three-bit binary ripple
counter. What will be the frequency and duty cycle of true output of the MSB flip-flop?
a. 1.25 KHz, 25% b. 3.33 KHz, 25%
c. 3.33 KHz, 50% d. 1.25 KHz, 50%