UNIT II – ARITHMETIC FOR COMPUTERS

2.1 Addition and Subtraction of Signed Numbers

2.1.1 Addition of Signed Numbers

Addition and subtraction of two numbers are basic operations at the machine-
instruction level in all computers. These operations, as well as other arithmetic and logic
operations, are implemented in the arithmetic and logic unit (ALU) of the processor. In this
unit, we present the logic circuits used to implement arithmetic operations. The time needed
to perform addition or subtraction affects the processor's performance. Multiply and divide
operations, require more complex circuitry than either addition or subtraction operations,
that also affects performance. Here we described the representation of signed binary
numbers, and showed that 2's-complement is the best representation from the standpoint of
performing addition and subtraction operations.
The truth table for the sum and carry-out functions for adding equally weighted
bits x; and yi in two numbers X and Y is given below.

Addition of the 4-bit unsigned numbers 7 and 6.

At each stage of the addition process must accommodate a carry-in bit. We use ci to
represent the carry-in to stage i, which is the same as the carry-out from stage (i — 1).

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The logic expression for si can be implemented with a 3-input XOR gate, used as part of the

logic required for a single stage of binary addition.

The carry-out function, ci+1, is implemented with an AND-OR circuit, as shown.

A convenient symbol for the complete circuit for a single stage of addition, called
a Full adder (FA), is also shown in the figure.

A cascaded connection of n full-adder blocks can be used to add two n-bit

numbers, as shown in (b).

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 Since the carries must propagate, or ripple, through this cascade, the
configuration is called a ripple-carry adder. The n-bit adder can be used to add 2's-

complement numbers X and Y, where the x„_1 and y„_1, bits are the sign bits.

The carry-in, co, into the least-significant-bit (LSB) position helps us to add 1 to a

number.
For example, the 2's-complement of a number can be formed by adding 1 to the
1's-complement of the number. The carry signals are also useful for interconnecting k
adders to form an adder capable of handling input numbers that are kn bits long, as shown
in Figure.

2.1.2 Subtraction of Signed Numbers

Subtraction operation X — Y :
Form the 2's-complement of Y and add it to X.

The following logic circuit can be used to perform either addition or subtraction

based on the value applied to the Add/Sub input control line.

For addition:
This line is set to 0 for addition, then apply Y unchanged to one of the adder

inputs along with a carry-in signal, c0, of 0.

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 For Subraction:
The Add/Sub control line is set to 1, so the Y number is 1 's-complemented by

the XOR gates and c0 is set to 1 to complete the 2's-complementation of Y.

2.2 Design of Fast Adders

If the above n-bit ripple-carry adder is used in the addition/subtraction circuit , it
may have too much delay in developing its outputs s0 through sn-1 and cn. One approach to

reduce delay in adders is to use a logic gate network called a carry-lookahead network.

2.2.1 Carry-Lookahead Addition

A fast adder circuit must speed up the generation of the carry signal. The logic

expression for si (sum) and ci+1 (carry-out) of stage i are:

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 Gi is called the generate function for stage i. If the generate function for stage i
is equal to 1, then ci+1 = 1, independent of the input carry, ci. This occurs when both xi
and yi are 1.

Pi is called the propagate functions for stage i. The propagate function means
that an input carry will produce an output carry when either xi is 1 or yi is 1.

All Gi and Pi functions can be formed independently and in parallel in one logic
gate delay after the X and Y operands are applied to the inputs of an n-bit adder.
Propagate function can be implemented as Pi = xi yi.

Two 2-input XOR gates to realize the 3-input XOR function for si,

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For a 4-bit adder the carries can be implemented independently as follows.

The complete 4 bit adder is shown in the diagram. The carries are produced in block labeled

Carry-lookahead logic.

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2.3 Multiplication of Unsigned Numbers
The first operand is called the multiplicand and the second the multiplier. The final result
is called the product.
If we ignore the sign bits, the length of the multiplication of an n-bit multiplicand and an
m-bit multiplier is a product that is n+ m bits long.

2.3.1 Array Multiplier

Binary multiplication of unsigned operands can be implemented in a

combinational, two-dimensional, logic array, as shown in Figure for the 4-bit operand case

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The main component in each cell is a full adder, FA.

The AND gate in each cell determines whether a multiplicand bit, nth is added to
the incoming partial-product bit, based on the value of the multiplier bit, qi. Each row i,
where 0 ≤ i ≤ 3, adds the multiplicand (appropriately shifted) to the incoming partial
product, PPi, to generate the outgoing partial product, PP(i 1), if qi = 1. If qi = 0, PPi is
passed vertically downward unchanged. PP0 is all 0s, and PP4 is the desired product. The
multiplicand is shifted left one position per row by the diagonal signal path.

2.3.2 Sequential Circuit Multiplier

The combinational array multiplier just described uses a large number of logic
gates for multiplying numbers of practical size, such as 32- or 64-bit numbers. Multiplication
of two n-bit numbers can also be performed in a sequential circuit that uses a single n-bit
adder.This circuit performs multiplication by using a single n-bit adder n times to implement
the spatial addition performed by then rows of ripple-carry adders.

Registers A and Q are shift registers. Together, they hold partial product PPi
while multiplier bit qi generates the signal Add/Noadd. This signal causes the multiplexer
MUX to select 0 when qi = 0, or to select the multiplicand M when qi = 1, to be added to
PPi to generate PP(i + 1). The product is computed in n cycles.

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The block diagram in Figure shows the hardware arrangement for sequential multiplication.

The partial product grows in length by one bit per cycle from the initial vector, PP0, of n
0’s in register A. The carry-out from the adder is stored in flip-flop C. shown at the left
endof register A.

At the start, the multiplier is loaded into register Q, the multiplicand into register M. and C
and A are cleared to 0. At the end of each cycle, C, A. and Q are shifted right one bit
position to allow for growth of the partial product as the multiplier is shifted out of
register Q.

Because of this shifting, multiplier bit 0 appears at the LSB position of Q to generate the
Add/No add signal at the correct time, starting with qo during the first cycle. qi during the
second cycle, and so on. After they are used, the multiplier bits are discarded by the right-
shift operation.

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 Note that the carry-out from the adder is the leftmost bit of PP(i + 1) and it must be held
in the C flip-flop to be shifted right with the contents of A and Q. After n cycles, the high-
order half of the product is held in register A and the low-order half is in register Q
The multiplication example as it would be performed by hardware arrangement

2.3.3 Multiplication of Signed numbers

Consider a positive multiplier and a negative multiplicand. When we add a

negative multiplicand to a partial product, we must extend the sign-bit value of the
multiplicand to the left as far as the product will extend. An example shows a 5-bit signed
operand, —13, which is the multiplicand. It is multiplied by +11 to get the 10-bit product, —

143. The sign extension of the multiplicand is shown in grey.

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 UNIT II COMPUTER ARITHMETIC
Addition and Subtraction of Signed Numbers - Design of Fast Adders - Multiplication of Unsigned Numbers
- Multiplication of Signed Numbers - Fast Multiplication - Integer Division - Floating-Point Numbers and
Operations

Booth's Multiplication Algorithm

• The booth algorithm is a multiplication algorithm that allows us to multiply the two signed binary
integers in 2's complement, respectively. It is also used to speed up the performance of the
multiplication process. It is very efficient too.
• It works on the string bits 0's in the multiplier that requires no additional bit only shift the right-most
string bits and a string of 1's in a multiplier bit weight 2k to weight 2m that can be considered as 2k+ 1-
2m
• Following is the pictorial representation of the Booth's Algorithm:

• In the above flowchart, initially, AC and Qn + 1 bits are set to 0, and the SC is a sequence counter that
represents the total bits set n, which is equal to the number of bits in the multiplier. There are BR that
represent the multiplicand bits, and QR represents the multiplier bits.
• After that, we encountered two bits of the multiplier as Qn and Qn + 1, where Qn represents the last bit
of QR, and Qn + 1 represents the incremented bit of Qn by 1. Suppose two bits of the multiplier is equal
to 10; it means that we have to subtract the multiplier from the partial product in the accumulator AC
and then perform the arithmetic shift operation (ashr).
 • If the two of the multipliers equal to 01, it means we need to perform the addition of the multiplicand
to the partial product in accumulator AC and then perform the arithmetic shift operation (ashr),
including Qn + 1.
• The arithmetic shift operation is used in Booth's algorithm to shift AC and QR bits to the right by one
and remains the sign bit in AC unchanged. And the sequence counter is continuously decremented till
the computational loop is repeated, equal to the number of bits (n).
Working on the Booth Algorithm
1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.
2. Initially, we set the AC and Qn + 1 registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a sequence counter that is continuously
decremented till equal to the number of bits (n) or reached to 0.
4. A Qn represents the last bit of the Q, and the Qn+1 shows the incremented bit of Qn by 1.
5. On each cycle of the booth algorithm, Qn and Qn + 1 bits will be checked on the following parameters
as follows:
i. When two bits Qn and Qn + 1 are 00 or 11, we simply perform the arithmetic shift right operation
(ashr) to the partial product AC. And the bits of Qn and Qn + 1 is incremented by 1 bit.
ii. If the bits of Qn and Qn + 1 is shows to 01, the multiplicand bits (M) will be added to the AC
(Accumulator register). After that, we perform the right shift operation to the AC and QR bits
by 1.
iii. If the bits of Qn and Qn + 1 is shows to 10, the multiplicand bits (M) will be subtracted from the
AC (Accumulator register). After that, we perform the right shift operation to the AC and QR
bits by 1.
6. The operation continuously works till we reached n - 1 bit in the booth algorithm.
7. Results of the Multiplication binary bits will be stored in the AC and QR registers.
• There are two methods used in Booth's Algorithm:
1. RSC (Right Shift Circular)
It shifts the right-most bit of the binary number, and then it is added to the beginning of the binary bits.

2. RSA (Right Shift Arithmetic)

It adds the two binary bits and then shift the result to the right by 1-bit position.
Example: 0100 + 0110 => 1010, after adding the binary number shift each bit by 1 to the right and put the
first bit of resultant to the beginning of the new bit.

Example: Multiply the two numbers 7 and 3 by using the Booth's multiplication algorithm.
Ans. Here we have two numbers, 7 and 3.
• First of all, we need to convert 7 and 3 into binary numbers like 7 = (0111) and 3 = (0011).
• Now set 7 (in binary 0111) as multiplicand (M) and 3 (in binary 0011) as a multiplier (Q). And SC
(Sequence Count) represents the number of bits, and here we have 4 bits, so set the SC = 4. Also, it
shows the number of iteration cycles of the booth's algorithms and then cycles run SC = SC - 1 time.
 Qn Qn + 1 M= (0111) AC Q Qn + 1 SC
M' + 1 = (1001) & Operation

1 0 Initial 0000 0011 0 4

Subtract - Addition (AC+M' + 1) 1001

1001

Perform Arithmetic Right Shift 1100 1001 1 3

operations (ashr)

1 1 Perform Arithmetic Right Shift 1110 0100 1 2

operations (ashr)

0 1 Addition (AC + M) 0111

0101 0100

Perform Arithmetic right shift 0010 1010 0 1

operation

0 0 Perform Arithmetic right shift 0001 0101 0 0

operation

The numerical example of the Booth's Multiplication Algorithm is 7 x 3 = 21 and the binary representation of
21 is 10101. Here, we get the resultant in binary 00010101. Now we convert it into decimal, as
(000010101)10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21.

Example: Multiply the two numbers 23 and -9 by using the Booth's multiplication algorithm.
Here, M = 23 = (010111) and Q = -9 = (110111)
• Now set 23 (in binary 010111) as multiplicand (M) and -9 (in binary 110111) as a multiplier (Q). And
SC (Sequence Count) represents the number of bits, and here we have 6 bits, so set the SC = 6. Also,
it shows the number of iteration cycles of the booth's algorithms and then cycles run SC = SC - 1 time.

Qn Qn + 1 M=010111 AC Q Qn+1 SC
M' + 1 = 1 0 1 0 0 1

Initially 000000 110111 0 6

1 0 Subtract - Addition (AC+M' + 1) 101001

101001

Perform Arithmetic right shift 110100 111011 1 5

operation

1 1 Perform Arithmetic right shift 111010 011101 1 4

operation

1 1 Perform Arithmetic right shift 111101 001110 1 3

operation
 0 1 Addition (AC+ M) 010111

010100

Perform Arithmetic right shift 001010 000111 0 2

operation

1 0 Subtract M - Addition (AC+M' + 1) 101001

110011

Perform Arithmetic right shift 111001 100011 1 1

operation

1 1 Perform Arithmetic right shift 111100 110001 1 0

operation
Qn + 1 = 1, it means the output is negative.
Hence, 23 * -9 = 2's complement of 111100110001 => (000011001111) => -207

Example:
A numerical example of booth’s algorithm is shown below for n = 4.
It shows the step-by-step multiplication of -5 and -7.
• Now set -5 (in 2’s 1011) as multiplicand (M) and -7 (in 2’s 1001) as a multiplier (Q). And SC (Sequence
Count) represents the number of bits, and here we have 4 bits, so set the SC = 4. Also, it shows the
number of iteration cycles of the booth's algorithms and then cycles run SC = SC - 1 time.

Qn Qn + 1 M= 1011 AC Q Qn+1 SC
M' + 1 = 0101

Initially 0000 1001 0 4

1 0 Subtract - Addition (AC+M' + 1) 0101

0101

Perform Arithmetic right shift 0010 1100 1 3

operation

0 1 Addition (AC+ M) 1011

1101

Perform Arithmetic right shift 1110 1110 0 2

operation

0 0 Perform Arithmetic right shift 1111 0111 0 1

operation

1 0 Subtract M - Addition (AC+M' + 1) 0101

0100 0111

Perform Arithmetic right shift 0010 0011 0 0

operation
Product is calculated as follows:
Product = AC Q
Product = 0010 0011 = 35
The numerical example of the Booth's Multiplication Algorithm is -5 x -7 = 35 and the binary
representation of 35 is 100011. Here, we get the resultant in binary 00010101. Now we convert it into decimal,
as (000010101)10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21.

Advantages:
Faster than traditional multiplication: Booth’s algorithm is faster than traditional multiplication methods,
requiring fewer steps to produce the same result.
Efficient for signed numbers: The algorithm is designed specifically for multiplying signed binary numbers,
making it a more efficient method for multiplication of signed numbers than traditional methods.
Lower hardware requirement: The algorithm requires fewer hardware resources than traditional
multiplication methods, making it more suitable for applications with limited hardware resources.
Widely used in hardware: Booth’s algorithm is widely used in hardware implementations of multiplication
operations, including digital signal processors, microprocessors, and FPGAs.

Disadvantages:
Complex to understand: The algorithm is more complex to understand and implement than traditional
multiplication methods.
Limited applicability: The algorithm is only applicable for multiplication of signed binary numbers, and
cannot be used for multiplication of unsigned numbers or numbers in other formats without additional
modifications.
Higher latency: The algorithm requires multiple iterations to calculate the result of a single multiplication
operation, which increases the latency or delay in the calculation of the result.
Higher power consumption: The algorithm consumes more power compared to traditional multiplication
methods, especially for larger inputs.

Fast Multiplication
• Fast multiplication techniques like Bit Pair Recoding and Carry Save Adder (CSA) help in optimizing
binary multiplication by reducing the number of operations required and improving speed. Here's a
brief overview of each method:
1. Bit Pair Recoding
• Bit Pair Recoding optimizes binary multiplication by reducing the number of partial products
generated. Here's how it works:
Basic Idea:
• Instead of generating partial products for each bit in the multiplier, Bit Pair Recoding groups bits into
pairs to simplify the multiplication process.
Steps:
1. Group Bits in Pairs:
o Recoding groups of two bits are used to reduce the number of partial products. For example,
for a 4-bit multiplier, recoding might use pairs like (00, 01, 10, 11).
2. Use Recoding Rules:
o Each bit pair is recoded into a form that minimizes the number of required partial products. For
instance:
▪ 00 → 0
▪ 01 → 1
▪ 10 → -1 (with carry adjustment)
▪ 11 → 2 (can be handled with additional shifts)
3. Multiply and Shift:
o Apply the recoded values to the multiplicand, adjust for shifts, and sum the results.
Example: Multiply 6 by 5
Let’s multiply 6 and 5 using bit pair recoding.

011000
+ 000110
---------
011110
3. Convert Result Back to Decimal:
 • Binary 0111102 = 3010.

Carry Save Adder (CSA)

• Carry Save Adder is used to speed up the addition of multiple partial products. It helps in managing
carry propagation more efficiently.
Basic Idea:
• CSA reduces the time required for addition by not waiting for carry propagation between addition
stages.
Steps:
• Partial Product Generation: In multiplication, each bit of one operand is multiplied by each bit of
the other operand, producing partial products. For instance, in binary multiplication, if you have two
numbers A and B, each bit of B is multiplied by A, producing multiple partial products.
• Carry-Save Addition: Instead of adding these partial products directly, which can be slow, you use
carry-save adders to sum them efficiently. CSAs add three binary numbers at once and produce a sum
and a carry. The carry is stored separately and added later.
• Structure: Typically, a CSA takes three inputs and produces two outputs: a sum and a carry. These are
then fed into subsequent CSAs. This process is repeated in a tree structure where each stage reduces
the number of numbers to add by combining them in pairs using CSAs.
• Final Addition: Once the number of partial products is reduced to two, you perform a final addition
using a standard adder (like a ripple-carry adder or a carry-lookahead adder).
Integer Division
• Restoring division is usually performed on the fixed-point fractional numbers.
• When we perform division operations on two numbers, the division algorithm will give us two things,
i.e., quotient and remainder. This algorithm is based on the assumption that 0 < D < N. With the help
of digit set {0, 1}, the quotient digit q will be formed in the restoring division algorithm.
• The division algorithm is generally of two types, i.e., fast algorithm and slow algorithm. Goldschmidt
and Newton-Raphson are the types of fast division algorithm, and STR algorithm, restoring algorithm,
non-performing algorithm, and the non-restoring algorithm are the types of slow division algorithm.
• In this section, we are going to perform restoring algorithm with the help of an unsigned integer. We
are using restoring term because we know that the value of register A will be restored after each
iteration. We will also try to solve this problem using the flow chart and apply bit operations.

Restoring Division Algorithm for Unsigned Integer

• Figure shows the operations of division.
 • Here, register Q is used to contain the quotient, and register A is used to contain the remainder. Here,
the divisor will be loaded into the register M, and n-bit dividend will be loaded into the register Q. 0
is the starting value of a register. The values of these types of registers are restored at the time of
iteration. That's why it is known as restoring.

Now we will learn some steps of restoring division algorithm, which is described as follows:
Step 1: In this step, the corresponding value will be initialized to the registers, i.e., register A will contain
value 0, register M will contain Divisor, register Q will contain Dividend, and N is used to specify the number
of bits in dividend.
Step 2: In this step, register A and register Q will be treated as a single unit, and the value of both the registers
will be shifted left.
Step 3: After that, the value of register M will be subtracted from register A. The result of subtraction will be
stored in register A.
Step 4: Now, check the most significant bit of register A. If this bit of register A is 0, then the least significant
bit of register Q will be set with a value 1. If the most significant bit of A is 1, then the least significant bit of
register Q will be set to with value 0, and restore the value of A that means it will restore the value of register
A before subtraction with M.
Step 5: After that, the value of N will be decremented. Here n is used as a counter.
Step 6: Now, if the value of N is 0, we will break the loop. Otherwise, we have to again go to step 2.
Step 7: This is the last step. In this step, the quotient is contained in the register Q, and the remainder is
contained in register A.
For example:
In this example, we will perform a division restoring algorithm.
1. Dividend = 11
2. Divisor = 3

N M A Q Operation

4 00011 00000 1011 Initialize

00011 00001 011_ Shift left AQ

00011 11110 011_ A=A- M

00011 00001 0110 MSB(A) =1, Q[0] = 0 And

restore A

3 00011 00010 110_ Shift left AQ

00011 11111 110_ A=A- M

00011 00010 1100 MSB(A) =1, Q[0] = 0 And

restore A

2 00011 00101 100_ Shift left AQ

00011 00010 100_ A=A- M

00011 00010 1001 MSB(A) =0, Q[0] = 1

1 00011 00101 001_ Shift left AQ

00011 00010 001_ A=A- M

00011 00010 0011 MSB(A) =0, Q[0] = 1

So we should not forget to restore the value of the most significant bit of A, which is 1. So, register A contains
the remainder 2, and register Q contains the quotient 3.

Non-Restoring Division Algorithm for Unsigned Integer

• Instead of the quotient digit set {0, 1}, the set {-1, 1} is used by the non-restoring division.
 • The non-restoring division algorithm is more complex as compared to the restoring division algorithm.
But when we implement this algorithm in hardware, it has an advantage, i.e., it contains only one
decision and addition/subtraction per quotient bit. After performing the subtraction operation, there
will not be any restoring steps. Due to this, the numbers of operations basically cut down up to half.
Because of the less operation, the execution of this algorithm will be fast. This algorithm basically
performs simple operations such as addition, subtraction. In this method, we will use the sign bit of
register A. 0 is the starting value/bit of register A.

Now we will learn steps of the non-restoring division algorithm, which are described as follows:
Step 1: In this step, the corresponding value will be initialized to the registers, i.e., register A will contain
value 0, register M will contain Divisor, register Q will contain Dividend, and N is used to specify the number
of bits in dividend.
Step 2: In this step, we will check the sign bit of A.
Step 3: If this bit of register A is 1, then shift the value of AQ through left, and perform A = A + M. If this bit
is 0, then shift the value of AQ into left and perform A = A - M. That means in case of 0, the 2's complement
of M is added into register A, and the result is stored into A.
Step 4: Now, we will check the sign bit of A again.
Step 5: If this bit of register A is 1, then Q[0] will become 0. If this bit is 0, then Q[0] will become 1. Here
Q[0] indicates the least significant bit of Q.
Step 6: After that, the value of N will be decremented. Here N is used as a counter.
Step 7: If the value of N = 0, then we will go to the next step. Otherwise, we have to again go to step 2.
Step 8: We will perform A = A + M if the sign bit of register A is 1.
Step 9: This is the last step. In this step, register A contains the remainder, and register Q contains the quotient.
For example:
In this example, we will perform a Non-Restoring Division algorithm with the help of an Unsigned integer.
1. Dividend = 11
2. Divisor = 3
3. -M = 11101

N M A Q Action

4 00011 00000 1011 Begin

00011 00001 011_ Sign bit(A) =0, Shift left AQ

00011 11110 011_ A=A- M

00011 11110 0110 Sign bit(A) =1, Q[0] = 0

3 00011 11100 110_ Sign bit(A) =1, Shift left AQ

00011 11111 110_ A=A+ M

00011 11111 1100 Sign bit(A) =1, Q[0] = 0

2 00011 11111 100_ Sign bit(A) =1, Shift left AQ

00011 00010 100_ A = A +M

00011 00010 1001 Sign bit(A) =0, Q[0] = 1

1 00011 00101 001_ Sign bit(A) =0, Shift left AQ

00011 00010 001_ A=A- M

00011 00010 0011 Sign bit(A) =0, Q[0] = 1

So, register A contains the remainder 2, and register Q contains the quotient 3.

Floating Point Operations:

Addition and Subtraction:
• Align Exponents: Adjust the significand of the number with the smaller exponent to match the larger
exponent.
• Perform the Operation: Add or subtract the significands.
• Normalize the Result: Ensure the result is in normalized form (i.e., the leading bit is 1).
• Round the Result: Apply rounding rules to fit the result within the precision limit.
2. Align the binary numbers for addition
Align the numbers by placing the binary point:
11.01
00.11
3. Perform Binary Addition
Add the numbers bit by bit from right to left:

11.01
00.11
-----------
100.00
Multiplication:
• Multiply Significands: Perform binary multiplication on the significands.
• Add Exponents: Add the exponents of the two numbers and adjust for the bias.
• Normalize the Result: Adjust the result so that it fits the normalized format.
• Round the Result: Apply rounding rules.

Division:
• Divide Significands: Perform binary division on the significands.
• Subtract Exponents: Subtract the exponent of the divisor from the dividend and adjust for the bias.
• Normalize the Result: Adjust the result so that it fits the normalized format.
• Round the Result: Apply rounding rules.