Scribd
Upload
28 views

PCIe Power Management

Pcie power management topic

Uploaded by

Sachin R Devang
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
28 views

PCIe Power Management

Pcie power management topic

Uploaded by

Sachin R Devang
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

PCIE POWER MANAGEMENT

Traditionally PCI Express cards / devices were always considered as Power hungry. They
were always used in systems where power supply was always plugged-in. Recently PCI-SIG has
introduced PCIe with smaller form factors, which have significant power savings making them
easy to adapt to battery powered devices like Laptops, Tablets and even mobile phones.

Figure: Various PCIe form factors

PCI CEM (Card ElectroMechanical) is the largest form factor device being used in the
traditional add-in graphics card or in data center applications.

PCIe U.2 is the mid-sized form factor device primarily used in SSD (solid state devices)
as a replacement to HDD.

PCIe M.2 is the next generation smallest form factor ideal to be used in tablets, ultra-light
and thin laptops, smartphones and hand-held devices.

PCI Express-PM defines Link power management states, that a PCI Express physical
Link is permitted to enter in response to either software driven D-state transitions or Active State

RAVIKUMAR JAVALI 1

ELECTRONICSPEDIA

RAVIJAVALI
Link Power Management (ASPM) activities. PCIe spec Defined Link states are L0, L0s, L1, L2,
and L3. The power savings increase as the Link state transitions from L0 through L3.

PCIe supports

1. PCI-PM Software defined power states


2. Active State Power Management (ASPM)

PCIe Device PM States


PCI Express supports all PCI-PM device power management states. Various Device states
are from D0 to D3. Few device states are mandatory to support and few are optional.

State Description
D0 Mandatory. PCI Express supports all PCI-PM device power management
states
D1 Optional. Indicates lower power savings than D2 and higher power
savings than D1.
D2 Optional. Indicates lower power savings than D3 and higher power
savings than D2.
D3 Mandatory. Indicates a deeper low power state. Recovery time is longer
than D2 and power can be removed gracefully.

PCIe Link States


PCI Express-PM defines the following Link power management states.

L0 → L0 support is required for both ASPM and PCI-PM compatible power management.
All PCI Express transactions and other operations are enabled.

L0s → A low resume latency, energy saving “standby” state. L0s support is optional for ASPM
unless the applicable form factor specification for the Link explicitly requires L0s support. It is

RAVIKUMAR JAVALI 2

ELECTRONICSPEDIA

RAVIJAVALI
not applicable to PCI-PM compatible power management. All main power supplies, component
reference clocks, and components’ internal PLLs must be active at all times during L0s. TLP and
DLLP transmission is disabled for a Port whose Link is Tx_L0s.

L1 → Higher latency, lower power “standby” state. L1 support is required for PCI-PM compatible
power management. L1 is optional for ASPM. All main power supplies must remain active during
L1. All platform-provided component reference clocks must remain active during L1. Can have
sub low power states L1.1 and L1.2

L2 → Auxiliary-powered Link, deep-energy-saving state. L2 support is optional, and dependent


upon the presence of Vaux. A component may only consume Vaux power. In L2, the component’s
main power supply inputs and reference clock inputs are shut off.

L3 → Link Off state. When no power is present, the component is in the L3 state.

Figure: Link Power Management State Flow Diagram

RAVIKUMAR JAVALI 3

ELECTRONICSPEDIA

RAVIJAVALI
Below table shows the relationship of Device states and Link States and what are the
clocks, supplies can be turned off during each state.

D-State Permissible Trigger Active power Active clocks


Link States supply
D0Unitialized L0 NA
L0 Vmain Refclk
D0Active L0s ASPM + +
L1 Vaux Auxclk
D1, D2, D3hot L1
D3cold L2 PCI-PM Vaux Auxclk
L3 OFF OFF

As shown in the above table, L0 and L0s, L1 can be achieved be ASPM from D0Active State. In
these states the Main Power supply and Auxiliary power supplies are present, similarly the
reference clock and auxiliary clocks are present.

L1 can be entered from ASPM or PCI-PM. L1 can be entered through PCI-PM can be entered
from D1, D2 and D3hot device states, whereas L2 and L3 link states are entered only though PCI-
PM from D3cold state. These link states offer greater power states.

In L2 link states the main power supply and reference clocks are turned off, only the Auxiliary
power and auxiliary clock are present, whereas in L3 state both the auxiliary clocks and power are
turned off.

With above said power saving link states and device states, PCIe has been evolved to use greatly
with M.2 form factor targeting the smartphone, hand-held devices which run on the battery
providing faster data transfer and reduced power consumption.

RAVIKUMAR JAVALI 4

ELECTRONICSPEDIA

RAVIJAVALI

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy