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Blmjdb Abdelhafid
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20 views

S3

Uploaded by

Blmjdb Abdelhafid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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module D_latch( C,D,Q);

input C,D;

output Q;

wire w3,w6,w7;

not #(1) inv_1(w3,C);

nmos #(1) nmos_2(D,Q,C); // 0.3u 0.05u

pmos #(1) pmos_3(D,Q,w3); // 0.5u 0.05u

not #(1) inv_4(w6,Q);

pmos #(2) pmos_5(Q,w7,C); // 0.5u 0.05u

nmos #(2) nmos_6(Q,w7,w3); // 0.3u 0.05u

not #(1) inv_7(w7,w6);

endmodule

// Simulation parameters in Verilog Format

always

#200 C=~C;

#400 D=~D;

// Simulation parameters
// C CLK 1 1

// D CLK 2 2

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