ADE Lab front page B section

.
K.S.RANGASAMY COLLEGE OF TECHNOLOGY

(Autonomous Institution)
TIRUCHENGODE – 637 215
LAB MANUAL CUM

RECORD NOTE BOOK
50 EC 5P2–CMOS DESIGN LABORATORY

V- Semester B.E- Electronics and Communication Engineering
Department of Electronics and Communication Engineering

K.S.Rangasamy College of Technology
Tiruchengode – 637 215
LABORATORY CLASSES – INSTRUCTIONS TO STUDENTS
1. Students must wear uniform to the laboratory classes. Boys - Shirts tucked in and
wearing closed leather shoes; Girls with cut shoes, overcoat, plait inside the coat.
2. Attendance is mandatory and a passing grade in the laboratory component is
required to pass the course
3. Students must check if the components, instruments and equipment are in working
condition before setting up the experiment.
4. Power supply to the experimental setup/equipment must beswitched on only
after the faculty checks and gives approval for doing the experiment.
5. Any damage to any of the equipment / instrument caused due to carelessness, the
cost will be fully recovered from the individual (or) group of students.
6. Students may contact the Lab In charge immediately for any unexpected incidents
and emergency.
7. The apparatus used for the experiments must be returned to the technician, safely
without any damage.
8. Make sure, while leaving the lab after the stipulated time, that all the power
connections are switched off.
Guidelines:
9. There are four hours assigned weekly to the laboratory session of each experiment
10. Student has to complete the aim-1 of each experiment in first two hours and aim-2
in next two hours including answering for post lab questions.
Open Ended Experiments:
11. Students can choose any logic/ applications given in each experiment or bring logic/
applications of their choice suitable to the given experiment.
12. Students should be prepared for all the given example logic/ applications before
coming to the laboratory. A lot system will be introduced for the selection of
experiments for that particular laboratory. Students interested in bringing
applications of their choice should be familiar with the example circuits already
given in themanual.
13. The details of the experiment should be well documented.
14. Students have to do the experiment using specified software in the first two hours
and simulate, analyze and interpret the results in the next two hours.
15. Program should be developed according to the given criteria. They should not be
simply downloaded from the web.
16. Codes should be with comments.
17. All simulations should be saved in the names of students.
Evaluation:
● Marks will be awarded based on preparedness, way of conducting
experiment, observation, calculations, results, basic understanding and
answering for pre lab and post lab questions.
● Marks will be reduced for repetition / re-do, delay in completing the
observation notebook.
● Each experiment will be evaluated for a maximum of 100 marks.
● A mini project based on concepts learned during lab sessions will be
evaluated for 100 marks.
● A model examination conducted at the end of the semester will be
evaluated for 100marks.
● For laboratory GPA calculation 50% weightage will be given for total
marks obtained from all experiments,10% for mini project evaluation and
40% for model examination.
K.S.RANGASAMY COLLEGE OF TECHNOLOGY
(Autonomous Institution)
TIRUCHENGODE – 637215
CERTIFICATE
Register Number:
Certified that this is the Bonafide record of work done by

Selvan/Selvi ___________________________ of the third Semester
B.E - Electronics and Communication Engineering branch during the
academic year ___________ in the ANALOG AND DIGITAL
ELECTRONICS LABORATORY
Staffin-charge Head of the Department

Submitted for the UniversityPractical
Examination on ______________
InternalExaminer External Faculty

50 EC 5P2–CM0S DESIGN LABORATORY
V - Semester B.E- Electronics and Communication Engineering
LIST OF EXPERIMENTS
1. Verify the functionality of digital logic circuits using test bench.
2. Application circuit model by Finite State Machine (FSM).
Compare pre synthesis and post synthesis report by using scripting language (Perl/TCL),
implement by FPGA for experiments 1 & 2
3. DC and transient characteristics of static and dynamic CMOS circuits.
4. Layout diagram for above circuits .
Analyse the power, area and delay for experiments 3 & 4 by performing pre layout and post
layout simulations.
5. Digital circuit logic using System Verilog (SV).
6. Adder and multiplier logic using arithmetic building blocks by Verilog HDL.
7. Design a protocol (APB/SPI/UART/I2C) using Verilog/System Verilog and verify using UVM
methodology.
CONTENTS
Ex. Page
No. Date Name of the Experiments No. Marks Sign.
Repetitions
Ex. Page
Date Name of the Experiments Marks Sign.
No. No.
Content beyond syllabus (Additional experiments)

Ex. Page
Date Name of the Experiments Marks Sign.
No. No.

ADE Lab front page B section

Uploaded by

Copyright:

Available Formats

ADE Lab front page B section

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ADE Lab front page B section

Uploaded by

Copyright:

Available Formats

.

K.S.RANGASAMY COLLEGE OF TECHNOLOGY

LAB MANUAL CUM

50 EC 5P2–CMOS DESIGN LABORATORY

Department of Electronics and Communication Engineering

Certified that this is the Bonafide record of work done by

Staffin-charge Head of the Department

InternalExaminer External Faculty

1. Verify the functionality of digital logic circuits using test bench.

2. Application circuit model by Finite State Machine (FSM).

implement by FPGA for experiments 1 & 2

3. DC and transient characteristics of static and dynamic CMOS circuits.

4. Layout diagram for above circuits .

5. Digital circuit logic using System Verilog (SV).

Content beyond syllabus (Additional experiments)

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.