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ACHARIYA

COLLEGE OF ENGINEERING TECHNOLOGY


(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE

MODEL EXAM
ACADEMIC YEAR 2023-24
Subject Name: COA Time : 3 Hrs
Subject Code: ADPC407 Max. Marks : 75
Date of Exam: ..2024 YEAR / SEM : II/IV

Course Outcomes:
CO1- To understand the components of a basic computer.
CO2- To understand the key components of a CPU and how the instructions are executed.
CO3-To analyze the execution time taken in a pipelined processor.
CO4-To understand the need of memory hierarchy and efficiency achieved due to the use of cache.
CO5-To interpret how the data is stored and input-output is performed in computers.
Knowledge Level: K1-Knowledge, K2-Understand, K3-Apply, K4-Analyze, K5-Synthesis K6 -
Evaluate

Q.No Ms CO’s B.L


PART A (10 × 2 = 20 Marks)
Answer all the Questions
1. What are the roles of abstraction? 2 CO1 K1
2. Define Moore’s law 2 CO1 K1
3. What is CISC. 2 CO2 K1
4. Define Instruction Set 2 CO2 K2
5. List Limitation of ILP. 2 CO3 K1
6. What is pipelining 2 CO3 K1
7. Define SRAM 2 CO4 K1
8. Define Writeback caches 2 CO4 K1
9. What is flash memory. 2 CO5 K1
10. Define DMA 2 CO5 K1

PART B (3× 10 = 30 Marks)

Answer all the Questions


11. Explain in detail about Von neumann Architecture 11 CO1 K1, K2

Or

12. Describe basic functional units of computer 11 CO1 K2

13. Explain in detail about Instruction set 11 CO2 K2

Or
ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE

14. Describe in detail about RISC. 11 CO2 K2

15. Explain in detail about Amdhal’s law. 11 CO3 K2

Or

16. Describe in detail about pipelining. 11 CO3 K2

17. Explain Cache mechanism & size 11 CO4 K2

Or

18. Describe Cache Replacement policies 11 CO4 K2

19. Describe Interrupt Driven I/O 11 CO5 K2

Or

20. Describe DMA in detail 10 CO5 K2


ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE
MODAL EXAM
ACADEMIC YEAR 2023-24
Subject Name: COA Time : 3 Hrs
Subject Code: ADPC407 Max. Marks : 75
Date of Exam: ..2024 YEAR / SEM : II/IV

Course Outcomes:
CO1 To understand the components of a basic computer.

CO2 To understand the key components of a CPU and how the instructions are executed.
Knowledge Level: K1-Knowledge, K2-Understand, K3-Apply, K4-Analyze, K5-Synthesis K6 -
Evaluate

Q.No Ms CO’s B.L


PART A (10 × 2 = 20 Marks)
Answer all the Questions
1. What are the roles of abstraction? 2 CO1 K1
2. Define Moore’s law 2 CO1 K1
3. What is CISC. 2 CO2 K1
4. Define Instruction Set 2 CO2 K2
5. List Limitation of ILP. 2 CO3 K1
6. What is pipelining 2 CO3 K1
7. Define SRAM 2 CO4 K1
8. Define Writeback caches 2 CO4 K1
9. What is flash memory. 2 CO5 K1
10. Define DMA 2 CO5 K1

PART B (3× 10 = 30 Marks)

Answer ANY THREE Questions


11. Explain in detail about Von neumann Architecture 11 CO1 K1, K2

Or

12. Describe basic functional units of computer 11 CO1 K2

13. Explain in detail about Instruction set 11 CO2 K2

Or

14. Describe in detail about RISC. 11 CO2 K2


ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE

15. Explain in detail about Amdhal’s law. 11 CO3 K2


Or

16. Describe in detail about pipelining. 11 CO3 K2

17. Explain Cache mechanism & size 11 CO4 K2

Or

18. Describe Cache Replacement policies 11 CO4 K2

19. Describe Interrupt Driven I/O 11 CO5 K2

Or

20. Describe DMA in detail 10 CO5 K2


ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE

ANSWER KEY
PART A
1. Abstraction in computer science is used to simplify complex systems by breaking them down into smaller,
more manageable parts. It allows programmers to hide the complex details of the system, focusing on the
essential features instead.
2. The exponential increase in the number of transistors on integrated circuits over time is referred to as
Moore’s law. According to this, a chip transistor count tends to double every two years or so, resulting in
higher processing power and better performance.
3. The main idea is that a single instruction will do all loading, evaluating, and storing operations just like a
multiplication command will do stuff like loading data, evaluating, and storing it, hence it’s complex.
4. An instruction is a set of codes that the computer processor can understand. The code is usually in 1s and 0s, or
machine language. It contains instructions or tasks that control the movement of bits and bytes within the
processor.
5. Instructions with data dependencies cannot be executed in parallel, leading to potential stalls in the pipeline .
Branch Prediction Misprediction: Speculative execution relies on accurate branch prediction
6. Pipelining is a technique for breaking down a sequential process into various sub-operations and executing
each sub-operation in its own dedicated segment that runs in parallel with all other segments.
7. Static random-access memory (static RAM or SRAM) is a type of random-access memory (RAM) that uses
latching circuitry (flip-flop) to store each bit.
8. The data is updated only in the cache and updated into the memory at a later time. Data is updated in the
memory only when the cache line is ready to be replaced (cache line replacement is done using Belady’s
Anomaly, Least Recently Used Algorithm, FIFO, LIFO, and others depending on the application).
9. Flash memory is widely used to store data and code used in embedded systems. It is a non-volatile storage
medium, meaning that it can retain data without a power supply. Flash memory can be electrically erased and
reprogrammed and it erases data in units called blocks and rewrites data at the byte level
10. Direct Memory Access uses hardware for accessing the memory, that hardware is called a DMA Controller.
It has the work of transferring the data between Input Output devices and main memory with very less
interaction with the processor. The direct Memory Access Controller is a control unit, which has the work of
transferring data.
PART B

11. Von-Neumann computer architecture design was proposed in 1945.It was later known as Von-
Neumann architecture.
Historically there have been 2 types of Computers:
1. Fixed Program Computers – Their function is very specific and they couldn’t be
reprogrammed, e.g. Calculators.
2. Stored Program Computers – These can be programmed to carry out many different tasks,
applications are stored on them, hence the name.
ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE

Modern computers are based on a stored-program concept introduced by John Von Neumann. In this
stored-program concept, programs and data are stored in the same memory. This novel idea meant that a
computer built with this architecture would be much easier to reprogram.
12. Computer: A computer is a combination of hardware and software resources which integrate together and
provides various functionalities to the user. Hardware are the physical components of a computer like the
processor, memory devices, monitor, keyboard etc. while software is the set of programs or instructions that
are required by the hardware resources to function properly.
There are a few basic components that aids the working-cycle of a computer i.e. the Input- Process- Output
Cycle and these are called as the functional components of a computer. It needs certain input, processes that
input and produces the desired output. The input unit takes the input, the central processing unit does the
processing of data and the output unit produces the output. The memory unit holds the data and instructions
during the processing.
ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE

13. An instruction is a set of codes that the computer processor can understand. The code is usually in 1s and 0s, or
machine language. It contains instructions or tasks that control the movement of bits and bytes within the
processor.
Example of some instruction sets −
 ADD − Add two numbers together.
 JUMP − Jump to designated RAM address.
 LOAD − Load information from RAM to the CPU.
14. Reduced Instruction set Computer (RISC)
A number of computer designers recommended that computers use fewer instructions with simple constructs so that they
can be executed much faster within the CPU without having to use memory as often. This type of computer is called a
Reduced Instruction Set Computer.
The concept of RISC involves an attempt to reduce execution time by simplifying the instruction set of computers.
Characteristics of RISC
The characteristics of RISC are as follows −
 Relatively few instructions.
 Relatively few addressing modes.
 Memory access limited to load and store instructions.
 All operations done within the register of the CPU.
 Single-cycle instruction execution.
 Fixed length, easily decoded instruction format.
 Hardwired rather than micro programmed control.
A characteristic of RISC processors’ ability is to execute one instruction per clock cycle. This is done by overlapping the
fetch, decode and execute phases of two or three instructions by using a procedure referred as pipelining.
15. It is a formula that gives the theoretical speedup in latency of the execution of a task at a fixed workload that
can be expected of a system whose resources are improved. In other words, it is a formula used to find the
maximum improvement possible by just improving a particular part of a system.
ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE

The formula for Amdahl’s law is:


S = 1 / (1 – P + (P / N))
Where:
S is the speedup of the system
P is the proportion of the system that can be improved
N is the number of processors in the system
16. Pipeline hazards are conditions that can occur in a pipelined machine that impede the execution of a subsequent
instruction in a particular cycle for a variety of reasons.
Types of Pipeline Hazards in Computer Architecture
The three different types of hazards in computer architecture are:
1. Structural
2. Data
3. Control
17. Cache Memory is a special very high-speed memory. The cache is a smaller and faster memory that stores copies
of the data from frequently used main memory locations. There are various different independent caches in a CPU,
which store instructions and data. The most important use of cache memory is that it is used to reduce the average
time to access data from the main memory.
Characteristics of Cache Memory
 Cache memory is an extremely fast memory type that acts as a buffer between RAM and the CPU.
 Cache Memory holds frequently requested data and instructions so that they are immediately available
to the CPU when needed.
 Cache memory is costlier than main memory or disk memory but more economical than CPU registers.
 Cache Memory is used to speed up and synchronize with a high-speed CPU.

Cache Memory
Levels of Memory
 Level 1 or Register: It is a type of memory in which data is stored and accepted that are immediately
stored in the CPU. The most commonly used register is Accumulator, Program counter, Address
Register, etc.
 Level 2 or Cache memory: It is the fastest memory that has faster access time where data is
temporarily stored for faster access.
 Level 3 or Main Memory: It is the memory on which the computer works currently. It is small in size
and once power is off data no longer stays in this memory.
 Level 4 or Secondary Memory: It is external memory that is not as fast as the main memory but data
stays permanently in this memory.
18. In the direct-mapped cache, the position of each block is predetermined hence no replacement policy exists.
 In fully associative and set-associative cache there exist policies.
ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE
 When a new block is brought into the cache and all the position that it many occurs are full, and then the
controller needs to decide which of the old blocks it can overwrite
First in First out policy
 The block which has entered first in the main be replaced first.
 This can lead to a problem known as "Belady's Anamoly", it starts that if we increase the no. of lines in cache
memory the cache miss will increase.

LRU (least recently used)


 The page which was not used for the largest period of time in the past will get reported first.
 We can think of this strategy as the optimal cache- replacement algorithm looking backward in time, rather
than forward.
 LRU is much better than FIFO replacement.

Optimal Approach
 The page which will not be used for the largest period of time in future reference will be replaced first.
 The optimal algorithm will provide the best performance but this is difficult to implement as it requires the
future knowledge of pages which is not possible.
 It is used as a benchmark for the cache replacement algorithm.
 It is mainly used for comparison studies.

19. In interrupt-driven I/O, The I/O module will then interrupt the processor to request service when it is ready to
exchange data with the processor. The processor then executes the data transfer, as before, and resumes its former
processing.
 This frees up the processor to do other work, doesn’t need to constantly check on I/O module
 The process will be BLOCKED, processor can execute other processes
ACHARIYA
COLLEGE OF ENGINEERING TECHNOLOGY
(Approved by AICTE New Delhi & Affiliated to Pondicherry University)
An ISO 9001 : 2008 Certified Institution
DEPARTMENT OF ARTIFICIAL INTELLIGENCE & DATA SCIENCE

20. Direct Memory Access uses hardware for accessing the memory, that hardware is called a DMA Controller. It has
the work of transferring the data between Input Output devices and main memory with very less interaction with the
processor. The direct Memory Access Controller is a control unit, which has the work of transferring data.
DMA Controller Diagram in Computer Architecture
DMA Controller is a type of control unit that works as an interface for the data bus and the I/O Devices. As
mentioned, DMA Controller has the work of transferring the data without the intervention of the processors,
processors can control the data transfer. DMA Controller also contains an address unit, which generates the address
and selects an I/O device for the transfer of data. Here we are showing the block diagram of the DMA Controller.

 Single-Ended DMA
 Dual-Ended DMA
 Arbitrated-Ended DMA
 Interleaved DMA

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