EXPERIMENT-2

INTEGRATOR AND DIFFERENTIATOR

2.1 OBJECTIVE

1. Design an integrator for a frequency of 500 Hz, given R=1KΩ, C=0.1 µF and Rf =
1MΩ. Conduct the experiment and plot integrated output waveforms for various
input waveforms and analyse.
2. Design a differentiator for a frequency of 500 Hz, given R=1KΩ, and C=0.1µf and
R1 = 470Ω. Conduct the experiment and plot differentiated output waveforms for
various input waveforms and analyse.

2.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

Refer data sheet in
1 IC 741 1
appendix
2 Cathode Ray Oscilloscope (0 – 20MHz) 1
1K Ω
11
1M Ω
3 Resistors 1
10 K Ω
1
470 Ω
4 Capacitors 0.1µf 2

5 Dual Regulated power supply (0 -30V), 1A 1

6 Function Generator (0-2) MHz 1

2.3 THEORY
In this laboratory experiment, several basic ways are learned in which an op-amp can be
connected using negative feedback to stabilize the gain and increase the frequency response. The
extremely high open-loop gain of an op-amp creates an unstable situation because a small noise
voltage on the input can be amplified to a point where the amplifier in driven out of its linear
region. Also unwanted oscillations can occur. In addition, the open-loop gain parameter of an op-
amp can vary greatly from one device to the next. Negative feedback takes a portion of output and

31
applies it back out of phase with the input, creating an effective reduction in gain. This closed-
loop gain is usually much less than the open-loop gain and independent of it.

2.3.1 Integrator

An op-amp integrator simulates mathematical integration which is basically a summing

process that determines the total area under the curve of a function ie., the integrator does
integration of the input voltage waveform. Here the input element is resistor and the feedback
element is capacitor as shown in Fig.2.1.

Fig.2.1 Basic op-amp integrator

The output voltage is given by
−1 𝑡
𝑉0 = ∫ 𝑉𝑠 𝑑𝑡 + 𝑉𝑐 (𝑡 = 0)
𝑅𝐶 0

Where VC (t=0) is the initial voltage of the capacitor. For proper integration, R C has to be much
greater than the time period of the input signal.

It can be seen that the gain of the integrator decreases with the increasing frequency so,
the integrator circuit does not have any high frequency problem unlike a differentiator circuit.
However, at low frequencies such as at dc, the gain becomes infinite. Hence the op-amp saturates
(ie., the capacitor is fully charged and it behaves like an open circuit). A practical integrator circuit
is shown in Fig. 2.2.

32
 Fig. 2.2 Practical op-amp integrator
2.3.2 Differentiator
An op-amp differentiator simulates mathematical differentiation, which is a process of
determining the instantaneous rate of change of a function. Differentiator performs the reverse of
integration function. The output waveform is derivative of the input waveform. Here, the input
element is a capacitor and the feedback element is a resistor. An ideal differentiation is shown in
Fig. 2.3.

Fig.2.3 Basic op-amp differentiator

The output voltage is given by
𝑑𝑉𝑠
VO =−RC
𝑑𝑡
For proper differentiation, RC has to be much smaller than the time period of the input signal. It
can be seen that at high frequencies a differentiator may become unstable and break into
oscillation. Also, the input impedance of the differentiator decreases with increase in frequency,
thereby making the circuit sensitive to high frequency noise. So, in order to limit the gain of the
differentiator at high frequencies, the input capacitor is connected in series with a resistance R 1
and hence avoiding high frequency noise and stability problems. A practical differentiator circuit
is shown in Fig.2.4.

33
 Fig.2.4 Practical op-amp differentiator

2.4 PRE LAB QUESTIONS

1. Op-amp is used mostly as an integrator than a differentiator. Why?
2. Why open-loop op-amp configurations are not used in linear applications?
3. Determine the output voltage of each amplifier in the Figures given below.

2.5 EXPERIMENT
(1) Integrator

1.1 Assemble an integrator circuit with R=1KΩ and C=0.1µf. Connect Rf of value

1MΩ across the capacitor.

1.2 Feed +1V, 500Hz square wave input.
1.3 Observe the input and output voltages on a CRO.

34
 1.4 Determine the gain of the circuit and tabulate the readings in table. Model
waveform is shown.
1.5 Plot the input and output voltages on the same scale on a linear graph sheet.

(2) Differentiator

2.1 Assemble a differentiator circuit with R=1KΩ and C=0.1µf. Connect a resistor R1
of value 470Ω between the source and the capacitor.

2.2 Feed +1V, 500Hz square wave input.

2.3 Observe the input and output voltages on a CRO.
2.4 Determine the gain of the circuit and tabulate the readings. Model waveform is
shown below.
2.5 Plot the input and output voltages on the same scale on a linear graph sheet.

35
 op-amp Input signal Output signal
configuration /
Amplitude Frequency Amplitude Frequency
circuit
Integrator
Differentiator

2.6 POST LAB QUESTIONS

1. What are the limitations of an ordinary op-amp differentiator? How that will be
eliminated in practical differentiator?
2. Determine the input and output impedances of each amplifier.
3. (a) What is the normal output voltage in below circuits?
(b)What is the output voltage if Resistance connected to 0.2V is opened?
(c)What happens if the feedback resistance is opened?

Result:

36
 EXPERIMENT-3
PRECISION RECTIFIERS
3.1 OBJECTIVE
To study the operation of active diode circuits (precisions circuits) using op-amps,
such as half wave rectifier and full wave rectifier.

3.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

Refer data sheet in

1 IC 741 1
appendix

2 Cathode Ray Oscilloscope (0 – 20MHz) 1

3 Resistors 10 K Ω 6

4 Semiconductor(Diode) 1N4002 2

5 Dual Regulated power supply (0 -30V), 1A 1

6 Function Generator (0-2) MHz 1

3.3 THEORY
The major limitation of ordinary diodes is that it cannot rectify voltage below 0.6v, the
cut in voltage of the diode. The precision rectifier, which is also known as a super diode, is a
configuration obtained with an operational amplifier in order to have a circuit behaving like an
ideal diode and rectifier. It can be useful for high-precision signal processing.

3.3.1 Active Half Wave Rectifier

Op-amps can enhance the performance of diode circuits. For one thing, the op-amp can
eliminate the effect of diode offset voltage, allowing us to rectify, peak-detect, clip, and clamp
low-level signals (those with amplitudes smaller than the offset voltage). And because of their
buffering action op-amps can eliminate the effects of source and load on diode circuits. Circuits
that combine op-amps and diodes are called active diode circuits. Fig. 3.1(a) shows an active
HWR, with gain.

37
 Fig3.1(a) Active HWR, (b) input and output waveforms
When the input signal goes positive, the op-amp output goes positive and turns on the diode. The
circuit then acts as a conventional non-inverting amplifier, and the positive half-cycle appears
across the load resistor. On the other hand, when the input goes negative, the op-amp output goes
negative and turns off the diode. Since the diode is open, no voltage appears across the load
resistor. This is why the final output is almost a perfect half-wave signal.

The high gain of the op-amp virtually eliminates the effect of offset voltage. For
instance, if the offset voltage equals 0.7V and open-loop gain is 100,000, the input that just turns
on the diode is
0.7𝑣
𝑉𝑖𝑛 >
100000
i.e.
𝑉𝑖𝑛 > 7µ𝑣

When the input is greater than 7µV, the diode turns on and the circuit acts like a voltage follower.
The effect is equivalent to reducing the offset voltage by a factor of gain A.

3.3.2 Design Constraints

The output signal is limited by the IC's power sources: the output signal cannot be greater
than +15V

38
3.3.3 Full Wave Rectifier
A Full Wave Rectifier is a circuit as shown in Fig. 3.2 (a), which converts an ac voltage
into a pulsating dc voltage using both half cycles of the applied ac voltage. It uses two diodes
of which one conducts during one half cycle while the other conducts during the other half
cycle of the applied ac voltage.

During the positive half cycle of the input voltage, diode D1 becomes forward biased
and D2 becomes reverse biased. Hence D1 conducts and D2 remains OFF. The load current
flows through D1 and the output voltage will be equal to the input voltage. During the negative
half cycle of the input voltage, diode D1 becomes reverse biased and D2 becomes forward
biased. Hence D1 remains OFF and D2 conducts. The load current flows through D2 and the
voltage at the output will be equal to the input voltage.

Input waveform

Output waveform:

39
 Fig.3.2 (a) Full wave rectifier, (b) input and output waveforms

3.4 PRE-LAB QUESTIONS

1. What is a precision diode? How a precision diode is different from ordinary diode?
2. Give some applications of precision diode.

3. For a precision HWR, draw the output waveform if Vin is a 300mV peak sine wave

at 1 KHz.
4. Draw the circuit of precision peak detector.
5. Draw the transfer characteristics of practical ordinary rectifier circuit and compare
it with that of a precision rectifier.
3.5 Experiment
3.5.1. Half Wave Rectifier
1. Connect the circuit as shown in the Fig. 3.1. Consider all resistors value 10kΩ.
Use 1N4002 diodes. Assemble the circuit.

2. Feed sinusoidal input of amplitude 200mVPP and frequency 100Hz. Using a CRO

to observe the input and output voltages simultaneously. Determine the amplitude
and frequency of the output voltage.
3. Plot the input and output voltages on the same scale.

Particulars Amplitude Time period Frequency

Input Voltage
Output Voltage

3.5.2 Full Wave Rectifier

1. Connect the circuit as shown in the Fig. 3.2. (a). Consider all resistors value 10kΩ.
Use 1N4002 diodes. Assemble the circuit.

2. Feed sinusoidal input of amplitude 200mVPP and frequency 100Hz.

3. Using a CRO observe the input and output voltages simultaneously. Determine the
amplitude and frequency of the output voltage.

40
 4. Plot the input and output voltages on the same scale.
Particulars Amplitude Time period Frequency
Input Voltage
Output Voltage

3.6 POST LAB QUESTIONS

1. If the diode is reversed in half wave rectifier, what would the output voltage be?
2. Draw the equivalent circuit of a full wave rectifier for input voltage less than zero
volts.
3. For the circuit shown below, find the output voltage

4. For the precision rectifier shown below, draw the circuit to reverse the polarity of Vout

Result:

41
 EXPERIMENT-4
COMPARATOR (BASIC COMPARATOR & SCHMITT
TRIGGER)

4.1 OBJECTIVE:
1. Design the comparator for a frequency of 1 KHz sine wave with 5 Vpp at the non-
inverting input terminal and apply 1V dc voltage as reference voltage at the
inverting terminal of IC741

2. Design a Schmitt Trigger and conduct an experiment to obtain VUTP and VLTP for
various values of R1 and R2.

4.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet 1
2 Cathode Ray Oscilloscope (0 – 20MHz) 1
10 kΩ 2
3 Resistors
56 K Ω 1
4 Dual Regulated power supply (0 -30V), 1A 1
5 Function Generator (0-2) MHz 1

4.3 THEORY
4.3.1 Comparator

A Comparator is a non-linear signal processor. It is an open loop mode application of op-

amp operated in saturation mode. Comparator compares a signal voltage at one input with a
reference voltage at the other input. Here the op-amp is operated in open loop mode and hence the
output is ±Vsat. It is basically classified as inverting and non-inverting comparator. In a non-
inverting comparator Vin is given to +ve terminal and Vref to –ve terminal. When Vin < Vref, the
output is –Vsat and when Vin > Vref, the output is +Vsat. In an inverting comparator input is given
to the inverting terminal and reference voltage is given to the non-inverting terminal. The output

42
of the inverting comparator is the inverse of the output of non-inverting comparator. The
comparator can be used as a zero-crossing detector, window detector, time marker generator and
phase meter.

.
Fig. 4.1 Comparator

Fig. 4.2 Comparator Input & Output Waveforms

43
4.3.2 Schmitt Trigger
Circuit shows in Fig.4.3 is an inverting comparator with positive feedback. This circuit
converts an irregular shaped waveform to square wave or pulse. This circuit is known as Schmitt
trigger or Regenerative comparator or Squaring circuit. The input voltage Vin triggers (changes the
state of ) the output Vo every time it exceeds certain voltage levels called Upper threshold voltage,
VUT and Lower threshold voltage, VLT. The hysteresis width is the difference between these two
threshold voltages i.e. VUT – VLT. These threshold voltages are calculated as follows.

VUTP =
R2
R1 +R 2
 
VSat 
when Vo = +Vsat

VLTP =
R2
R1 +R 2
 
VSat 
when Vo= -Vsat

The output of Schmitt trigger is a square wave when the input is sine wave or triangular wave,
where as if the input is a saw tooth wave then the output is a pulse signal.

Fig. 4.3 Schmitt trigger

Design Equations:

VUTP =
R2
R1 +R 2
 
VSat 

44
VLTP =
R2
R1 +R 2
 
VSat 

VHyst =VUTP -VLTP =

R2
R1 +R 2
 
VSat 
 VSat 

Fig.4.4 Schmitt trigger input and output Waveforms

4.4 PRE LAB QUESTION

4.4.1 Comparator
1. Draw the transfer characteristics of open loop op-amp.
2. How many basic input parameters are required for a comparator?
3. How is Vo related to Vin and Vref?
4. Why this circuit is called a non-inverting comparator?

4.4.2 Schmitt Trigger

1. Which type of comparator is called Schmitt trigger using IC741?
2. What is the output wave of Schmitt trigger if the input is sine wave?
3. What type of waveform is obtained when triangular or ramp waveforms are applied
to Schmitt trigger circuit?

45
4.5 EXPERIMENT
4.5.1 Comparator
1. Connect the components as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply 1 KHz sine wave with 5 Vpp at the non-inverting input terminal of IC741
using a function generator.
4. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.
5. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the
output terminals.
6. Observe the input sinusoidal signal at channel-1 and the corresponding output square
wave at channel-2 of CRO. Note down their amplitude and time period.
7. Overlap both the input and output waves and note down voltages at positions on sine
wave where the output changes its state. These voltages denote the Reference voltage.
8. Plot the output square wave corresponding to the sine input with Vref = 1V.

Observation:
Theoretical Reference voltage (From the circuit)
Practical Reference voltage (From output waveform)

4.5.2 Schmitt trigger

1. Connect the components as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply 5 Vpp and 1KHz input sine wave using function generator.
4. Connect the channel - 1 of CRO at the input terminals and Channel-2 at the output
terminals.
5. Observe the output square waveform corresponding to input sinusoidal signal.
6. Overlap both the input and output waves and note down voltages at positions on
sine wave where output changes its state. These voltages denote the Upper
threshold voltage and the Lower threshold voltage.

46
 7. Verify that these practical threshold voltages are almost same as the theoretical
threshold voltages calculated using formulas.
8. Sketch the waveforms by noting down the amplitude and the time period of the
input Vin and the output Vo.

Observation:
Theoretical Values Practical Value
Sl
no. R1 R2 VUTP =
R2
R1 +R 2
 VSat  VLTP =
R2
R1 +R 2
 VSat  VUTP VLTP

1
2
3

4.6 POST LAB QUESTION

4.6.1 Comparator
1. Draw the circuit diagram of a non-inverting and inverting comparator.
2. What is the role of resistors R1 and R2 in the comparator circuit?
3. For the comparator shown below, determine the transfer curves if an ideal op-amp
with VZ1= VZ2=9v.

4. Draw the circuit of comparator with clamp diodes. Explain the purpose of clamp
diodes in comparator circuit.
5. List the applications of comparator.

47
4.6.2 Schmitt Triger
1. What is the Hysteresis width?
2. What is the minimum amplitude of the input sine wave in the case of Schmitt
trigger using IC741?
3. Draw the transfer characteristics of the circuit given below assuming ideal diodes

Result:

48
 EXPERIMENT-5
WAVE SHAPING CIRCUIT USING OP-AMP: CLIPPER AND
CLAMPER
5.1 OBJECTIVE
To study the operation of wave shaping circuits (clipper and clamper) using op-amps.

5.2 HARDWARE REQUIRED

1 IC 741 Refer data sheet in appendix 1

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

3 Resistors 2.2 K Ω, 4.7K Ω, 10K Ω 10KPOT 4
4 Capacitor 0.1µF 1
5 Semiconductor (Diode) 1N4002 1
6 Dual Regulated power supply (0 -30V), 1A 1
7 Function Generator (0-2) MHz 1

5.3 THEORY
5.3.1 Active Clipper

Clipper is a circuit that is used to clip off (remove) a certain portion of the input signal
to obtain a desired output wave shape. In op-amp clipper circuits, a rectified diode may be used
to clip off certain parts of the input signal. Fig. 5.1 (a) shows an active positive clipper circuit
that removes positive parts of the input signal. The clipping level is determined by the reference

49
voltage.

Fig 5.1 (a) Active clipper

(b) (c)

Fig 5.1 (b) input & output waveforms with +Vref, (c) input & output waveforms
with -Vref

50
With the wiper all the way to the left, Vref is o and the non-inverting input is grounded. When Vin

goes positive, the error voltage drives the op-amp output negative and turns on the diode. This

means the final output VO is 0 (same as Vref) for any positive value of Vin.

When Vin goes negative, the op-amp output is positive, which turns off the diode

and opens the loop. When this happens, the final output VO is free to follow the negative half cycle
of the input voltage. This is why the negative half cycle appears at the output. To change the
clipping level, Vref should be adjusted.

5.3.2 Active clamper

In clamper circuits, a predetermined dc level is added to the input voltage. In other words,
the output is clamped to a desired dc level. If the clamped dc level is positive, the clamper is
called a positive clamper. On the other hand, if the clamped dc level is negative, it is called a
negative clamper. The other equivalent terms for clamper are dc inserter or dc restorer.
A clamper circuit with a variable dc level is shown in Fig.5.2. (a). Here the input wave

form is clamped at +Vref and hence the circuit is called a positive clamper.

R1=4.7k, R2=10k, C = 0.1µF

Fig 5.2 (a) Peak clamper circuit

The output voltage of the clamper is a net result of ac and dc input voltages applied to the
inverting and non-inverting input terminals respectively. Therefore, to understand the circuit

51
operation, each input must be considered separately. First, consider Vref at the non-inverting

input. Since this voltage is positive, Vo is also positive, which forward biases diode D1. This closes
the feedback loop and the op-amp operates as a voltage follower. This is possible because C1 is an
open circuit for dc voltage. Therefore Vo = Vref. As for as voltage Vin at the

Inverting input is concerned during its negative half-cycle D1 conducts, charging C1 to the

negative peak value of the VP. However, during the positive half-cycle of VIN diode D1 is reverse

biased and hence the voltage VP across the capacitor acquired during the negative half-cycle is

retained. Since this voltage VP is in series with the positive peak voltage VP, the output peak

voltage VO=2VP. Thus, the net output is Vref +2VP. For precision clamping C1Rd<<T/2, where Rd

is the forward resistance of the diode D1 (100Ω typically) and T is the time period of VIN. The

input and output wave forms are shown in Fig.5.2. (b).

(i) (ii)

52
 (iii)

Fig 5.2(b) Input and output waveforms (i) with Vref=0V, (ii) with +Vref, (iii) with -Vref

Resistor R is used to protect the op-amp against excessive discharge currents from capacitor C1
especially when the dc supply voltages are switched off. Negative clamping at a negative voltage
is accomplished by reversing diode D1 and using the negative reference voltage

– Vref.

5.4 PRE LAB QUESTIONS

1. Find the output waveform, when Vin < Vref

53
 2. Determine the output waveform for a clamper with input =4Vp sine wave and Vref=1V.
3. Why clamper is called a DC restorer?

4. What are the applications of clippers and clampers?

5. Which factor determines clipping level in a clipper?

5.5 EXPERIMENT

5.5.1 Active Clipper

1. Connect all the components as shown in the circuit diagram.

2. Apply sinusoidal input of amplitude 3v and frequency 1Khz.

3. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.

4. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the
output terminals.
5. Observe the input sinusoidal signal at channel-1 and the corresponding clipped
output wave at channel-2 of CRO. Note down their amplitude and time period of
input waveform.
6. Overlap both the input and output waves and note down voltages at positions on
sine wave where the output changes its state. These voltages denote the Reference
voltage.
7. Plot both the input and the output wave form.
Observation Clipper

5.5.2 Active clamper

1. Connect the components/equipment clamping level at zero as shown in fig.5 (a). Note

that Vref = 0V. Consider C1 = 0.1µF, R = 4.7 KΩ and RL = 10 KΩ . Use 1N4002

diode. Feed 5VPP, 10 KHz sinusoidal inputs.

54
 2. Switch ON the power supply.

3. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.

4. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the
output terminals.
5. Observe the input sinusoidal signal at channel-1 and the corresponding output wave at
channel-2 of CRO. Note down their amplitude and time period.
6. Overlap both the input and output waves and note down voltages at positions on sine
wave where the output changes its state. These voltages denote the Reference voltage.
7. Plot both the input and the output wave form.

Observation Clamper

5.6 POST LAB QUESTIONS

1. For a given sinusoidal input voltage, the voltage waveform at point P of the clamper
circuit shown in figure will be

55
 A) B)

C) D)

2. Compare clipper with clamping circuit.

3. Which elements are used in linear and non-linear wave shaping circuits?
4. Draw the output waveform for the following circuit

5. Sketch the negative clamper using opamp.

Result:

56
 EXPERIMENT-6
SINE WAVE GENERATOR USING OP-AMP

6.1 OBJECTIVE
Design a sine wave oscillator using operational amplifier
1. RC phase shift oscillator
2. Wien bridge oscillator

6.2 HARDWARE REQUIRED

S.No Equipment/Component Specifications/Value Quantity

name
Refer data sheet in
1 IC 741 1
appendix
2 Cathode Ray Oscilloscope (0 – 20MHz) 1

1.5K Ω
4
15K Ω
2
1M Ω
1
4.7K Ω
1
18K Ω
1
10K Ω
3 Resistors 1

0.1µf 3
4 Capacitors
0.01µf 2

5 Regulated power supply 15 V 1

6.3 THEORY
6.3.1 RC phase shift oscillator

The feedback network consists of three identical RC sections. Each section produces a
phase shift of 60o . Therefore, the net phase shift of the feedback is 180 o
the amplifier stage
introduces a phase shift of 180 o. Hence, the total phase shift between the input and output is 360
o
or 0 o. When the circuit is energized, by switching on the supply, the circuit starts oscillating. The

57
oscillations will be maintained if the loop gain is at least equal to unity.
Feedback fraction of the RC phase shift network is β=1/29.
The frequency of oscillation is f0=1/2 πRC√6.

Circuit diagram

C=0.1µF, R=1.5KΩ, R1=15KΩ, RF=1MΩ pot

Design:
f0=1/2 πRC√6
Rf ≥ 29R1
R1 ≥ 10R
Choose C =0.1µF
f0 = 500 Hz
1
𝑅 = 2𝜋𝑓 𝐶√6
0

1
𝑅= = 1.3𝐾Ω
2 × 3.14 × 500 × 0.1 × 10−6 × √6

Choose R = 1.5KΩ
R1≥ 15KΩ (to prevent loading)
R1 = 10R = 15KΩ

Rf = 29R1=29x15KΩ=435KΩ (Use 1MΩpot)

58
6.3.2 Wien Bridge Oscillator
It is commonly used in audio frequency oscillator. The feedback signal is connected to
non-inverting the input terminal, so that the amplifier is working as a non-inverting amplifier. The
Wien bridge circuit is connected between amplifier input terminal and output terminal. The bridge
has a series RC network, in one arm and a parallel RC network in the adjoining arm. In the
remaining two arms of the bridge, resistor R1 and Rf are connected. The phase angle criterion for
oscillation is that the total phase shift around the circuit must be zero. This condition occurs when
bridge is balanced. At resonance, frequency of oscillation is exactly the resonance frequency of
balanced Wien bridge and is given by f0 = 1/ (2πRC).

Design
Given, fo = 1KHz; Assume C = 0.01µF

fo = 1/ (2π RC)
R = 15KΩ
Rf = 2R = 20KΩ (approximately 22.7 KΩ)

Design Constraints

 The loading effect of the amplifier on the feedback network has an effect on the frequency
of oscillations and can cause the oscillator frequency to be up to 25% higher than
calculated. Then the feedback network should be driven from a high impedance output
source and fed into a low impedance load such as a common emitter transistor amplifier
but better still is to use an Operational Amplifier as it satisfies these conditions perfectly.

59
 The voltage gain of the Wien bridge oscillator circuit must be equal to or greater than
three “Gain = 3″ for oscillations to start.
 Due to the open-loop gain limitations of operational amplifiers, frequencies above
1MHz are unachievable without the use of special high frequency op-amps.

6.4 PRE LAB QUESTIONS

1. In an op-amp based RC phase shift oscillator, what is the minimum gain that should be
maintained. Why?
2. State Barkhausen criterion for oscillation
3. Write the formula to calculate frequency of oscillation for RC &Wien bridge oscillator
4. What are the applications of oscillators?
5. In RC phase shift oscillator using, the value of capacitor is 0.01µF and the frequency of
oscillation is 35 KHz the voltage gain of the amplifier should be 30. Calculate the value
of R of RC feedback Network.

6.5 EXPERIMENT

1. Connect all the components as shown in the circuit diagram.

2. Observe the output sinusoidal signal in CRO and note down the
amplitude and time period of output waveform.
3. Plot the output wave form.
Observation
Oscillator Amplitude(V) Time period (ms) Frequency (Hz) Frequency (Hz)
(Design) (Observed)
RC Phase Shift
Wein Bridge

6.6 POST LAB QUESTIONS

1. What are the merits and demerits of Wien bridge oscillator?

2. Why do we need three RC networks for a phase shift oscillator?
3. Explain the main difference between an amplifier and an oscillator.
4. In as RC phase shift oscillator, if R1 = R2 = R3 = 200kΩ and C1 = C2 = C3 = 100pF.
Find the frequency of oscillation.
5. Mention the advantages and disadvantages of negative feedback.

Result:

60
 EXPERIMENT-7
SQUARE WAVE GENERATOR USING OP-AMP

7.1 OBJECTIVE

Design a square wave generator using operational amplifier.

7.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in appendix 1
2 Cathode Ray Oscilloscope (0 – 20MHz) 1
10k 2
3 Resistors
8.2k 1
5 Capacitors 0.1µf 1

7.3 SQUARE WAVE GENERATOR

The square wave generator circuit is forced to operate in the saturated region. That is, the
output of the Op-Amp is forced to swing between positive saturation (+Vsat) and negative
saturation (-Vsat), resulting in the square wave output. This square wave generator is also called
free running or astable multivibrator.
●

R2/[R1+R2]Vout = βVout
Rf=10k R1=10k R2=8.2k C=0.1µf

61
 A fraction of the output (βV◦) is feedback to the input non-inverting terminal. Thus the
Vref is βV◦ and may take values as + βVsat or – βVsat. The output is also feedback to the negative
input terminal after integrating by means of a low pass RC combination. Whenever the input at
the negative terminal exceeds Vref switching takes place resulting in a square wave output. Time
period of square wave is given as

for R1 = 1.16 R2, it can be seen that T = 2RC.

T = 1.6 ms
V◦ = 24 V
Vsat = 12V; βVsat = 4v

4𝑉 4
𝛽= = = 0.333
𝑉𝑠𝑎𝑡 12

7.4 PRE LAB QUESTIONS

1. Where IC oscillators are used?
2. Explain the operation of square wave generator with respect to voltage across
capacitor and output waveform.
3. Why zener diode is used at the output terminal of square generator?
A. To reduce both output and capacitor voltage swing
B. To reduce output voltage swing
C. To reduce input voltage swing
D. To reduce capacitor voltage swing
4. What could be the possible output waveform for a free running multivibrator
whose op-amp has a supply voltage of ±5V operating at 5KHz?

7.5 EXPERIMENT
1. Connect the circuit as shown in the figure with the designed values.
2. Switch on the power supply and observe the waveform.
3. Note down the amplitude and time period.
4. Plot the waveforms on a graph sheet.

62
Observation

Theoretical Output Practical Output

TOTAL TIME ` TOTAL TIME
TON TON
TOFF TOFF
AMPLITUDE of AMPLITUDE of
Close to VCC
Square wave Square wave
Charg& Discharging Charg& Discharging
Of Capcitor by βVsat Of Capcitor by
measuring Amplitude measuring Amplitude

7.6 POST LAB QUESTIONS

1. Explain the main difference between an amplifier and an oscillator.
2. Calculate the frequency of oscillation of square wave generator if R2=10kΩ,
R1=11.kΩ, Rf=100kΩ, C=0.01μf.
3. Given that the feedback factor is 0.6, find the time period of the square wave
generator with R=10KΩ and C=1µF.
4. A square wave oscillator has fo = 1KHz. Assume the resistor value to be 10KΩ and
find the capacitor value?

Result:

63
 EXPERIMENT-8
DESIGN OF MONOSTABLE AND ASTABLE MULTIVIBRATOR USING
IC555 TIMER
8.1 OBJECTIVE
1. Design a Monostable multivibrator for an ON- time of 11secs, with capacitor value
of 1 µF. Conduct the experiment and plot appropriate graphs.
2. Design an Astable multivibrator for a frequency of 1KHz with 60% duty cycle
using 555 timer.

8.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

Refer data sheet in
1 IC 555 Timer 1
appendix
2 Cathode Ray Oscilloscope (0 – 20MHz) 1
330 Ω 1
15K Ω 1
3 Resistors 10 M Ω 1
6.8 K Ω 1
1K Ω 1
0.1µf 1
4 Capacitors
1µf 1
5 Regulated power supply (1 -5V), 1A 1

8.3 THEORY
The 555 Timer is a monolithic timing circuit that can produce accurate and highly stable
time delays or oscillations. The timer basically operates in one of the two modes-monostable (one-
shot) multivibrator or as an astable (free-running) multivibrator. In the monostable mode, it can
produce accurate time delays from microseconds to hours. In the astable mode, it can produce
rectangular waves with a variable duty cycle. Frequently, the 555 is used in astable mode to
generate a continuous series of pulses, it can also be used as a one-shot or monostable circuit.

64
 Fig. 8.1 Functional block diagram of IC 555
In astable or free running mode, the 555 can operate as an oscillator. The uses include LED
and lamp flashers, logic clocks, security alarms, pulse generation, tone generation, pulse position
modulation, etc. In the bistable mode, the 555 can operate as a flip-flop and is used to make
bounce-free latched switches, etc.

Fig 8.2 Pin diagram of IC555

65
8.3.1 MONOSTABLE MULTIVIBRATOR
The circuit has an external resistor and capacitor. The voltage across the capacitor is used
for the threshold to pin 6. When the trigger arrives at pin 2, the circuit produces output pulse at pin
3. Initially, if the output of the timer is low, that is, the circuit is in a stable state, transistor Q1 is
on and the external capacitor C is shorted to ground. Upon application of a negative trigger pulse
to pin 2, transistor Q1 is turned off, which releases the short circuit across the capacitor and as a
result, the output becomes high. The capacitor now starts charging up towards Vcc through RA.
When the voltage across the capacitor equals 2/3 Vcc the output of comparator 1 switches from
low to high, which in turn makes the output low via the output of the flip-flop. Also, the output of
the flip-flop turns transistor Q1 on and hence the capacitor rapidly discharges through the
transistor. The output of the monostable multivibrator remains low until a trigger pulse is again
applied. The cycle then repeats. Figure 8.4 shows the trigger input, output voltage, and capacitor
voltage waveforms. As shown, the pulse width of the trigger input must be smaller than the
expected pulse width of the output waveform. Moreover, the trigger pulse must be a negative-
going input signal with an amplitude larger than 1/3 Vcc. The time for which the output remains
high is given by time period = 1.1RAC.

Once the circuit is triggered, the output will remain high for the time interval time period.
It will not change even if an input trigger is applied during this time interval. In other words, the
circuit is said to be non-retriggerable. However, the timing can be interrupted by the application
of a negative signal at the reset input on pin 4. A voltage level going from + Vcc to ground at the
reset input will cause the timer to immediately switch back to its stable state with the output low.

The trigger input may be driven by the output of astable multivibrator with high duty cycle.
If the desired pulse width is of the order of seconds, the output can be seen using a LED and the
resistance value used will be of the order of MΩ. In this case the trigger can be supplied manually
by grounding the trigger input for a fraction of a second.

66
 Fig. 8.3 Monostable Multivibrator using IC 555

Fig 8.4 Input and output waveform of Monostable Multivibrator

Design
Time period of pulse=T=1.1RC=11s
Let C=1 µf
T=1.1RC

67
11s=1.1*R*1µf
R=10MΩ
8.3.2 ASTABLE MULTIVIBRATOR
An astable multivibrator is a wave-generating circuit in which neither of the output levels
is stable. The output keeps on switching between the two unstable states and is a periodic,
rectangular waveform. The circuit is therefore known as an ‘astable multivibrator’. Also, no
external trigger is required to change the state of the output, hence it is also called ‘free-running
multivibrator’. The time for which the output remains in one particular state is determined by the
two resistors and a capacitor externally connected to the 555 timer.

If the output is high initially, capacitor C starts charging towards Vcc through RA and RB.
As soon as the voltage across the capacitor becomes equal to 2/3 Vcc, the upper comparator triggers
the flip-flop, and the output becomes low. The capacitor now starts discharging through RB and
transistor Q1. When the voltage across the capacitor becomes 1/3 Vcc, the output of the lower
comparator triggers the flip-flop, and the output becomes high. The cycle then repeats. The output
voltage and capacitor voltage waveforms are shown in Fig. 8.6.

Fig. 8.5 Astable Multivibrator using IC 555

68
 Fig 8.6 Input and Output waveform of Astable Multivibrator
Design

In output voltage waveform the time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is
equal to the time the output is high and is given by
ton =0.69(RA + RB)C
the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the
output is low and is given by
toff =0.69RBC
the total period of the output wave form is
T=ton+toff=0.69(RA+2RB)C
Thus the frequency of oscillation is
fo=1/T=(1.45/(RA+2RB)C)
Design Constraints
● The 555 Timer is a very versatile low cost timing IC that can produce a very accurate timing
periods with good stability of around 1%
● Duty cycle should be greater than 50% to 80%
● Single RC network connected to a single positive supply of between 4.5 and 16 volts.
● Load resistance minimum value is 1KΩ.
69
8.4 PRE LAB QUESTIONS
Choose the correct answer
1.A quasi-stable state is such that the output
a) does not change at all
b) Changes unpredictably
c) Changes after a predetermined period of time
d) Changes just after a very short duration of time.
2. A monostable multivibrator is also called a ‘one-shot multivibrator’ because
a) Each time a trigger pulse is applied, the circuit produces a single pulse.
b) The circuit has to be triggered only once
c) The output pulse duration is very small
d) None of the above.
3. For a 5 V circuit, if pin 4 is connected to 1 V, does the chip reset?
a) Yes
b) No
c) Cannot be determined

8.5 EXPERIMENT
1. Connect the circuit as shown in the figure with the designed values.
2. Switch on the power supply and observe the waveform.
3. Note down the amplitude and time period.
4. Plot the waveforms on a graph sheet.

Theoretical Output Practical Output

TOTAL TIME TOTAL TIME

TON TON

TOFF TOFF

Amplitude of Amplitude of
Close to VCC
Square waveform. Square waveform.
Charge & discharging Charge & discharging
2/3 VCC – 1/3 VCC
of capacitor by of capacitor by
3.3 – 1.6 = 1.7 v
measuring Amplitude measuring Amplitude

70
8.6 POST LAB QUESTIONS
1. If the diode is connected across RB in the astable multivibrator circuit, what is condition
on RA and RB to achieve duty cycle of 50%?
2. Why the control voltage pin (pin 5) of 555 timers is connected to ground through a
0.01µf capacitor?
3. Calculate the ON time, OFF time, Total time period, Duty cycle and Frequency of the
output generated by an astable multivibrator using resistors RA = 5KΩ, RB =5KΩ and
capacitor C = 10µf.
4. Why the Reset pin of IC555 is normally connected to Vcc?

Result:

71
 EXPERINMENT-9
DESIGN OF LOW PASS FILTER AND HIGH PASS FILTER

9.1 OBJECTIVE
To design a low pass, high pass filter and plot the frequency response.
9.2 HARDWARE REQUIRED
S.No Equipment/Component Name Specifications/Value Quantity
Refer data sheet in
1 IC 741 1
appendix
3.3kΩ 2
2 Resistor 5.8kΩ 1
10kΩ 1
3 Capacitor 0.047uf 2
4 Cathode Ray Oscilloscope (0 – 20MHz) 1
6 Dual power supply 15 V 1
7 Function Generator (0-2) MHz 1

9.3 THEORY

A filter is a circuit that lets certain frequencies pass and blocks other frequencies. This
selective nature can be done two ways, either with passive filters or with active filters. Passive
filters completely comprised of passive elements; namely resistors, capacitors and/or inductors.
Active filters use active devices, i.e., an op-amp, to filter out unwanted signals.

Active filters have the following advantages over passive filters.

● Gain and frequency adjustment and tuning.
● No inductors (reduces cost and size).
● No loading effects.

Some disadvantages of active filters.

● Bandwidth limitations
● Fabrication tolerances
● Can only respond to a specific range of signal magnitudes.

72
Fig. 9.1shows the performance of a practical low-pass and high pass circuit. Active filters can be
classified as; low-pass, high-pass, band-pass, notch, or all pass circuit.

Fig 9.1 Graph of practical (a) Low pass Filter and (b) High pass Filter
Design:
Given fc = 1KHz,
Choose C2=C3=0.047µF, fc=1/2πRC, R2=R3=3.3KΩ, Rf=5.8KΩ, R1=10KΩ, α=3-A
α =1.414; A =1.586
A=1+Rf/R1

SECOND ORDER LOW PASS FILTER

Fig.9.2 Second-Order Low-Pass Filter

73
SECOND ORDER HIGH PASS FILTER

Fig.9.3 Second-Order High-Pass Filter

9.4 PRE LAB QESTIONS

1. Design a second order low pass butterworth filter at a high cut-off frequency of 2.2KHz.
Given RF=20KΩ and capacitor 0.047µF.
2. How is the higher order filters formed?
3. The internal resistor of the second order high pass filter is equal to 10KΩ. Find the value of
feedback resistor?

9.5 EXPERIMENT
9.5.1 Low pass filter
1. Connect the Second order low pass filter circuit as shown in Fig.9.2 with the values
of R2 =R3 =3.3K Ω Rf=5.8K Ω, R1= 10KΩ C2=C3=0.47uF.
2. Apply the sinusoidal input of amplitude 100mV.
3. Vary the frequency and note down the corresponding output amplitude.
4. Plot the frequency response.

9.5.2 High pass filter

1. Connect the Second order high pass filter circuit as shown in Fig.9.3 with the values of
R2 = R3=3.3KΩ, C2=C3=0.047uF, Rf=5.8KΩ, R1=10KΩ.
2. Apply the sinusoidal input of amplitude 100mV.
3. Vary the frequency and note down the corresponding output amplitude.
4. Plot the frequency response.

74
Observation
Low Pass Filter
Vin =
Input Frequency fin Output Amplitude Gain A = Gain(dB) = 20
S.No
(Hz) Vo Vo/Vin log(A)

High Pass Filter

Vin =
Input Frequency Gain A = Gain(dB) = 20
S.No Output Amplitude Vo
fin (Hz) Vo/Vin log(A)

75
9.6 POST LAB QUESTIONS
1. Compute the pass band gain and high cut-off frequency for the first order low pass filter.

2. Determine voltage gain of second order high pass Butterworth filter with the specifications
R3 =R2=33Ω, f = 250Hz and fL=1KHz.

Result:

76
 EXPERINMENT-10
DESIGN OF BAND PASS FILTER AND BAND REJECT FILTER

10.1 OBJECTIVE

To design a Band pass and Band stop filter and plot the frequency response.

10.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in appendix 1

5.6 KΩ 7
2 Resistor 39 KΩ 1
3.9 KΩ 1
3 Capacitor 0.01µF 2

4 Cathode Ray Oscilloscope (0 – 20MHz) 1

6 Regulated power supply (0 -5V), 1A 1

7 Function Generator (0-2) MHz 1

10.3 THEORY

BAND PASS FILTER

The band pass filter passes one set of frequencies while rejecting all others. The band-stop
filter does just the opposite. It rejects a band of frequencies, while passing all others. This is also
called a band-reject or band-elimination filter. Both band pass filters, band-stop filters
classified as (i) wide-band and (ii) narrow band filters.

The narrow band reject filter is also called a notch filter. Because of its higher Q, which
exceeds 10, the bandwidth of the narrow band reject filter is much smaller than that of a wide band
reject filter.

77
 This cascading together of the individual low and high pass passive filters produces a low
“Q-factor” type filter circuit which has a wide pass band. The first stage of the filter will be the
high pass stage that uses the capacitor to block any DC biasing from the source. This design has
the advantage of producing a relatively flat asymmetrical pass band frequency response with one
half representing the low pass response and the other half representing high pass response as shown
in below figure.

Fig. 10.1 Graphical representation of practical Band pass Filter.

The higher corner point ( ƒH ) as well as the lower corner frequency cut-off point ( ƒL ) are
calculated the same as before in the standard first-order low and high pass filter circuits. Obviously,
a reasonable separation is required between the two cut-off points to prevent any interaction
between the low pass and high pass stages. The amplifier also provides isolation between the two
stages and defines the overall voltage gain of the circuit.

The bandwidth of the filter is therefore the difference between these upper and lower -3dB
points. For example, if the -3dB cut-off points are at 200Hz and 600Hz then the bandwidth of the
filter would be given as: Bandwidth (BW) = 600 – 200 = 400Hz.

BAND-STOP (OR REJECT) FILTER.

A wide band-stop filter using a low-pass filter, a high-pass filter and a summing amplifier
is shown in fig 10.2. For a proper band reject response, the low cut-off frequency fL of high-pass
filter must be larger than the high cut-off frequency fH of the low-pass filter. In addition, the pass
band gain of both the high-pass and low-pass sections must be equal.

78
 Fig. 10.2 Graph of practical (a) Band pass Filter and (b) Band stop Filter
Band Pass Filter
Design:
To design a band pass filter having fH = 4KHz and fL = 400Hz and pass band gain of 2.
As shown in Fig 10.3, the first section consisting of Op Amp, RF, R1, R and C is the high pass
filter and second section consisting of low pass filter. The design of low pass and high pass
filters are given below.
Low Pass Filter Design:
Assuming C’=0.01μf, the value of R’ is found from
R’ = 1/ (2πfH C’) Ω =3.97KΩ
The pass band gain of LPF is given by ALPF = 1+ (R’ F / R’1) = 2
Assuming R’1=5.6 KΩ, the value of R’F is found from R’F = (AF-1) R’1 = 5.6KΩ

High Pass Filter Design:

Assuming C=0.01μf, the value of R is found from
R = 1/(2πfLC) Ω =39.7KΩ
The pass band gain of HPF is given by AHPF = 1+ (RF / R1) = 2
Assuming R1=5.6 KΩ, the value of RF is found from
RF = (AF-1) R1=5.6KΩ

79
 Fig. 10.3 Band Pass Filter

Band Stop Filter

Design:
To design a band reject filter with fL = 4 KHz, fH = 400Hz and pass band gain of 2

Low Pass Filter Design:

Assuming C’=0.01μf, the value of R’ is found from
R’ = 1/(2πfH C’) Ω =39.7KΩ
The pass band gain of LPF is given by ALPF = 1+ (R’ F / R’1 ) = 2
Assuming R’1=5.6 KΩ, the value of R’F is found from
R’F = (AF-1) R’1=5.6KΩ

High Pass Filter Design:

Assuming C=0.01μf, the value of R is found from
R = 1/ (2πfLC) Ω =3.97KΩ
The pass band gain of HPF is given by AHPF = 1+ (RF / R1) =2
Assuming R1=5.6 KΩ, the value of RF is found from
RF = (AF-1) R1=5.6KΩ

Adder circuit design: Select all resistors equal value such that gain is unity.
Assume R2=R3=R4=5.6 KΩ

80
 Fig. 10.4 Band Stop Filter

10.4 PRE LAB QUESTIONS

1. A band-pass filter has a bandwidth of 250Hz and center frequency of 866Hz. Find the
quality factor of the filter?
2. Write the center frequency expression of wide band-pass filter.
3. Compute the quality factor of the wide band-pass filter with high and low cut-off
frequencies
equal to 950Hz and 250Hz.

10.5 EXPERIMENT
10.5.1 Band Pass Filter

1. Connect the Second order band pass filter circuit as shown in Fig.10.3
2. Apply the sinusoidal input of amplitude 100mV.
3. Vary the frequency and note down the corresponding output amplitude.
4. Plot the frequency response.

10.5.2 Band Stop Filter

1. Connect the Second order band stop filter circuit as shown in Fig.10.4
2. Apply the sinusoidal input of amplitude 100mV.
3. Vary the frequency and note down the corresponding output amplitude.
4. Plot the frequency response.

81
Observation
Band Pass Filter
Vin =
Input Frequency Output Amplitude Gain(dB) = 20
S.No Gain A = Vo/Vin
fin Vo log(A)

Band Stop Filter

Vin =
S.No Input Frequency Output Amplitude Vo Gain A = Gain(dB) = 20
fin Vo/Vin log(A)

82
10.6 POSTLAB QUESTIONS
1. The details of low pass filter are given as fh =10kHz, AF= 2 and f=1.2kHz. Find the
voltage
a. gain magnitude of first order wide band-pass filter, if the voltage gain
magnitude of high
b. pass filter section is 8.32dB.

2. Find the voltage gain magnitude of the wide band-pass filter, where total pass band
gain is
a. 6, input frequency = 750Hz, lower cut-off frequency = 200Hz and higher
cut-off frequency
b. =1KHz.

Result:

83
 EXPERINMENT-11
SERIES VOLTAGE REGULATOR

11.1 OBJECTIVES
Design a series voltage regulator using op amp IC741.

11.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity
Refer data sheet in
1 IC 741 1
appendix
1 KΩ 1
24 KΩ 1
2 Resistors
100 Ω 1
12 KΩ 1

3 Transistor Q2N2222 1

4 Diode DIN746 1

5 Dual Regulated power supply (0 -30V), 1A 1

6 Multimeter 1
7 Decade Resistance Box (DRB) 1

11.3 THEORY
A voltage regulator is a voltage stabilizer that is designed to automatically stabilize a
constant voltage level. A voltage regulator circuit is also used to change or stabilize the voltage
level according to the necessity of the circuit. Thus, a voltage regulator is used for two reasons:

1. To regulate or vary the output voltage of the circuit.

2. To keep the output voltage constant at the desired value in-spite of variations in the
supply voltage or in the load current.

All electronic voltage regulators will have a stable voltage reference source which is
provided by the reverse breakdown voltage operating diode called zener diode. The main reason
to use a voltage regulator is to maintain a constant dc output voltage. It also blocks the ac ripple

84
 voltage that cannot be blocked by the filter. A good voltage regulator may also include additional
circuits for protection like short circuits, current limiting circuit, thermal shutdown, and over
voltage protection. Electronic voltage regulators are designed by any of the three or a combination
of any of the three regulators given below.

A zener controlled voltage regulator is used when the efficiency of a regulated power
supply becomes very low due to high current. There are two kinds of zener controlled transistor
voltage regulators. Zener Controlled Transistor Series Voltage Regulator is a circuit is also named
an emitter follower voltage regulator. It is called so because the transistor used is connected in an
emitter follower configuration. The circuit consists of an N-P-N transistor and a zener diode. As
shown in the figure below, the collector and emitter terminals of the transistor are in series with
the load. Thus, this regulator has the name series in. The reference voltage is provided by the
zener diode and the transistor acts as a variable resistor, whose resistance varies with the operating
conditions of base current, Ibase. The main principle behind the working of such a regulator is that
a large proportion of the change in supply or input voltage appears across the transistor and thus
the output voltage tends to remain constant.

The output voltage can thus be written as

Vout = Vzener – Vbe
The transistor base voltage Vbase and the zener diode voltage Vzener are equal and thus the
value of Vbase remains almost constant.

Operation

When the input supply voltage Vin increases the output voltage Vload also increases. This
increase in Vload will cause a reduced voltage of the transistor base emitter voltage Vbe as the zener
voltage Vzener is constant. This reduction in Vbe causes a decrease in the level of conduction which
will further increase the collector-emitter resistance of the transistor and thus causing an increase
in the transistor collector-emitter voltage and all of this causes the output voltage Vout to reduce.
Thus, the output voltage remains constant. The operation is similar when the input supply voltage
decreases.

The next condition would be the effect of the output load change in regard to the output
voltage. Let us consider a case, where the current is increased by the decrease in load resistance
Rload. This causes a decrease in the value of output voltage and thus causes the transistor base

85
emitter voltage to increase. This causes the collector emitter resistance value to decrease due to an
increase in the conduction level of the transistor. This causes the input current to increase slightly
and thus compensates for the decrease in the load resistance Rload.

The biggest advantage of this circuit is that the changes in the zener current are reduced by
a factor β and thus the zener effect is greatly reduced and a much more stabilized output is obtained.
The output voltage of the series regulator is Vout = Vzener – Vbe. The load current Iload of the circuit
will be the maximum emitter current that the transistor can pass. For a normal transistor like the
2N3055, the load current can go upto 15A. If the load current is zero or has no value, then the
current drawn from the supply can be written as Izener + Ic(min). Such an emitter follower voltage
regulator is more efficient than a normal zener regulator. A normal zener regulator that has only a
resistor and a zener diode has to supply the base current of the transistor.

Limitations

The limitations listed below has proved the use of this series voltage regulator only suitable
for low output voltages.

1. With the increase in room temperature, the values of Vbe and Vzener tend to decrease.
Thus, the output voltage cannot be maintained a constant. This will further increase
the transistor base emitter voltage and thus the load.
2. There is no option to change the output voltage in the circuit.
3. Due to the small amplification process provided by only one transistor, the circuit
cannot provide good regulation at high currents.
4. When compared to other regulators, this regulator has poor regulation and ripple
suppression with respect to input variations.
5. The power dissipation of a pass transistor is large because it is equal to Vcc Ic and
almost all variation appears at Vce and the load current is approximately equal to
collector current. Thus, for heavy load currents pass transistor has to dissipate a lot of
power and, therefore, becoming hot.

86
 Fig.11.1 Voltage regulator

R1=1kΩ, RL =R4=100Ω, R2=12kΩ, R3=24kΩ.

11.4 PRE LAB QUESTIONS

1. A voltage regulator with a no-load output dc voltage of 12V is connected to a load
with a resistance of 10Ω. If the load resistance decreases to 7.5Ω, the load voltage
will decrease to 10.9V. Calculate load current and the percent load regulation.
2. The ________ regulator is less efficient than the ________ type, but offers inherent
short-circuit protection.
3. What is line regulation?

11. 5 EXPERIMENT
1. Connect the circuit as shown in Figure-11.1.
2. For Line Regulation, set RL at 100 Ω. Vary the input voltage (V1) from 5V to 25V. For
each setting, find the output voltage (Vo). Plot the graph of Vo vs Vi.
3. For Load Regulation, set V1 at 10 V. Vary the load resistance RL from 100Ω to 1000Ω.
For each setting, find the output voltage (Vo). Plot the graph of Vo vs RL.

87
Observation
Line Regulation RL=100Ω

S.No. VIN (V) VOUT (V)

Load Regulation VIN= 10 V

S.No. RL(Ω) VOUT(V)

11.6 POST LAB QUESTIONS

1. Calculate the voltage regulation of a power supply having VNL = 50 V and VFL = 48 V.
2. What is the purpose of an additional RC filter section in a power supply circuit?
3. In a series regulator, what is the purpose of fold-back limiting?

Result:

88
 EXPERINMENT-12
R-2R LADDER DAC

12.1 OBJECTIVES

Design a D to A Convertor with a resolution of 0.3125V using R-2R network. Assume

the logic 1 to be 5V and logic 0 to be 0V.

12.2.1 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in appendix 1

3 Resistors 2K Ω 5

1K Ω 3

5 Dual Regulated power supply (0 -30V), 1A 1

5 Regulated power supply (0 -5V), 1A 1

6 Multimeter 1

12.3 THEORY

In electronics, a digital-to- analog converter (DAC) is a device for converting a digital

(usually binary) code to an analog signal (current, voltage or electric charge). Digital-to-analog
converters are the interface between the abstract digital world and the analog real life. An analog-
to-digital converter (abbreviated ADC, A/D or A to D) is an electronic circuit that converts
continuous signals to discrete digital numbers. Most of the real world physical quantities such as
voltage, current, temperature, pressure and time are available in analog form. Even though an
analog signal represent a real physical parameter with accuracy, it is difficult to process, store or
transmit the analog signal without introducing considerable error because of the superimposition
of noise as in the case of amplitude modulation. Therefore, for processing, transmission and
storage purposes, it is often convenient to express these variable in digital form. It gives better
accuracy and reduces noise.

89
 D/A conversion is an important interface process for converting digital signals to analog
(linear) signals. An example is a voice signal that is digitized for storage processing, or
transmission and must be changed back into an approximation of the original audio signal in order
to drive a speaker.

Fig.12.1 A basic DAC

D/A Conversion fundamentals

The DAC fundamentally converts finite-precision numbers (usually fixed-point binary

numbers) into a physical quantity, usually an electrical voltage. Normally the output voltage is a
linear function of the input number.

Fig.12.2 Block Schematic of a basic DAC

Fig.12.2 shows the basic configuration for digital-to-analog (D/A) conversion. The input is
an n-bit binary word D and is combined with a reference voltage VR to give an analog output
signal. The output of a DAC can be either a voltage or current. For a voltage output DAC, the D/A
converter is mathematically described as
Vo = K VFS (d12-1+ d22-2+….+dn2-n)
Where, Vo =output voltage

VFS= full scale output voltage

90
 K=scaling factor usually adjusted to unity

d1 d2... dn=n-bit binary fractional word with the decimal point located at the
left d1 = most significant bit (MSB) with a weight of VFS / 2

dn=least significant bit (ISB) with a weight of VFs / 2n

Since the input to the D/A converter has a finite number of digital combinations, the
resulting analog output also has a limited number of possible values (unlike pure analog signals,
which may have an infinite number of values). The greater the number of possible values, the
closer the analog output will be to the ideal value. The number of possible levels is determined by
the number of lines or bits in the digital number. More specifically, the number of states is
computed as 2N where N is the number of bits in the digital number. For example, an 8-bit D/A
converter could be expected to produce 28 or 256, discrete output steps. If the full-scale range of
the converter is 0 to 10 volts, then each step will be 10/256, or about 39 millivolts. If finer
resolution is required, we need more bits in the digital number. Thus, a converter with 10-bit
resolution would provide 210 or 1024, steps with each step being equivalent to 10/1024, or about
9.8 millivolts. Accuracy of a D/A converter describes the amount of error between the actual output
of the converter and the theoretical output for a given input number. This rating inherently includes
several other sources of error.

R-2R Ladder D/A Converter

One of the most popular methods for D/A conversion is shown in Fig 12.3. It is called an
R-2R ladder D/A converter, since the input network resembles the rungs on a ladder and the
resistors in the input network are either equal (R) or have a 2:1 ratio (2R). One advantage of the
R-2R converter over the weighted converter is the resistors have a 2:1 ratio regardless of the
number of bits being converted. This makes matching resistors much easier and even makes the
use of integrated resistors practical.

An easy way to analyze the operation of the circuit is to Thevenize the input circuit for one
or more digital input numbers. Once the input circuit has been simplified with the Thevenin’s
theorem, it is left with a simple inverting amplifier circuit whose input voltage is the Thevenin
equivalent voltage and whose gain is determined by the ratio of feedback resistance to Thevenin

91
equivalent input resistance. By performing several analyses with different input numbers, you will
discover that the least significant input (b0) produces the least effect on output voltage, and the
next input (bl) has twice as much effect on output voltage. Similarly, bit b2 has twice the effect of
b1, but only half the effect onoutput voltage of b3. These variable effects are identical to the relative
weights of the digits in a binary number.

Fig.12.3 A 3-bit R2R ladder D/A converter utilizing a 741 Op-amp

Calculations: Output Voltage is given by

Vo = - V * (R / 2R) * (b /2 + b /4 + b /8)
R f 2 1 0

where, V = 5V, R = 2R, b (MSB bit) and b (LSB bit)

R f 2 0

Design Constraints
● Resistance should be use ±1 to ±5 tolerance

● Input voltage should be 5V for high and 0V for low.

12.4 PRE LAB QUESTIONS

1. Classify DACs on the basis of their output.

2. How many resistors are required in a 12-bit weighted-resistor DAC?
3. How many levels are possible in a 2-bit DAC? What is its resolution if the output voltage
range is 0 to 3 V?

92
 4. A 5-bit D/A converter is available. Assume that ‘00000’ corresponds to an output of +10
V and that the D/A converter is connected for -0.1V per increment. What output voltage
will be produced for ‘11111’?
5. What is the resolution of a 0–5 V 6-bit digital-to-analog converter (DAC).

12.5 EXPERIMENT
.
1. Setup the circuit as shown in Fig. 12.3.
2. Set the approximate value of R and 2R.
3. Reference voltage V is set as 5V
R

4. Find the output voltage Vo for different combinations of digital binary inputs from 000 to
111.
5. Compare the calculated values with observed values and plot DAC characteristics.

Observations

R-2R LADDER DAC

b2 b1 b0 Vo ( observed) Vo ( Calculated)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

12.6 POST LAB QUESTIONS

1. Determine the output voltage of the DAC in Fig-12.5(a). The sequence of four-digit binary
codes represented by the waveforms in Fig-12.5(b) are applied to the inputs. A high level is a
binary l, and low level is a binary 0. The least significant binary digit is D0.

93
 Fig-12.5

2. The R-2R ladder DAC shown in Fig-12.6 below consists of 10KΩ & 20KΩ resistors, VREF
= 2V and R1 = 10KΩ. Determine the values required for RF such that VFS = 10V.

Fig-12.6 R-2R Ladder DAC

3. What is the value of resistor required in weighted resistor DAC if LSB resistor value is
12KΩ for 4-bit DAC?

4. A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the
analog output for the input code 0101?

5. What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to
a binary-weighted digital-to-analog DAC converter?

Result:

94
 EXPERINMENT-13
FLASH TYPE ADC

13.1 OBJECTIVE
To construct a FLASH type A to D Convertor using LTspice simulation.

13.1.1 SOFTWARE REQUIRED

LTspice simulator

13.2 THEORY
A flash ADC (also known as a direct-conversion ADC) is a type of analog-to-digital
converter that uses a linear voltage ladder with a comparator at each "rung" of the ladder to
compare the input voltage to successive reference voltages. Often these reference ladders are
constructed of many resistors; however, modern implementations show that capacitive voltage
division is also possible. The output of these comparators is generally fed into a digital encoder,
which converts the inputs into a binary value (the collected outputs from the comparators can be
thought of as a unary value). Flash converters are extremely fast compared to many other types of
ADCs.

A flash converter requires a huge number of comparators compared to other ADCs, especially
as the precision increases. A flash converter requires comparators for an n-bit conversion. The
size, power consumption and cost of all those comparators makes flash converters generally
impractical for precisions much greater than 8 bits (255 comparators). In place of these
comparators, most other ADCs substitute more complex logic and/or analog circuitry that can be
scaled more easily for increased precision. Flash ADCs have been implemented in many
technologies, varying from silicon-based bipolar (BJT) and complementary metal–
oxide FETs (CMOS) technologies to rarely used III-V technologies. Often this type of ADC is
used as a first medium-sized analog circuit verification.

The earliest implementations consisted of a reference ladder of well-matched resistors

connected to a reference voltage. Each tap at the resistor ladder is used for one comparator,
possibly preceded by an amplification stage, and thus generates a logical 0 or 1 depending on

95
whether the measured voltage is above or below the reference voltage of the resistor tap. The
reason to add an amplifier is twofold: it amplifies the voltage difference and therefore suppresses
the comparator offset, and the kick-back noise of the comparator towards the reference ladder is
also strongly suppressed. Typically designs from 4-bit up to 6-bit and sometimes 7-bit are
produced.

Fig.13.1 Flash type ADC

Flash type ADC

Comparator o/p Digital o/p

Analog i/p

(0-5v)
C3 C2 C1 C0 A1 A0
0-1.25 0 0 0 1 0 0
1.25-2.5 0 0 1 1 0 1
2.5-3.75 0 1 1 1 1 0
3.75-5.0 1 1 1 1 1 1

96
Design Constraints
● Resistance should be use ±1 to ±5 tolerance
● Input voltage should be 5V for high and 0V for low.

13.4 PRE LAB QUESTIONS

1. Classify ADCs on the basis of their output.
2. Mention the control lines present in ADC.
3. Which type of ADC follows conversion technique of changing the analog input voltage as a
function of frequency?

13.5 LTSPICE SIMULATION

Circuit Diagram:

97
Input and Output:

Observation:

Output
Input voltage range
𝑌1 𝑌0
0 to 1.25 V
1.25 V to 2.5 V
2.5 V to 3.75 V
3.75 V to 5 V

13.6 POST LAB QUESTIONS

1. Calculate the conversion time of a 12-bit counter type ADC with 1MHz clock frequent
to convert a full scale input?
2. How many comparators are required for 4-bit ADC?

Result:

98
 Product Order Technical Tools & Support &
Folder Now Documents Software Community

uA741
SLOS094G – NOVEMBER 1970 – REVISED JANUARY 2018

µA741 General-Purpose Operational Amplifiers

1 Features 3 Description
•
1 Short-Circuit Protection The µA741 device is a general-purpose operational
amplifier featuring offset-voltage null capability.
• Offset-Voltage Null Capability
• Large Common-Mode and Differential Voltage The high common-mode input voltage range and the
Ranges absence of latch-up make the amplifier ideal for
voltage-follower applications. The device is
• No Frequency Compensation Required short-circuit protected and the internal frequency
• No Latch-Up compensation ensures stability without external
components. A low-value potentiometer may be
2 Applications connected between the offset null inputs to null out
the offset voltage as shown in Figure 12.
• DVD Recorders and Players
• Pro Audio Mixers The µA741C device is characterized for operation
from 0°C to 70°C.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
µA741CD SOIC (8) 4.90 mm × 3.91 mm
µA741CP PDIP (8) 9.81 mm × 6.35 mm
µA741CPS SO (8) 6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Schematic
OFFSET N1

IN + +
OUT
IN – –

OFFSET N2

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
uA741
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Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 10
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 11
3 Description ............................................................. 1 7.5 µA741Y Chip Information........................................ 11
4 Revision History..................................................... 2 8 Application and Implementation ........................ 12
8.1 Application Information............................................ 12
5 Pin Configurations and Functions ....................... 4
8.2 Typical Application .................................................. 12
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5 9 Power Supply Recommendations...................... 14
6.2 Recommended Operating Conditions....................... 5 10 Layout................................................................... 14
6.3 Thermal Information .................................................. 5 10.1 Layout Guidelines ................................................. 14
6.4 Electrical Characteristics: μA741C............................ 6 10.2 Layout Example .................................................... 14
6.5 Electrical Characteristics: μA741Y ............................ 7 11 Device and Documentation Support ................. 16
6.6 Switching Characteristics: μA741C ........................... 7 11.1 Receiving Notification of Documentation Updates 16
6.7 Switching Characteristics: μA741Y ........................... 7 11.2 Trademarks ........................................................... 16
6.8 Typical Characteristics .............................................. 8 11.3 Electrostatic Discharge Caution ............................ 16
7 Detailed Description ............................................ 10 11.4 Glossary ................................................................ 16
7.1 Overview ................................................................. 10 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 10 Information ........................................................... 16

4 Revision History
Changes from Revision F (May 2017) to Revision G Page

• Changed supply voltage unit from "°C" to "V" in Absolute Maximum Ratings table ............................................................. 5

Changes from Revision E (January 2015) to Revision F Page

• Updated data sheet text to the latest documentation and translation standards .................................................................. 1
• Deleted text regarding µA741M device (obsolete package) from Description section........................................................... 1
• Added µA741CD, µA741CP, and µA741CPS devices to Device Information table .............................................................. 1
• Deleted µA741x device from Device Information table ......................................................................................................... 1
• Updated pinout diagrams and Pin Functions tables in the Pin Configurations and Functions section .................................. 4
• Deleted µA741M pinout drawings information from Pin Configurations and Functions section ............................................ 4
• Deleted Electrical Characteristics: µA741M table from Specifications section ...................................................................... 5
• Added operating junction temperature (TJ) and values to Absolute Maximum Ratings table ............................................... 5
• Deleted text regarding µA741M from Absolute Maximum Ratings table .............................................................................. 5
• Deleted text regarding µA741M device from Recommended Operating Conditions table .................................................... 5
• Deleted Dissipation Ratings table .......................................................................................................................................... 5
• Added Thermal Information table and values ........................................................................................................................ 5
• Deleted µA741M in Switching Characteristics table .............................................................................................................. 7
• Correct typo in Figure 1 ......................................................................................................................................................... 8
• Deleted text regarding µA741M device from Detailed Description section .......................................................................... 10
• Updated text in Overview section ........................................................................................................................................ 10
• Added 2017 copyright to Functional Block Diagram ........................................................................................................... 10
• Added caption to Figure 11 in Device Functional Modes section ........................................................................................ 11
• Changed pins 1 and 5 from "NC" to "Offset N1" and "Offset N2" in Figure 18 .................................................................... 15

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Changes from Revision D (February 2014) to Revision E Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
• Moved Typical Characteristics into Specifications section. ................................................................................................... 8

Changes from Revision C (January 2014) to Revision D Page

• Fixed Typical Characteristics graphs to remove extra lines. ................................................................................................. 8

Changes from Revision B (September 2000) to Revision C Page

• Updated document to new TI data sheet format - no specification changes. ........................................................................ 1

• Deleted Ordering Information table. ....................................................................................................................................... 1

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5 Pin Configurations and Functions

uA741C D, P, or PS Package
8-Pin SOIC, PDIP, SO
Top View

OFFSET N1 1 8 NC

IN± 2 7 VCC+

IN+ 3 6 OUT

VCC± 4 5 OFFSET N2

Not to scale

NC- no internal connection

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
IN+ 3 I Noninverting input
IN– 2 I Inverting input
NC 8 — No internal connection
OFFSET N1 1 I External input offset voltage adjustment
OFFSET N2 5 I External input offset voltage adjustment
OUT 6 O Output
VCC+ 7 — Positive supply
VCC– 4 — Negative supply

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6 Specifications
6.1 Absolute Maximum Ratings
over virtual junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VCC (2) µA741C –18 18 V
Differential input voltage, VID (3) µA741C –15 15 V
(2) (4)
Input voltage, VI (any input) µA741C –15 15 V
Voltage between offset null (either OFFSET N1 or
µA741C –15 15 V
OFFSET N2) and VCC–
(5)
Duration of output short circuit Unlimited
Continuous total power dissipation See Thermal Information
Case temperature for 60 seconds µA741C N/A N/A °C
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds µA741C N/A N/A °C
Lead temperature 1.6 mm (1/16 inch) from case for 10
D, P, or PS package µA741C 260 °C
seconds
Operating junction temperature, TJ 150 °C
Storage temperature range, Tstg µA741C –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC–.
(3) Differential voltages are at IN+ with respect to IN –.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output may be shorted to ground or either power supply.

6.2 Recommended Operating Conditions

MIN MAX UNIT
VCC+ 5 15
Supply voltage V
VCC– –5 –15
TA Operating free-air temperature µA741C 0 70 °C

6.3 Thermal Information

µA741
THERMAL METRIC (1) D (SOIC) P (PDIP) PS (SO) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 129.2 87.4 119.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 73.6 89.3 66 °C/W
RθJB Junction-to-board thermal resistance 72.4 64.4 70 °C/W
ψJT Junction-to-top characterization parameter 25.9 49.8 27.2 °C/W
ψJB Junction-to-board characterization parameter 71.7 64.1 69 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.4 Electrical Characteristics: μA741C

at specified virtual junction temperature, VCC± = ±15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
25°C 1 6
VIO Input offset voltage VO = 0 mV
Full range 7.5
ΔVIO(adj) Offset voltage adjust range VO = 0 25°C ±15 mV
25°C 20 200
IIO Input offset current VO = 0 nA
Full range 300
25°C 80 500
IIB Input bias current VO = 0 nA
Full range 800
25°C ±12 ±13
VICR Common-mode input voltage range V
Full range ±12
RL = 10 kΩ 25°C ±12 ±14
RL ≥ 10 kΩ Full range ±12
VOM Maximum peak output voltage swing V
RL = 2 kΩ 25°C ±10
RL ≥ 2 kΩ Full range ±10

Large-signal differential voltage RL ≥ 2 kΩ 25°C 20 200

AVD V/mV
amplification VO = ±10 V Full range 15
ri Input resistance 25°C 0.3 2 MΩ
ro Output resistance VO = 0; see (2) 25°C 75 Ω
Ci Input capacitance 25°C 1.4 pF
25°C 70 90
CMRR Common-mode rejection ratio VIC = VICRmin dB
Full range 70
25°C 30 150
kSVS Supply voltage sensitivity (ΔVIO/ΔVCC) VCC = ±9 V to ±15 V µV/V
Full range 150
IOS Short-circuit output current 25°C ±25 ±40 mA
25°C 1.7 2.8
ICC Supply current VO = 0; no load mA
Full range 3.3
25°C 50 85
PD Total power dissipation VO = 0; no load mW
Full range 100

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified.
Full range for the µA741C is 0°C to 70°C.
(2) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.

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6.5 Electrical Characteristics: μA741Y

at specified virtual junction temperature, VCC± = ±15 V, TA = 25°C (unless otherwise noted) (1)
(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage VO = 0 1 5 mV
ΔVIO(adj) Offset voltage adjust range VO = 0 ±15 mV
IIO Input offset current VO = 0 20 200 nA
IIB Input bias current VO = 0 80 500 nA
VICR Common-mode input voltage range ±12 ±13 V
RL = 10 kΩ ±12 ±14
VOM Maximum peak output voltage swing V
RL = 2 kΩ ±10 ±13
AVD Large-signal differential voltage amplification RL ≥ 2 kΩ 20 200 V/mV
ri Input resistance 0.3 2 MΩ
ro Output resistance VO = 0; see (1) 75 Ω
Ci Input capacitance 1.4 pF
CMRR Common-mode rejection ratio VIC = VICRmin 70 90 dB
kSVS Supply voltage sensitivity (ΔVIO/ΔVCC) VCC = ±9 V to ±15 V 30 150 µV/V
IOS Short-circuit output current ±25 ±40 mA
ICC Supply current VO = 0; no load 1.7 2.8 mA
PD Total power dissipation VO = 0; no load 50 85 mW

(1) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified.

6.6 Switching Characteristics: μA741C

over operating free-air temperature range, VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Rise time VI = 20 mV, RL = 2 kΩ 0.3 µs
Overshoot factor CL = 100 pF; see Figure 1 5%
VI = 10 V, RL = 2 kΩ
SR Slew rate at unity gain 0.5 V/µs
CL = 100 pF; see Figure 1

6.7 Switching Characteristics: μA741Y

over operating free-air temperature range, VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Rise time VI = 20 mV, RL = 2 kΩ 0.3 µs
Overshoot factor CL = 100 pF; see Figure 1 5%
VI = 10 V, RL = 2 kΩ
SR Slew rate at unity gain 0.5 V/µs
CL = 100 pF; see Figure 1

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6.8 Typical Characteristics

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.

VI
– OUT
IN
+
0V

INPUT VOLTAGE
WAVEFORM
CL = 100 pF RL = 2 kΩ

TEST CIRCUIT
Figure 1. Rise Time, Overshoot, and Slew Rate

100 400
VCC+ = 15 V
VCC+ = 15 V
90 VCC – = –15 V
350 VCC – = –15 V
I IO – Input Offset Current – nA

I IB – Input Bias Current – nA

80
300
70

60 250

50 200

40
150
30
100
20
50
10

0 0
– 60 – 40 – 20 0 20 40 60 80 100 120 140 – 60 – 40 – 20 0 20 40 60 80 100 120 140

TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C

Figure 2. Input Offset Current vs Free-Air Temperature Figure 3. Input Bias Current vs Free-Air Temperature
±14 ±20
VCC+ = 15 V VCC+ = 15 V
VOM – Maximum Peak Output Voltage – V

VOM – Maximum Peak Output Voltage – V

±13 VCC – = –15 V ±18 VCC – = –15 V

TA = 25°C RL = 10 kΩ
±12 ±16 TA = 25°C

± 11 ±14

±10 ±12

±9 ±10

±8 ±8

±7 ±6

±6 ±4

±5 ±2

±4 0
0.1 0.2 0.4 0.7 1 2 4 7 10 100 1k 10k 100k 1M
RL – Load Resistance – kΩ f – Frequency – Hz
Figure 4. Maximum Output Voltage vs Load Resistance Figure 5. Maximum Peak Output Voltage vs Frequency

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Typical Characteristics (continued)

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
400 110
VO = ±10 V
RL = 2 kΩ 100 VCC+ = 15 V
TA = 25°C VCC – = –15 V
AVD – Open-Loop Signal Differential

AVD – Open-Loop Signal Differential

200 90 VO = ±10 V
Voltage Amplification – V/mV

80 RL = 2 kΩ

Voltage Amplification – dB
TA = 25°C
70
100
60

50

40 40
30
20
20
10
0
10 –10
0 2 4 6 8 10 12 14 16 18 20 1 10 100 1k 10k 100k 1M 10M
VCC ± – Supply Voltage – V f – Frequency – Hz
Figure 6. Open-Loop Signal Differential Voltage Figure 7. Open-Loop Large-Signal Differential Voltage
Amplification vs Supply Voltage Amplification vs Frequency
100 28
CMRR – Common-Mode Rejection Ratio – dB

VCC+ = 15 V
90 VCC– = –15 V 24
BS = 10 kΩ
80
TA = 25°C
20
VO – Output Voltage – mV

70
90%
16
60

50 12

40 8
30 VCC+ = 15 V
4
VCC– = –15 V
20 10% RL = 2 kΩ
0
10 CL = 100 pF
tr TA = 25°C
0 –4
1 100 10k 1M 100M 0 0.5 1 1.5 2 2.5
f – Frequency – Hz t – Time - µs
Figure 8. Common-Mode Rejection Ratio vs Frequency Figure 9. Output Voltage vs Elapsed Time
8
VCC+ = 15 V
6 VCC– = –15 V
RL = 2 kΩ
CL = 100 pF
Input and Output Voltage – V

4
TA = 25°C
VO
2

0
VI
–2

–4

–6

–8
0 10 20 30 40 50 60 70 80 90

t – Time – ms
Figure 10. Voltage-Follower Large-Signal Pulse Response

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7 Detailed Description

7.1 Overview
The μA741 has been a popular operational amplifier for over four decades. Typical open loop gain is 106 dB
while driving a 2000-Ω load. Short circuit tolerance, offset voltage trimming, and unity-gain stability makes the
μA741 useful for many applications.

7.2 Functional Block Diagram

VCC+

IN –

OUT
IN+

OFFSET N1
OFFSET N2

VCC –

Component Count
Transistors 22
Resistors 11
Diode 1
Capacitor 1 Copyright © 2017, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Offset-Voltage Null Capability
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors and so forth. The input offset pins allow the designer to adjust for
mismatches caused by external circuitry. See Application and Implementation for more details on design
techniques.

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Feature Description (continued)

7.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change an output when there is a change on the
input. The µA741 device has a 0.5-V/μs slew rate. Parameters that vary significantly with operating voltages or
temperature are shown in Typical Characteristics.

7.4 Device Functional Modes

The µA741 device is powered on when the power supply is connected. The device can operate as a single-
supply or dual-supply operational amplifier depending on the application.

7.5 µA741Y Chip Information

When properly assembled, this chip displays characteristics similar to the µA741C device. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips can be mounted with conductive
epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

VCC+
(7)
(7) (6) IN +
(3)
+ (6)
(2) OUT
IN – –
OFFSET N1 (1) (4)
(8)
OFFSET N2 (5) VCC –

45
(5)

(1) CHIP THICKNESS: 15 TYPICAL

(4)
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150 °C.
(2) (3) TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
36

Figure 11. Bonding Pad Assignments

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas (β), collector or emitter resistors and so forth. The input offset pins allow the designer to adjust for
mismatches resulting from external circuitry. These input mismatches can be adjusted by placing resistors or a
potentiometer between the inputs as shown in Figure 12. A potentiometer can fine-tune the circuit during testing
or for applications which require precision offset control. For more information about designing using the input-
offset pins, see Nulling Input Offset Voltage of Operational Amplifiers.

IN + +
OUT
IN – – OFFSET N2

OFFSET N1
10 kΩ

To VCC –

Figure 12. Input Offset Voltage Null Circuit

8.2 Typical Application

The voltage follower configuration of the operational amplifier is used for applications where a weak signal drives
a relatively high current load. This circuit is also called a buffer amplifier or unity-gain amplifier. The inputs of an
operational amplifier have a very high resistance which puts a negligible current load on the voltage source. The
output resistance of the operational amplifier is almost negligible, so the resistance can provide as much current
as necessary to the output load.
10 k

12 V

VOUT
+

VIN

Figure 13. Voltage Follower Schematic

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Typical Application (continued)

8.2.1 Design Requirements
• Output range from 2 V to 11.5 V
• Input range from 2 V to 11.5 V
• Resistive feedback to negative input

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Swing

The output voltage of an operational amplifier is limited by the internal circuitry to some level below the supply
rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output
voltage requirements.

8.2.2.2 Supply and Input Voltage

For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail
voltage or lower than the recommended negative supply rail voltage. The selected amplifier must be able to
operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to
11.5 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail rather than ground allows the
amplifier to maintain linearity for inputs below 2 V.

8.2.3 Application Curves for Output Characteristics

12 0.045
0.040
10
0.035
0.030
8
0.025
VOUT (V)

IIO (mA)

6 0.020
0.015
4
0.010
0.005
2
0.000
0 ±0.005
0 2 4 6 8 10 12 0 2 4 6 8 10 12
VIN (V) C001 VIN (V) C002

Figure 14. Output Voltage vs Input Voltage Figure 15. Current Drawn Input of Voltage Follower (IIO)
vs Input Voltage

0.45

0.40

0.35

0.30
ICC (mA)

0.25

0.20

0.15

0.10

0.05

0.00
0 2 4 6 8 10 12
VIN (V) C003

Figure 16. Current Drawn from Supply (ICC)

vs Input Voltage

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9 Power Supply Recommendations

The μA741 device is specified for operation from ±5 to ±15 V; many specifications apply from 0°C to 70°C.
Typical Characteristics presents parameters that can exhibit significant variance with regard to operating voltage
or temperature.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.

CAUTION
Supply voltages larger than ±18 V can permanently damage the device (see Absolute
Maximum Ratings).

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors reduce the coupled noise by providing low impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close as possible to the device. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

RIN
VIN +
VOUT
RG
RF

Figure 17. Operational Amplifier Schematic for Noninverting Configuration

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Layout Example (continued)

Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines RF
as possible
OFFSET N1 NC VS+
Use low-ESR, ceramic
RG bypass capacitor
GND IN1í VCC+

VIN IN1+ OUT

RIN
VCCí OFFSET N2 GND
Only needed for
dual-supply
operation
GND VS-
(or GND for single supply) VOUT Ground (GND) plane on another layer

Figure 18. Operational Amplifier Board Layout for Noninverting Configuration

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UA741CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C

UA741CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C

UA741CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C

UA741CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UA741CP

UA741CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UA741CP

UA741CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 U741

UA741CPSRE4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 U741

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UA741CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UA741CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UA741CDR SOIC D 8 2500 340.5 336.1 25.0
UA741CPSR SO PS 8 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UA741CD D SOIC 8 75 507 8 3940 4.32
UA741CP P PDIP 8 50 506 13.97 11230 4.32
UA741CPE4 P PDIP 8 50 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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