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5 views

sheet 10

Uploaded by

Mahmoud Shabaan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ELECTRONICS AND COMMUNICATION ENG. DEPT.

SPHINX UNIVERSITY
DIGITAL AND LOGIC CIRCUITS LEVEL 2 (2024-2025)

SHEET #10

A) If a 10-bit ring counter has the initial state 1010000000, determine the waveform for
each of the Q outputs.

Answer:

B) A 4-bit asynchronous binary counter is shown below. Each D flip-flop is


negative edge-triggered and has a propagation delay for 10 nanoseconds (ns).
Develop a timing diagram showing the Q output of each flip-flop, and determine the
total propagation delay time from the triggering edge of a clock pulse until a
corresponding change can occur in the state of Q3. Also determine the maximum
clock frequency at which the counter can be operated.
Answer:

For the total delay time, the effect of CLK8 or CLK16 must propagate through four flip-
flops before Q3 changes, so
t p(tot)=4 ×10 ns=40 ns
The maximum clock frequency is
1 1
f max= = =25 MHz
t p(tot) 40 ns
C) Show how an asynchronous counter with J-K flip-flops can be implemented having
a modulus of twelve with a straight binary sequence from 0000 through 1011.
Answer:
Since three flip-flops can produce a maximum of eight states, four flip-flops are required
to produce any modulus greater than eight but less than or equal to sixteen. When the
counter gets to its last state, 1011, it must recycle back to 0000 rather than going to its
normal next state of 1100, as illustrated in the following sequence chart:
Observe that Q0 and Q1 both go to 0 anyway, but Q2 and Q3 must be forced to 0 on the
twelfth clock pulse. The following figure shows the modulus-12 counter. The NAND gate
partially decodes count twelve (1100) and resets flip-flop 2 and flip-flop 3.
Thus, on the twelfth clock pulse, the counter is forced to recycle from count eleven to
count zero, as shown in the timing diagram of Figure 9–10(b). (It is in count twelve for
only a few nanoseconds before it is reset by the glitch on CLR.)

D) Show the timing diagram and determine the sequence of a 4-bit synchronous binary
up/down counter if the clock and UP/DOWN’ control inputs have waveforms as
shown below. The counter starts in the all-0s state and is positive edge-triggered.
Answer:

From these waveforms, the counter sequence is as shown in the following table.

E) Design a counter with the irregular binary count sequence shown in the next state
diagram. Use D flip-flops.
Answer:
Step 1: The state diagram is as shown. Although there are only four states, a 3-bit counter
is required to implement this sequence because the maximum binary count is seven.
Since the required sequence does not include all the possible binary states, the invalid
states (0, 3, 4, and 6) can be treated as “don’t cares” in the design. However, if the
counter should erroneously get into an invalid state, you must make sure that it goes back
to a valid state.
Step 2: The next-state table is developed from the state diagram and is given in the next
table.

Step 3: The transition table for the D flip-flop is shown in the next table.

Step 4: The D inputs are plotted on the present-state Karnaugh maps in Figure 9–31. Also
“don’t cares” can be placed in the cells corresponding to the invalid states of 000, 011,
100, and 110, as indicated by the red Xs.
Step 5: Group the 1s, taking advantage of as many of the “don’t care” states as possible
for maximum simplification. The expression for each D input taken from the maps is as
follows:

Step 6: The implementation of the counter is shown in the following figure.

An analysis shows that if the counter, by accident, gets into one of the invalid states (0, 3,
4, 6), it will always return to a valid state according to the following sequences: 0  3 
4  7, and 6  1.
F) Develop a synchronous 3-bit up/down counter with a Gray code sequence using J-K
flip-flops. The counter should count up when an UP/DOWN’ control input is 1 and
count down when the control input is 0.

Answer:
Step 1: The state diagram is shown below. The 1 or 0 beside each arrow indicates the
state of the UP/DOWN’ control input, Y.
Step 2: The next-state table is derived from the state diagram and is shown in next table.
Notice that for each present state there are two possible next states, depending on the
UP/DOWN’ control variable, Y.

Step 3: The transition table for the J-K flip-flops is repeated in next table.

Step 4: The Karnaugh maps for the J and K inputs of the flip-flops are shown in Figure
9–34. The UP/DOWN’ control input, Y, is considered one of the state variables along
with Q0, Q1, and Q2. Using the next-state table, the information in the “Flip-Flop Inputs”
column is transferred onto the maps as indicated for each present state of the counter.

Step 5: The 1s are combined in the largest possible groupings, with “don’t cares” (Xs)
used where possible. The groups are factored, and the expressions for the J and K inputs
are as follows:

Step 6: The J and K equations are implemented with combinational logic.

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