SEE 1223 – Digital Electronics

Chapter 8
Counters
and
Shift Registers

1
 Flip-Flop Applications

Applications of Flip-Flop:-
Frequency divider
Counters
Asynchronous Counter
Synchronous Counter
Register

2
 Frequency Divider

One J-K Flip-Flop is used with both inputs J and K
are connected and set at Logic ‘1’ or HIGH level
Logic ‘1’/ HIGH J Q A

CLK
K Q
CLK
A 0

TA=2TCLK thus, fA=fCLK/2

3
 Frequency Divider (continue)

When two J-K flip-flop is used
B A
1 J Q 1 J Q
CLK CLK
K Q K Q

CLK
B 0

A 0
What are the relations between fCLK, fB and fA?
4
 Counters

A counter is a register that goes through a
predetermined sequence of states upon the application
of clock pulses.
Asynchronous counters
Synchronous counters

Async. counters (or ripple counters), the clock signal
(CLK) is only used to clock the first FF. Each
successive FF is clocked by the preceding FF.

Sync. counters, the clock signal (CLK) is applied to
all FF, which means that all FF shares the same clock
signal, thus the output will change at the same time.
5
 Asynchronous counters

The async counter that counts 4 number starts from
(00,01,10,11,00)2 start counts from and back to (00)2
is called MOD-4 ripple up-counter.

MOD number is generally equal to the number of
state it counts in a complete cycle before it goes back
to the initial state.

Thus, the number of flip-flop used is depend on the
MOD of the counter and also the number of bit used
(ie; MOD-4 use 2 FF (2-bit), MOD-8 use 3 FF (3-
bit), etc..)
6
 Asynchronous Counters (continue)

State sequence table and state transition diagram
for a MOD-4 Asynchronous up-counter

Present State CLK Next State

AB ↓ AB
0
00 1 01
01 2 10 3 1
10 3 11
2
11 4 00

7
 Asynchronous Counters (continue)

MOD-4 Asynchronous up-counter
B (LSB) A (MSB)
1 J Q 1 J Q
CLK CLK
K Q K Q

CLK
B 0 1 0 1 0 1 0 1 0

A 0 0 1 1 0 0 1 1 0
Binary 0  1  2  3  0  1  2  3  0
8
 Asynchronous Counters (continue)

MOD-8 Asynchronous up-counter
C B A
1 J Q 1 J Q 1 J Q
CLK CLK CLK
K Q K Q K Q

CLK
C 0

B 0

A 0
9
 Asynchronous Counters (continue)

State sequence table and state transition diagram
Present St. Next St.
ABC CLK ABC
0
000 1 001
7 1
001 2 010
010 3 011 6 2
011 4 100
100 5 101 5 3
101 6 110 4
110 7 111
111 8 000
10
 Asynchronous Counters (continue)

Exercise:
Design a MOD-16 ripple up-counter
Design a MOD-4 ripple down-counter
Design a MOD-8 ripple down counter
Design a MOD-16 ripple down counter

In down-counter A ff changes state at each step in the sequence when

clock change from HIGH to LOW same as in up-counter. B ff change
state each time A ff goes from LOW to HIGH, C ff changes state each
time B ff goes from LOW to HIGH

11
 Asynchronous Counters (continue)

2-bit Asynchronous Binary counter
B (LSB) A (MSB)
1 J Q 1 J Q
CLK CLK
K Q K Q

CLK
B 0 1 0 1 0 1 0 1 0

A 0 1 1 0 0 1 1 0 0
Binary 0  3  2  1  0  3  2  1  0
12
 Asynchronous Counters (continue)

So far, we have design the counters with MOD number
equal to 2N, where N is the number of bit (N = 1,2,3,4….)
(also correspond to number of FF)

Thus, the counters are limited on for counting MOD-2,
MOD4, MOD-8, MOD-16 etc..

The question is how to design a MOD-5, MOD-6, MOD-7,
MOD-9 which is not a MOD-2N (MOD ≠ 2N) ?

MOD-6 counters will count from 010 (0002) to 510(1012)
and after that will recount back to 010 (0002) continuously.

13
 Asynchronous Counters

MOD-6 ripple up-counter (MOD ≠ 2N)
Present St. CLK Next St. 0
ABC ↓ ABC 5 1
000 1 001
001 2 010 4 2
010 3 011 3
011 4 100
100 5 101
101 6 000(110)
Reset the state to 0002
when 1102 is detected
14
 Asynchronous Counters (continue)

Circuit diagram for MOD-6 ripple up-counter (MOD ≠ 2N)
C B A
1 J Q 1 J Q 1 J Q
CLK CLK CLK

K Q K Q K Q
CLR CLR CLR

Detect the output at

ABC=110 to activate
CLR. NAND gate is used
to detect outputs that generates ‘1’!
15
 Chip for Asynchronous counters

74293 IC for Asynchronous counter with Reset (MR1 and MR2)
MR1 CP1
74293
MR2 CP0
Q3 Q2 Q1 Q0

Q0 Q1 Q2 Q3

1 J Q 1 J Q 1 J Q 1 J Q

CP0 CLK CLK CLK CLK

K Q K Q K Q K Q
CLR CLR CLR CLR
CP1
MR1
MR2
16
 Chip for Asynchronous counters
(continue)

Using 74293 IC to design MOD ≤ 16 asynchronous up-
counter!

Exercise:
use 74293 IC to design MOD-10 ripple up-counter

MR1 CP1
74293
MR2 CP0
Q3 Q2 Q1 Q0

1 0 1 0

17
 Chip for Asynchronous counters
(continue)

Exercise:
Determine the MOD for each configuration shown below?

MR1 CP1
74293
MR2 CP0
Q3 Q2 Q1 Q0

MR1 CP1
74293
MR2 CP0
Q3 Q2 Q1 Q0
1 0 1

18
 Chip for Asynchronous counters
(continue)

Determine the MOD for each configuration shown below?
MR1 CP1
74293
MR2 CP0
Q3 Q2 Q1 Q0

MR1 CP1 MR1 CP1

74293 74293
MR2 CP0 MR2 CP0
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

19
 Asynchronous counters

Disadvantages of Asynchronous Counters:-

Propagation delay is severe for larger MOD of counters,
especially at the MSB.
Existence of ‘glitch’ is inevitable for MOD ≠ 2N counters.
Difficult to design random counters (i.e:- to design circuit
that counts numbers in these sequence
56723156723156….)

Solution, use SYNCHRONOUS COUNTERS.

20
 Synchronous counters

For synchronous counters, all the flip-flops are using the
same CLOCK signal. Thus, the output would change
synchronously.

Procedure to design any counter circuit is clearly stated.

Procedure to design synchronous counter are as follows:-
Obtain the State Transition Diagram.
Obtain the Excitation Table using state transition table for
any particular FF. Determine number of FF used.
Obtain and simplify the function of each FF input using
K-Map.
Draw the circuit.
21
 Synchronous counters

Design a MOD-4 sync up-counter, using JK FF?
Obtain the State transition Diagram

0 00

3 1 11 01
Binary
2 10

22
 Synchronous counters
Obtain the Excitation table. Two JK FF are used.
OUTPUT TRANSITION FF INPUT
QN QN+1 J K
0  0 0 X
0  1 1 X
1  0 X 1
1  1 X 0

Present St. Next St.

A B A B JA KA JB KB
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1 23
 Synchronous counters
Obtain the simplified function using K-Map
B B
A 0 1 A 0 1
0 0 1 0 X X
JA = B KA = B
1 X X 1 0 1

B B
A 0 1 A 0 1
0 1 X 0 X 1
JB = 1 KB = 1
1 1 X 1 X 1
24
 Synchronous counters
Draw the circuit diagram

B (LSB) A (MSB)
1
JB Q JA Q
CLK CLK

KB Q KA Q

25
 Synchronous counters

Exercise:-
Design MOD-4 sync up-counter using D flip-flop.
Design MOD-8 sync up-counter using D flip-flop.
Design MOD-8 sync up-counter. Use T FF for MSB,
D FF for second bit and JK FF for LSB.
Design MOD-16 sync up-counter using T flip-flop.

26
 Synchronous counters

Design a MOD-4 sync down-counter, using JK FF?
Obtain the State transition Diagram

0 00

1 3 01 11
Binary
2 10

27
 Synchronous counters
Obtain the Excitation table. Two JK FF are used.
OUTPUT TRANSITION FF INPUT
QN QN+1 J K
0  0 0 X
0  1 1 X
1  0 X 1
1  1 X 0

Present St. Next St.

A B A B JA KA JB KB
0 0
0 1
1 0
1 1 28
 Synchronous counters
Obtain the simplified function using K-Map
B B
A 0 1 A 0 1
0 JA = 0 KA =
1 1

B B
A 0 1 A 0 1
0 JB = 0 KB =
1 1
29
 Synchronous counters
Draw the circuit diagram
JA Q A
CLK

KA Q

JB Q B
CLK

KB Q

30
 Synchronous counters

Exercise:-
Design MOD-4 sync down-counter using D flip-flop.
Design MOD-8 sync down-counter using D flip-flop.
Design MOD-8 sync down-counter. Use T FF for
MSB, D FF for second bit and JK FF for LSB.
Design MOD-16 sync down-counter using T flip-flop.

31
 Synchronous counters

Design a MOD-4 sync UP/DOWN-counter, using D FF?
Block diagram of the circuit.
#when X= 0, AB will COUNT-DOWN
#when X= 1, AB will COUNT-UP

X
SYNCHRONOUS A (MSB)
UP/DOWN
COUNTER B (LSB)

32
33
 Synchronous counters
Obtain the Excitation table. Two D FF are used.
Present St. Next St.
X A B A B DA DB
0 0 0 1 1 1 1
0 0 1 0 0 0 0
0 1 0 0 1 0 1
0 1 1 1 0 1 0
1 0 0 0 1 0 1
1 0 1 1 0 1 0
1 1 0 1 1 1 1
1 1 1 0 0 0 0
34
 Synchronous counters
Obtain the simplified function using K-Map
AB
X 00 01 11 10
0 1 0 1 0
⊕A⊕
DA = X⊕ ⊕B
1 0 1 0 1

AB
X 00 01 11 10
0 1 0 0 1 DB = B
1 1 0 0 1
35
 Synchronous counters
Draw the circuit diagram

X A
DA Q
CLK
Q

DB Q B

CLK
Q

36
 Synchronous counters

Exercise:-
Design MOD-4 sync UP/DOWN-counter using JK flip-flop.
Design MOD-8 sync UP/DOWN-counter using D flip-flop.
Design MOD-8 sync UP/DOWN-counter. Use T FF for
MSB, D FF for second bit and JK FF for LSB.
Design a circuit that counts numbers in these sequence
56723156723156…..

37
 Shift Register

Shift registers are constructed using several flip-flop,
connected in such a way to STORE and TRANSFER
digital data.

Basically, D flip-flop is used. The input data (either ‘0’ or
‘1’) is applied to the D terminal and the data will be stored
at Q during positive/negative-edge transition of the clock
pulse.
positive edge transition of CLK

1 D Q 1

Q
38
 Shift Register

One D FF is used to store 1-bit of data. Thus, the number of
flip-flop used is the same with the number of bit stored.

Shift register mean that the data in each FF can be
transferred/move to other FF upon edge triggering of the
clock signal.

Four types of data movement in shift register are:-

Parallel in / parallel out (PIPO)

Serial in / serial out (SISO)

Parallel in / serial out (PISO)

Serial in / parallel out (SIPO)
39
 Parallel in / parallel out (PIPO)

Flip-flop configuration for PIPO register.

D3 D2 D1 D0

D Q3 D Q2 D Q1 D Q0
CP CP CP CP

CLK

Q3 Q2 Q1 Q0

40
 Parallel in / parallel out (PIPO)

PIPO data movement.
CLK
D3 1 0 1 1 1
D2 0 1 0 1 0
D1 1 1 1 0 1
D0 0 0 0 1 0

Q3 0 1 0
Q2 0 0 1
Q1 0 1 1
Q0 0 0 0
41
 Parallel in / parallel out (PIPO)

74ALS147 chip for PIPO register (6-bit):-

D5 D4 D3 D2 D1 D0
CP 74ALS174
MR D5 D4 D3 D2 D1 D0

42
 Serial in / serial out (SISO)

Flip-flop connection for SISO.
1st CLK 2nd CLK 3rd CLK 4th CLK

DIN
D Q0 D Q1 D Q2 D Q3
CLK CP CP CP CP
FF0 FF1 FF2 FF3

43
 Serial in / serial out (SISO)

SISO data movement. Binary data 10000 is transferred!
1st 2nd 3rd 4th 5th
CLK
DATA-IN 1 0 0 0 0

Q0 1

Q1 1

Q2 1

Q3 1
44
 Serial in / parallel out (SIPO)

Flip-flop connection for SIPO.
1st CLK 2nd CLK 3rd CLK 4th CLK

DIN
D Q0 D Q1 D Q2 D Q3
CLK CP CP CP CP
FF0 FF1 FF2 FF3

Q0 Q1 Q2 Q3

45
 Serial in / parallel out (SIPO)

SIPO data movement. Binary data 10111 is transferred!
1st 2nd 3rd 4th 5th
CLK
DATA-IN 1 0 1 1 1

1 0 1 1
Q0

1 0 1
Q1

1 0
Q2

Q3 1
46
 Parallel in / serial out (PISO)

Flip-flop connection for PISO.
SHIFT/LOAD D0 D1 D2 D3

Serial
data
out
D Q0 D Q1 D Q2 D Q3
CLK CP CP CP CP
FF0 FF1 FF2 FF3
47
 Parallel in / serial out (PISO)

PISO data movement.
CLK
D0 0 0 1 1 1
D1 0 1 0 1 0
D2 1 1 1 0 1
D3 1 0 0 1 1

SHIFT/
LOAD

Q3 0 1 1 0 0 1
48
 Shift Register

Serial Data VS Parallel Data movement
Serial Parallel
•Movement of N-bit data require •Require only one CLK pulse to
N number of CLK pulses. Thus, transfer all N-bit of data. Thus,
the operation is slow. operation is faster than serial.
•Only one FF is required to be •Required N number of
connected at the output terminal, connection to the output
thus only one wire is required. terminal, which is proportional
to the number of bit. Thus, too
many connection is required.

49
 Shift Register Counters

A shift register counter is a shift register which output
being fed back (connected back) to the serial input. This
shift register would count the state in a unique sequence!

Two types of shift register counter:-

The Ring counter

The Johnson counter

50
 Ring Counter

Q3 Q2 Q1 Q0

51
 Ring Counter (continue)

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

Assuming the counter is initialized to Q3..Q0 = 1000, then the counting will
be as in the waveform given above
52
Ring Counter (continue)

53
54
Ring Counter (continue)

Assuming the counter is

initialized to Q3..Q0 =
1000, then the counting
will be as given above

55
 Johnson Counter
Or Twisted-ring counter

Q2 Q1 Q0

Johnson counter constructed exactly like a normal ring counter

except that the inverted output of the last flip-flop is fed back to
first flip-flop

56
 Johnson Counter (Continue)

0 1 1 1 0 0

0 0 1 1 1 0

0 0 0 1 1 1

57
Johnson Counter (Continue)

58