stm32wba54ce

STM32WBA5xxx
Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33 with

TrustZone®, FPU, Bluetooth® 5.4 and IEEE 802.15.4 radio solution
Datasheet - production data
Features
• Includes ST state-of-the-art patented
technology
• Ultra-low power radio
– 2.4 GHz radio UFQFPN32 (5 x 5 mm) UFBGA59 (5 x 5 mm)
– RF transceiver supporting Bluetooth® Low UFQFPN48 (7 x 7 mm)
Energy specification 5.4,
– Embedded regulator LDO and SMPS
IEEE 802.15.4-2015 PHY and MAC,
step-down converter supporting switch
supporting Thread, Matter and Zigbee®
on-the-fly and voltage scaling
– Proprietary protocols
• Core: Arm® 32-bit Cortex®-M33 CPU with
– RX sensitivity: -96 dBm (Bluetooth® Low
TrustZone®, MPU, DSP, and FPU running at
Energy at 1 Mbps), -97.5 dBm (IEEE
up to 100 MHz
802.15.4 at 250 kbps)
– Programmable output power, +10 dBm with • ART Accelerator: 8-Kbyte instruction cache
1 dB steps allowing 0-wait-state execution from flash
memory (frequency up to 100 MHz,
– Support for external PA
150 DMIPS)
– Isochronous channel (Auracast/Unicast),
AOA/AOD, long range • Benchmarks
– Packet traffic arbitration – 1.5 DMIPS/MHz (Drystone 2.1)
– Integrated balun to reduce BOM – 410 CoreMark® (4.10 CoreMark/MHz)
– Single crystal operation • Real time clock (RTC) with hardware calendar,
– Suitable for systems requiring compliance alarms, and calibration
with radio frequency regulations ETSI EN • Clock sources
300 328, EN 300 440, FCC CFR47 Part 15 – 32 MHz crystal oscillator
and ARIB STD-T66 – 32 kHz crystal oscillator (LSE)
• Operating conditions: – Internal low-power 32 kHz (±5%) RC
– 1.71 to 3.6 V power supply – Internal low frequency 32 kHz RC
– - 40 °C to 85/105 °C temperature range (500 ppm/ °C)
• Ultra-low power platform with – Internal 16 MHz factory trimmed RC (±1%)
FlexPowerControl – PLL for system clock, audio and ADC
– Autonomous peripherals with DMA, • Memories
functional down to Stop 1 mode – 1 MB flash memory with ECC, including
– 160 nA Standby mode (16 wake-up pins) 256 Kbytes with 100k cycles
– 0.9 µA Standby mode with 64 KB SRAM – 128 KB SRAM, including 64 KB with parity
– 6.5 µA Stop mode with 64 KB SRAM check
– 23 µA/MHz Run mode at 3.3 V – 512-byte (32 rows) OTP
– Radio: Rx 4.4 mA / Tx at 0 dBm 5.2 mA
February 2024 DS14127 Rev 5 1/149

www.st.com
STM32WBA5xxx
• Rich analog peripherals (independent supply) – Root of trust thanks to unique boot entry
– 12-bit ADC 2.5 Msps, up to 16-bit with and secure hide protection area (HDP)
hardware oversampling – SFI (secure firmware installation) thanks to
– Two ultra-low power comparators embedded RSS (root secure services)
• Communication peripherals – Secure data storage with root hardware
unique key (RHUK)
– One SAI (serial audio interface)
– Secure firmware upgrade support with
– Three UARTs (ISO 7816, IrDA, modem)
TF-M
– Two SPIs
– Two AES co-processors, including one with
– Two I2C Fm+ (1 Mbit/s), SMBus/PMBus® DPA resistance
• System peripherals – Public key accelerator, DPA resistant
– Touch sensing controller, up to 20 sensors, – HASH hardware accelerator
supporting touch key, linear, and rotary – True random number generator, NIST
touch sensors SP800-90B compliant
– One 16-bit, advanced motor control timer – 96-bit unique ID
– Three 16-bit timers – Active tampers
– One 32-bit timer – CRC calculation unit
– Two low-power 16-bit timers (available in
• General purpose input/output:
Stop mode)
– Up to 35 I/Os (most of them 5 V-tolerant)
– Two Systick timers
with interrupt capability
– Two watchdogs
• Development support
– 8-channel DMA controller, functional in
Stop mode – Serial wire debug (SWD), JTAG
• Security and cryptography • ECOPACK2 compliant packages

– Arm® TrustZone® and securable I/Os,
memories, and peripherals
– Flexible life cycle scheme with RDP and
password protected debug
Table 1. Device summary

Reference Part numbers
STM32WBA52xx STM32WBA52CE, STM32WBA52CG, STM32WBA52KE, STM32WBA52KG
STM32WBA54xx STM32WBA54KG, STM32WBA54CG, STM32WBA54KE, STM32WBA54CE
STM32WBA55xx STM32WBA55CG, STM32WBA55CE, STM32WBA55UG, STM32WBA55UE
2/149 DS14127 Rev 5

STM32WBA5xxx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Arm Cortex-M33 core with TrustZone, MPU, DSP, and FPU . . . . . . . . . . 17
3.2 ART Accelerator (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1 Flash memory protections when TrustZone is activated . . . . . . . . . . . . 21
3.5.2 FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.1 SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.2 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9.2 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 2.4 GHz RADIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11 PTA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.12 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.12.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.12.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12.3 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.12.4 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.13 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.13.1 RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.14 General-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.14.1 GPIO TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.15 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . 41
3.15.1 SYSCFG TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Contents STM32WBA5xxx
3.16 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.17 General purpose direct memory access controller (GPDMA) . . . . . . . . . 42
3.18 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.18.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 44
3.18.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 44
3.19 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 45
3.20 Analog-to-digital converter (ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.20.1 Analog-to-digital converter (ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.20.2 Temperature sensor (VSENSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.20.3 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.21 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.22 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.23 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.24 Secure advanced encryption standard hardware accelerator
(SAES) and encryption standard hardware accelerator (AES) . . . . . . . . 50
3.25 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.26 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.27 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.27.1 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.27.2 General-purpose timers (TIM2, TIM3, TIM16, TIM17) . . . . . . . . . . . . . . 54
3.27.3 Low-power timers (LPTIM1, LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.27.4 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.27.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.27.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.27.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.28 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.29 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.30 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.31 Universal synchronous/asynchronous receiver transmitter
(USART/UART) and low-power universal asynchronous
receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.31.1 USART/UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.31.2 LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.32 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.33 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.34 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4/149 DS14127 Rev 5

STM32WBA5xxx Contents
3.34.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 65
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.1 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.3 RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.4 RF IEEE802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.5 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . 89
5.3.6 Embedded reset and power control block characteristics . . . . . . . . . . . 90
5.3.7 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.8 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.9 Wake-up time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.3.19 Extended interrupt and event controller input (EXTI) characteristics . . 118
5.3.20 Wake-up pin (WKUP) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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Contents STM32WBA5xxx
5.3.21 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5.3.22 12-bit Analog-to-Digital converter (ADC4) characteristics . . . . . . . . . . 119
5.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.3.24 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.25 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.3.27 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.28 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.29 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.30 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.31 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.2 UFQFPN32 package information (A0B8) . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . 139
6.4 UFBGA59 package information (B0FS) . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6/149 DS14127 Rev 5

STM32WBA5xxx List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32WBA52xx device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. STM32WBA54/55xx device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Access status versus protection level and execution modes when TZEN = 0 . . . . . . . . . . 19
Table 5. Access status versus protection level and execution modes when TZEN = 1 . . . . . . . . . . 20
Table 6. Boot modes when TrustZone is disabled (TZEN = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Boot modes when TrustZone is enabled (TZEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Example of memory map security attribution versus SAU configuration regions . . . . . . . . 25
Table 10. Operating modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. GPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 13. GPDMA1 autonomous mode and wake-up in low-power modes . . . . . . . . . . . . . . . . . . . . 44
Table 14. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 15. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 16. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17. AES/SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 18. Timers comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 19. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 20. U(S)ART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 21. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 22. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 23. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 24. Device pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 25. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 26. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 27. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 28. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 29. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 30. Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 31. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 32. Generic RF transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 33. Generic RF receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 34. RF Bluetooth Low Energy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 35. RF transmitter Bluetooth Low Energy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 36. RF receiver Bluetooth Low Energy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 37. RF Bluetooth Low Energy power consumption for VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . 87
Table 38. RF IEEE802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 39. RF transmitter IEEE802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 40. RF receiver IEEE802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 41. RF IEEE802.15.4 power consumption for VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 42. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 43. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 44. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 45. Current consumption in Run modes on LDO, code with data processing running
from flash memory, Cache ON (1-way), prefetch OFF, VDD = 3.3 V . . . . . . . . . . . . . . . . . 92
Table 46. Current consumption in Run modes on SMPS, code with data processing running
from flash memory, Cache ON (1-way), prefetch OFF, VDD = 3.3 V . . . . . . . . . . . . . . . . . 92
DS14127 Rev 5 7/149

9
List of tables STM32WBA5xxx
Table 47. Current consumption in Run mode on LDO, with different codes running
from flash memory, Cache ON (2-way), Prefetch OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 48. Current consumption in Run mode on SMPS, with different codes running
from flash memory, Cache ON (2-way), Prefetch OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 49. Current consumption in Sleep modes, flash memory in power-down. . . . . . . . . . . . . . . . . 95
Table 50. Flash memory static power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 51. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 52. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 53. Current consumption in Standby retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 54. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 55. Peripheral typical dynamic current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 56. Low-power mode wake-up timings - LDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 57. Low-power mode wake-up timings - SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 58. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 59. Wake-up time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 60. HSE32 crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 61. HSE32 clock source requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 62. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 63. LSE clock source requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 64. LSE external clock bypass mode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 65. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 66. LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 67. LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 68. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 69. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 70. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 71. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 72. EMI characteristics for fHSE = 32 MHz and fHCLK = 100 MHz . . . . . . . . . . . . . . . . . . . . 112
Table 73. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 74. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 75. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 76. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 77. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 78. Output AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 79. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 80. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 81. WKUP input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 82. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 83. 12-bit ADC4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 84. Maximum RAIN for 12-bit ADC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 85. 12-bit ADC4 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 86. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 87. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 88. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 89. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 90. IWDG min/max timeout period at 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 91. WWDG min/max timeout value at 100 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 92. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 93. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 94. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 95. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 96. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8/149 DS14127 Rev 5

STM32WBA5xxx List of tables
Table 97. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 98. UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 99. UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 100. UFBGA59 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 101. UFBGA59 - Recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 102. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 103. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
DS14127 Rev 5 9/149

9
List of figures STM32WBA5xxx
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. 2.4 GHz RADIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3. Power supply overview with SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. Power supply overview with LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 6. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. UFQFPN32 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 8. UFQFPN48 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 9. UFQFPN48 SMPS pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 10. UFBGA59 SMPS ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 13. Power supply scheme with LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 14. Power supply scheme with SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 15. Power supply scheme with SMPS (high RF power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 16. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 17. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 18. LSE typical application with a crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 19. LSE external square clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 20. LSE external sinusoidal clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 21. I/O input characteristics (all I/Os except PH3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 22. Output AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 24. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 25. Typical connection diagram when using the ADC
with FT/TT pins featuring analog switch function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 26. USART timing diagram in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 27. USART timing diagram in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 28. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 29. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 30. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 31. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 32. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 33. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 34. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 35. UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 36. UFQFPN32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 37. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 38. UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 39. UFBGA59 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 40. UFBGA59 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10/149 DS14127 Rev 5

STM32WBA5xxx Introduction
1 Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32WBA5xxx microcontrollers, based on Arm® cores(a). It must be read in
conjunction with the reference manual (RM0493), available from the STMicroelectronics
website www.st.com.
Throughout the whole document TBD indicates a value to be defined.
For information on the device errata with respect to the datasheet and reference manual
refer to the STM32WBA5xxx errata sheet (ES0592), available from the STMicroelectronics
website www.st.com.
For information on the Arm® Cortex®-M33 core, refer to the Cortex®-M33 Technical
Reference Manual, available on the www.arm.com website.
For information on Bluetooth®, refer to www.bluetooth.com.
.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS14127 Rev 5 11/149

65
Description STM32WBA5xxx
2 Description
The STM32WBA5xxx multiprotocol wireless and ultra-low power devices embed a powerful
and ultra-low power radio compliant with the Bluetooth® SIG Low Energy specification 5.4.
They operate at a frequency of up to 100 MHz.
The devices integrate a 2.4 GHz RADIO supporting Bluetooth Low Energy, and make
possible to use proprietary protocols.
The STM32WBA5xxx are based on a high-performance Arm Cortex-M33 32-bit RISC core,
featuring a single-precision floating-point unit (FPU), supporting all the Arm single-precision
data-processing instructions and all the data types. This core also implements a full set of
DSP (digital signal processing) instructions and a memory protection unit (MPU) that
enhances the application security.
The devices embed high-speed memories (up to 1 Mbyte of flash memory and up to
128 Kbytes of SRAM), an extensive range of enhanced I/Os and peripherals connected to
AHB and APB buses on the 32-bit multi-AHB bus matrix.
The devices offer security foundation compliant with the TBSA (trusted-based security
architecture) requirements from Arm. It embeds the necessary security features to
implement a secure boot, secure data storage, and secure firmware update. Besides these
capabilities, the devices incorporate a secure firmware installation feature that allows the
customer to secure the provisioning of the code during its production. A flexible life cycle is
managed thanks to multiple levels readout protection and debug unlock with password.
Firmware hardware isolation is supported thanks to securable peripherals, memories and
I/Os, and privilege configuration of peripherals and memories.
Several protection mechanisms are available for embedded flash memory and SRAM:
readout protection, write protection, secure, and hide protection areas.
The devices embed several peripherals reinforcing security: a fast AES coprocessor, a
secure AES coprocessor with DPA resistance and hardware unique key that can be shared
by hardware with fast AES, a PKA (public key accelerator) with DPA resistance, a HASH
hardware accelerator, and a true random number generator.
Active tamper detection and protection against transient perturbation attacks, is achieved
thanks to several internal monitoring generating secret data erase in case of attack. This
helps to fit the PCI requirements for point of sales applications.
Hardware semaphores enable the synchronization between software processes.
The devices offer one 12-bit ADC (2.5 Msps), two comparators, a low-power RTC, one
32-bit general-purpose timer, one 16-bit PWM timer for motor control, three 16-bit general-
purpose timers, and two 16-bit low-power timers. They also feature standard and advanced
communication interfaces, namely two I2Cs, two SPIs, one SAI, two USARTs, and one
low-power UART. The feature set is product-dependent.
The STM32WBA5xxx operate in the -40 °C to 105 °C (120 °C junction) temperature range
from a 1.71 to 3.6 V power supply.
The design of low-power applications is enabled by a comprehensive set of power-saving
modes.
12/149 DS14127 Rev 5

STM32WBA5xxx Description
Many peripherals (including radio, communication, analog, and timer peripherals) can be
functional and autonomous in Stop mode with direct memory access thanks to BAM
(background autonomous mode) support.
Some independent power supplies are supported, like an analog independent supply input
for ADC and comparators, and radio dedicated supply inputs for the 2.4 GHz RADIO.
The STM32WBA5xxx devices offer three packages, up to 59 pins, with or without SMPS.
Table 2. STM32WBA52xx device features and peripheral counts

STM32 STM32 STM32 STM32
Feature
WBA52CG WBA52KG WBA52CE WBA52KE
Flash memory density 1024 KB 512 KB

SRAM1 64 KB 32 KB
SRAM density
SRAM2 64 KB
Bluetooth Low Energy Yes
802.15.4 No
SMPS No
PTA No
External PA support No
BLE AoA, AoD support No
Real time clock (RTC) Yes
Backup registers 32 x 32 bits
Advanced control 1 (16-bit)
General purpose 1 (32-bit) + 3 (16-bit)
Timers Low power 2 (16-bit)
SysTick 2
Watchdog (independent, window) 2
SPI 2
I2C 2
Communication
SAI No
interfaces
USART 2
LPUART 1
Tamper pins (active tampers)(1) 5 (4) 3 (2) 5 (4) 3 (2)
Wake-up pins 15 8 15 8
GPIOs 35 20 35 20
Capacitive sensing (channels) 20 12 20 12
12-bit ADC 1 (9 channels) 1 (8 channels) 1 (9 channels) 1 (8 channels)
True random number generator Yes
Analog comparators No
SAES, AES Yes
DS14127 Rev 5 13/149

65
Table 2. STM32WBA52xx device features and peripheral counts (continued)

STM32 STM32 STM32 STM32
Feature
WBA52CG WBA52KG WBA52CE WBA52KE
Public key accelerator (PKA) Yes

HASH Yes
Maximum CPU frequency 100 MHz
Ambient: -40 to 85 °C and -40 to 105 °C
Operating temperature
Junction: -40 to 105 °C and -40 to 120 °C
Operating voltage 1.71 to 3.6 V
Package UFQFPN48 UFQFPN32 UFQFPN48 UFQFPN32
1. Active tampers in output sharing mode (one output shared by all inputs).
Table 3. STM32WBA54/55xx device features and peripheral counts

STM32WBA54KG
STM32WBA54CG
STM32WBA55CG
STM32WBA55UG
STM32WBA54KE
STM32WBA54CE
STM32WBA55CE
STM32WBA55UE
Feature
Flash memory density (Kbytes) 1024 512 1024 512 1024 512 1024 512
SRAM1 64 KB 32 KB 64 KB 32 KB 64 KB 32 KB 64 KB 32 KB
SRAM density
SRAM2 64 KB
Bluetooth Low Energy Yes
802.15.4 Yes
SMPS No Yes
PTA Yes
External PA support Yes
BLE AoA, AoD support Yes
Real time clock (RTC) Yes
Backup registers 32 x 32-bit
Advanced control 1 (16-bit)
General purpose 1 (32-bit) + 3 (16-bit)
Low power 2 (16-bit)
Timers
SysTick 2
Watchdog
(independent, 2
window)
14/149 DS14127 Rev 5

STM32WBA5xxx Description
Table 3. STM32WBA54/55xx device features and peripheral counts (continued)
STM32WBA54KG
STM32WBA54CG
STM32WBA55CG
STM32WBA55UG
STM32WBA54KE
STM32WBA54CE
STM32WBA55CE
STM32WBA55UE
Feature
SPI 2
I2C 2
Communication
SAI 1
interfaces
USART 2
LPUART 1
(1)
Tamper pins (active tampers) 3 (2) 6 (5)
Wake-up pins 8 15 14 16
GPIOs 20 35 31 35
Capacitive sensing (channels) 12 20 16 20
12-bit ADC 1 (8 channels) 1 (9 channels) 1 (8 channels) 1 (10 channels)
Analog comparator 2
True random number generator Yes
SAES, AES Yes
Public key accelerator (PKA) Yes
HASH Yes
Maximum CPU frequency 100 MHz
Ambient operating temperature:-40 to 85 °C and -40 to 105 °C
Operating temperature
Junction temperature: -40 to 105 °C and -40 to 120 °C
Operating voltage 1.71 to 3.6 V
Package UFQFPN32 UFQFPN48 UFBGA59
1. Active tampers in output sharing mode (one output shared by all inputs).
DS14127 Rev 5 15/149

65
Figure 1 shows the general block diagram of the devices (some blocks are not available on
some versions).
Figure 1. Block diagram
DBGMCU
AHB5 32 MHz
Sequence SRAM
JTAG/SWD
2.4 GHz RADIO VDDRF domain

Arm Cortex-M33 retention
NVIC
(FPU, DSP) TXRX 2.4 GHz HSE32

MPU, SAU SRAM retention RF 32 MHz
PTACONV
C-BUS S-BUS
ICACHE VDD domain
SRAM2
with parity and retention LSI1
IWDG PLL HSI16
FLASH SRAM1
with ECC with retention
LSI2
Power supply
RAMCFG MCPBB5 BOR/PVD
RTC
GPDMA1 LSE
AHB 1 & 2 100 MHz
MCPBB2 Power
8-channel TAMP
management
GPIO Ports Temp oC
MCPBB1 regulator / SMPS
A, B, C, H sensor
SYSCFG
HSEM GTZC-TZSC
COMP
APB7 100 MHz

LPTIM1
True RNG GTZC_TZIC VDDA domain
I2C3 COMP1 COMP2

CRC PKA
ADC 12-bit
LPUART1
AES HASH 2.5 Msps
SPI3 ADC4
SAES
AHB4 100 MHz

TIM1 APB1 & 2 100 MHz RCC
USART1
TIM2 LPTIM2 PWR
USART2
TIM3 WWDG EXTI
SPI1
TIM16 TSC
VDD power domain
I2C1 VDDA power domain
TIM17 SAI1
VDDRF power domain
16/149 DS14127 Rev 5

STM32WBA5xxx Functional overview
3 Functional overview
3.1 Arm Cortex-M33 core with TrustZone, MPU, DSP, and FPU
The Cortex-M33 with TrustZone, MPU, DSP and FPU is a highly energy-efficient processor
designed for microcontrollers and deeply embedded applications, especially those requiring
efficient security.
The Cortex-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. It features:
• Arm TrustZone technology, using the Armv8-M main extension supporting secure and
non-secure states
• MPUs (memory protection units), supporting up to 16 regions for secure and
non-secure applications
• Configurable SAU (secure attribute unit) supporting up to eight memory regions as
secure or non-secure
• Floating-point arithmetic functionality, with support for single precision arithmetic
The processor supports a set of DSP instructions for efficient signal processing and
complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
• System AHB (S-AHB) bus: used for instruction fetch and data access to the memory-
mapped SRAM, peripheral, and Vendor_SYS regions of the Armv8-M memory map.
• Code AHB (C-AHB) bus: used for instruction fetch and data access to the code region
of the Armv8-M memory map.
DS14127 Rev 5 17/149

65
Functional overview STM32WBA5xxx
3.2 ART Accelerator (ICACHE)

The ICACHE (instruction cache) is introduced on C-AHB code bus of Cortex-M33 processor
to improve performance when fetching instruction (or data) from internal memories.
ICACHE offers the following features:
• Multi-bus interface:
– Slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
– Master1 port performing refill requests to internal flash memory
– Master2 port performing refill requests to internal SRAM memories
– Second slave port dedicated to ICACHE registers access
• Close to 0 wait-states instructions/data access performance:
– 0 wait-state on cache hit
– Hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– Critical-word-first refill policy, minimizing processor stalls on cache miss
– Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– Dual master ports to decouple internal flash memory and SRAM traffic, on fast and
slow buses, respectively; also minimizing impact on interrupt latency
– Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– Performance monitoring by means of a hit counter and a miss counter
• Extension of cacheable region beyond the code memory space, by means of address
remapping logic enabling the definition of four regions
• Power consumption intrinsically reduced (more accesses to cache memory rather than
to bigger main memories), even improved by configuring ICACHE as direct mapped
(rather than the default two-ways set-associative mode)
• TrustZone security support
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising
3.3 Memory protection unit

The MPU is used to manage the CPU accesses to the memory and to prevent tasks to
accidentally corrupt the memory or the resources used by other active tasks. This memory
area is organized into up to 16 protected areas. The MPU regions and registers are banked
across secure and non-secure states.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location prohibited by the MPU,
the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
18/149 DS14127 Rev 5

3.4 Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1) and the slaves
(flash memory, SRAMs, AHB, and APB) peripherals. It also ensures a seamless and
efficient operation even when several peripherals work simultaneously.
3.5 Embedded flash memory

The devices feature up to 1 Mbyte of embedded flash memory, available to store programs
and data. This memory supports 10000 cycles, and up to 100000 cycles on 32 pages
(256 Kbytes).
A 128-bit instruction prefetch is implemented and can optionally be enabled.
The flash memory contains up to 128 pages of 8 Kbytes, and embeds a 512-byte OTP (one
time programmable) for user data.
The configuration of flexible protections is possible thanks to the option bytes:
• RDP (readout protection) to protect the whole memory, has four levels of protection
available (see Table 4 and Table 5):
– Level 0: no readout protection
– Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the non-secure flash
memory are possible. The debug access to secure area is prohibited, that to
non-secure area remains possible.
– Level 1: memory readout protection
The flash memory cannot be read from or written to if either the debug features
are connected or the boot in SRAM or bootloader are selected. If TrustZone is
enabled, the non-secure debug is possible and the boot in SRAM is not possible.
Regressions from Level 1 to lower levels can be protected by password
authentication.
– Level 2: chip readout protection
The debug features, the boot in RAM and the bootloader selection are disabled. A
secure secret key can be configured in the secure options to allow the regression
capability from Level 2 to Level 1. By default (key not configured), this Level 2
selection is irreversible and JTAG/SWD interfaces are disabled. If the secret key
was previously configured in lower RDP levels, the device enables the RDP
regression from Level 2 to Level 1 after password authentication through
JTAG/SWD interface.
• Write protection (WRP) to protect areas against erasing and programming. Two areas
can be selected with 8-Kbyte granularity.
Table 4. Access status versus protection level and execution modes when TZEN = 0
User execution
RDP Debug/boot from RAM/bootloader(1)
Area (boot from flash memory)
level
Read Write Erase Read Write Erase
1 Yes Yes Yes No No No(4)

Flash main memory
2 Yes Yes Yes N/A N/A N/A
DS14127 Rev 5 19/149

65
Table 4. Access status versus protection level and execution modes when TZEN = 0 (continued)
User execution
RDP Debug/boot from RAM/bootloader(1)
level
1 Yes No No Yes No No
System memory (2)
2 Yes No No N/A N/A N/A
1 Yes Yes(4) N/A Yes Yes(4) N/A
Option bytes(3)
2 Yes No N/A N/A N/A N/A
1 Yes Yes(5) N/A Yes Yes (5)
N/A
OTP
2 Yes Yes(5) N/A N/A N/A N/A
1 Yes Yes N/A No No N/A(6)
Backup registers
2 Yes Yes N/A N/A N/A N/A
1 Yes Yes N/A No No N/A(7)
SRAM2
1. When the protection level 2 is active, the debug port, the boot from RAM, and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. Option bytes are accessible only through the flash memory interface registers and OPSTRT bit.
4. The flash main memory is erased when the RDP option byte changes from level 1 to level 0.
5. OTP can be written only once.
6. The backup registers are erased when RDP changes from level 1 to level 0.
7. All SRAMs are erased when RDP changes from level 1 to level 0.
Table 5. Access status versus protection level and execution modes when TZEN = 1
User execution
RDP Debug/bootloader(1)
level
(2) (2)
0.5 Yes Yes Yes Yes Yes Yes(2)
Flash main memory 1 Yes Yes Yes No No No(5)
2 Yes Yes Yes N/A N/A N/A
0.5 Yes No No Yes No No
System memory (3) 1 Yes No No Yes No No
2 Yes No No N/A N/A N/A
0.5 Yes Yes(5) N/A Yes Yes (5) N/A
(4) (5) (5)
Option bytes 1 Yes Yes N/A Yes Yes N/A
2 Yes No N/A N/A N/A N/A
0.5 Yes Yes(6) N/A Yes Yes(6) N/A
OTP 1 Yes Yes(6) N/A Yes Yes(6) N/A
(6)
20/149 DS14127 Rev 5

Table 5. Access status versus protection level and execution modes when TZEN = 1 (continued)
User execution
RDP Debug/bootloader(1)
level
(2) (2)
0.5 Yes Yes N/A Yes Yes N/A(7)
Backup registers 1 Yes Yes N/A No No N/A(7)
0.5 Yes Yes N/A Yes(2) Yes (2)
N/A(8)
SRAM2 1 Yes Yes N/A No No N/A(8)
1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.
2. Depends upon TrustZone security access rights.
3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
4. Option bytes are accessible only through the flash registers interface and OPSTRT bit.
5. The flash main memory is erased when the RDP option byte regresses from level 1 to level 0.
6. OTP can be written only once.
7. The backup registers are erased when RDP changes from level 1 to level 0.5 or level 0.
8. All SRAMs are erased when RDP changes from level 1 to level 0.5 or level 0.
The whole nonvolatile memory embeds the ECC (error correction code) feature supporting:
• single-error detection and correction
• double-error detection
• ECC fail address report
3.5.1 Flash memory protections when TrustZone is activated

When the TrustZone security is enabled through option bytes, the whole flash memory is
secure after reset and the following protections are available:
• Non volatile watermark-based secure flash memory area
The secure area can be accessed only in Secure mode. One area can be selected with
a page granularity.
• Secure hide protection area (HDP)
It is part of the flash memory secure area and can be protected to deny access to any
data read, write, and instruction fetch. For example, a software code in the secure flash
memory hide protection area can be executed only once, and deny any further access
to this area until the next system reset. One area can be selected at the beginning of
the secure area.
• Volatile block-based secure flash memory area
Each page can be programmed on-the-fly as secure or non-secure.
3.5.2 FLASH privilege protection

Each flash memory page can be programmed on-the-fly as privileged or unprivileged.
DS14127 Rev 5 21/149

65
3.6 Embedded SRAMs

SRAM1 and SRAM2 are the main SRAMs embedded in the devices, each with specific
features. Both can be used for peripherals background autonomous mode (BAM).
These SRAMs can be powered down in Stop mode to reduce consumption:
• SRAM1: one up to 64-Kbyte block, can be retained in Standby mode
• SRAM2: one 64-Kbyte block with parity, can be retained in Standby mode.
3.6.1 SRAMs TrustZone security

When TrustZone security is enabled, SRAMs are secure after reset. SRAM1 and SRAM2
can be programmed as secure or non-secure by blocks, using the MPCBB (block-based
memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes.
3.6.2 SRAMs privilege protection

The SRAM1 and SRAM2 can be programmed as privileged or non-privileged by blocks,
using the MPCBB. The granularity of SRAM block-based privilege is a page of 512 bytes.
3.7 Boot modes

At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0] (x = 0, 1), and
SECBOOTADD0[24:0] option bytes are used to select the boot memory address. This
includes:
• Boot from any address in user flash memory
• Boot from system memory bootloader
• Boot from any address in embedded SRAM
• Boot from RSS (root security services)
The BOOT0 value comes from the PH3-BOOT0 pin or from an option bit, depending upon
the value of a user option bit to free the GPIO pad if needed.
The bootloader is located in the system memory, programmed by ST during production. It is
used to program the flash memory by using USART, I2C or SPI in device mode.
The bootloader is available on all devices. Refer to AN2606 STM32 microcontroller system
memory boot mode, available on www.st.com, for more details.
The RSS are embedded in the flash memory area named secure information block,
programmed during ST production. For example, the RSS enables the SFI (secure firmware
installation), thanks to the RSSe (RSS extension firmware).
This feature allows the customers to produce the confidentiality of the firmware to be
provisioned into the STM32, when production is subcontracted to untrusted third party.
The RSS is available on all devices, after enabling the TrustZone through the TZEN option
bit. Refer to AN4992 STM32 MCUs secure firmware install (SFI) overview, available on
www.st.com, for more details.
Refer to Table 6 and Table 7, respectively, for boot modes with TrustZone disabled and
enabled.
22/149 DS14127 Rev 5

Table 6. Boot modes when TrustZone is disabled (TZEN = 0)

nBOOT0 nSWBOOT0 Boot address
BOOT0 ST programmed
FLASH_ FLASH_ option-bytes Boot area
pin PH3 default value
OPTR[27] OPTR[26] selection
Boot address defined by

Flash memory:
- 0 1 NSBOOTADD0[24:0] user option bytes
0x08000 000
NSBOOTADD0[24:0]
System bootloader:
- 1 1 NSBOOTADD1[24:0] user option bytes
0x0BF8 8000
NSBOOTADD1[24:0]
Flash memory:
1 - 0 NSBOOTADD0[24:0] user option bytes
0x0800 0000
NSBOOTADD0[24:0]
System bootloader:
0 - 0 NSBOOTADD1[24:0] user option bytes
0x0BF8 8000
NSBOOTADD1[24:0]
When TrustZone is enabled by setting the TZEN option bit, the boot space must be in the
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot
options are ignored.
Table 7. Boot modes when TrustZone is enabled (TZEN = 1)

RSS command
BOOT_LOCK
nBOOT0 BOOT0 nSWBOOT0 Boot address ST

FLASH_ pin FLASH_ option bytes Boot area programmed
OPTR[27] PH3 OPTR[26] selection default value
Secure boot address defined

SECBOOT- Flash memory:
- 0 1 0 by user option bytes
ADD0[24:0] 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
- 1 1 0 N/A RSS
0x0FF8 0000
0 SECBOOT- Flash memory:
1 - 0 0 by user option bytes
ADD0[24:0] 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
0 - 0 0 N/A RSS
0x0FF8 0000
RSS:
- - - ≠0 N/A RSS
0x0FF8 0000
SECBOOT- Flash memory:
1 - - - - by user option bytes
ADD0[24:0] 0x0C00 0000
SECBOOTADD0[24:0]
DS14127 Rev 5 23/149

65
The boot address option bytes allow any boot memory address to be programmed. The
allowed address space depends on the flash memory RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or higher, the default boot address is forced either in secure or non-secure
flash memory, depending on TrustZone security option, as detailed in Table 8.
Table 8. Boot space versus RDP protection

RDP TZEN = 1 TZEN = 0
0 Any boot address Any boot address

0.5 N/A
1 Boot address only in RSS or secure flash memory: Any boot address
0x0C00 0000 - 0x0C0F FFFF.
Boot address only in flash memory:
Otherwise, forced boot address is 0x0FF8 0000
2 0x0800 0000 - 0x080F FFFF.
Otherwise, forced boot address is: 0x0800 0000
3.8 Global TrustZone controller (GTZC)

GTZC is used to configure TrustZone and privileged attributes within the full system.
The GTZC includes different sub-blocks:
• TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. The
TZSC block informs some peripherals (such as RCC or GPIO) about the secure status
of each securable peripheral.
• TZIC: TrustZone illegal access controller
This sub-block gathers all security illegal access events in the system and generates a
secure interrupt towards NVIC.
• MPCBB: block-based memory protection controller
This sub-block controls secure states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral configures the internal RAM in a TrustZone system
product having segmented SRAM with programmable-security and privileged
attributes.
The GTZC main features are:
• Independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
• Secure and non-secure access supported for privileged/unprivileged part of TZSC
• Set of registers to define product security settings:
– Secure/privilege access mode for securable peripherals
– Secure/privilege access mode for securable memories
– Illegal access interrupt notification
3.9 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TZEN option bit in the FLASH_OPTR register activates the TrustZone security.
24/149 DS14127 Rev 5

When TrustZone is enabled, the SAU (security attribution unit) and IDAU (implementation
defined attribution unit) define the access permissions based on secure and non-secure
state.
• SAU: up to eight SAU configurable regions are available for security attribution.
• IDAU: provides a first memory partition as non-secure or non-secure callable attributes.
It is then combined with the results from the SAU security attribution, and the higher
security state is selected.
Based on IDAU security attribution, the flash memory, system SRAM and peripheral
memory space is aliased twice for secure and non-secure states.
Table 9 shows an example of typical SAU regions configuration based on IDAU regions.
Table 9. Example of memory map security attribution versus SAU configuration regions
SAU security
IDAU security Final security
Region description Address range attribution typical
attribution attribution
configuration
0x0000 0000
Reserved Non-secure Secure or non-secure or Non-secure callable
0x07FF FFFF
0x0800 0000
Non-secure
Code 0x0BFF FFFF
flash memory and SRAM 0x0C00 0000
Non-secure callable Secure or NSC
0x0FFF FFFF
0x1000 0000
0x17FF FFFF
Reserved Non-secure
0x1800 0000
Non-secure
0x1FFF FFFF
0x2000 0000
Non-secure
0x2FFF FFFF
SRAM
0x3000_0000
Non-secure callable Secure or Non-secure callable
0x3FFF FFFF
0x4000 0000
Non-secure
0x4FFF FFFF
Peripherals
0x5000 0000
Non-secure callable Secure or Non-secure callable
0x5FFF FFFF
0x6000 0000
Reserved Non-secure Secure or non-secure or Non-secure callable
0xDFFF FFFF
3.9.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be securable or TrustZone-aware:
• Securable: peripheral protected by an AHB/APB firewall gate controlled from TZSC to
define security properties.
• TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior, such as a subset of registers being secure.
DS14127 Rev 5 25/149

65
3.9.2 Default TrustZone security state

The default system security state is detailed below:
• CPU: Cortex-M33 is in secure state after reset. The boot address must be in secure
area.
• Memory map: SAU is fully secure after reset. Consequently, all memory map is fully
secure. Up to eight SAU configurable regions are available for security attribution.
• Flash memory:
– Flash memory security area is defined by watermark user options.
– Flash memory block based area is non-secure after reset.
• SRAMs: all are secure after reset, MPCBB is secure.
• Peripherals
– Securable peripherals are non-secure after reset.
– TrustZone-aware peripherals are non-secure after reset.
• All GPIOs are secure after reset.
• Interrupts (NVIC): all interrupts are secure after reset. NVIC is banked for secure and
non-secure state.
• TZIC: all illegal access interrupts are disabled after reset.
3.10 2.4 GHz RADIO

The 2.4 GHz RADIO is ultra-low power, operating in the 2.4 GHz ISM band. It provides
Bluetooth LE 1 Mbps coded, 1 Mbps and 2 Mbps non-coded GFSK, and IEEE802.15.4
125 kbps and 250 kbps modulation. It is compliant with the Bluetooth 5.4, Zigbee, Thread,
Ant+ specifications and radio regulations including ETSI EN 300 328, EN 300 440, EN 301
489-17, ARIB STD-T66, FCC CFR47 part 15 section 15.205, 15.209, 15.247 and 15.249, IC
RSS-139 and RSS-210.
The 2.4 GHz RADIO supports the following features:
• Radio protocol:
– Bluetooth Low Energy
– IEEE802.15.4
– Proprietary protocols
– Concurrent mode
• Bluetooth AoA/AoD
• External PA support
• Packet traffic arbitration
26/149 DS14127 Rev 5

Figure 2. 2.4 GHz RADIO block diagram
AHB bus
VDDRF
I
Rx VDDANA
Demodulator BPF LNA
RADIO interrupt Q
External PA control
IQ Matching RF
AoA/AoD Tx
Low layer protocol Modulator generator
antenna control
PTA interface LF PA VDDRFPA

2.4 GHz RADIO VDDHPA
kernel clock Sleep timer
PFD/CP DIV
Sleep timer clock
RXTXRAM SEQRAM VSSRF

2.4 GHz RADIO
2.4 GHz RADIO RF clock
VDDANA only available on packages with SMPS. On LDO packages VDDANA is double bonded with VDDRF.
In QFN packages VSSRF is connected to exposed pad.
3.11 PTA interface

The PTA interface enables packet traffic arbitration with other connectivity devices, such as
WiFi®. Its main features are:
• based on IEEE802.15.2 standard
• supports both grant and deny signaling
• supports from 1- up to 4-wire protocols
• programmable transmit receive PTA_STATUS polarity
• programmable priority polarity
• programmable grant polarity
• programmable active polarity
• programmable PTA_ACTIVE timing
• programmable PTA_STATUS time multiplexed priority timing.
• programmable transmit packet abort
3.12 Power supply management

The power controller (PWR) main features are:
• Power supplies and supply domains
– Core domain (VCORE)
– VDD and backup domain
– Analog domain (VDDA)
– SMPS power stage (VDDSMPS, available only on SMPS packages)
– VDDRF for 2.4 GHz RADIO
• System supply voltage regulation
– SMPS step-down converter
– Voltage regulator (LDO)
DS14127 Rev 5 27/149

65
• Power supply supervision

– BOR monitor
– PVD monitor
• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• TrustZone security and privilege protection
3.12.1 Power supply schemes

The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V (functionality guaranteed down to VBORx minimum value)
External power supply for the I/Os, the internal regulator, the system analog such as
reset, power management, and internal clocks and the backup domain. It is provided
externally through the VDD pins. VDDRF must be connected to the same supply used
for VDD.
• VDDA = 1.62 V to 3.6 V
External analog power supply for ADC. The voltage level is independent from the VDD
voltage and must be connected to VDD (preferably) or to VSS pin when this peripheral
is not used.
• VDDSMPS = 1.71 V to 3.6 V
External power supply for the SMPS step down converter. It is provided externally
through VDDSMPS supply pin and must be connected to the same supply as VDD.
• VLXSMPS is the switched SMPS step down converter output.
Note: The SMPS power supply pins are available only on packages with SMPS step-down
converter option.
• VDDRF = 1.71 V to 3.6 V
External power supply for the 2.4 GHz RADIO, it must be connected to the same
supply used for VDD.
• VDDANA = 0 V to 3.6 V (must be ≥ 1.2 V for 2.4 GHz RADIO operation)
External power supply for the 2.4 GHz RADIO, it can be connected to VDD11.
Note: VDDANA pin is available only on packages with SMPS step-down converter option.
• VDDRFPA = 0 V to 3.6 V (must be ≥ 1.2 V for 2.4 GHz RADIO operation)
External power supply for the 2.4 GHz RADIO and power amplifier regulator. The
maximum reachable transmit output power is determined by VDDRFPA supply level.
The devices embed two regulators: one LDO and one SMPS in parallel to provide the
VCORE supply for digital peripherals, SRAM1, SRAM2, 2.4 GHz RADIO, and embedded
flash memory. The LDO generates this voltage on VCAP pin connected to an external
capacitor of 4.7 μF (typical). The SMPS generates this voltage on VDD11 pin, with a total
external capacitor of 4.7 μF (typical)..
Both regulators can provide two different voltages (voltage scaling), and can operate in Stop
modes.
It is possible to switch from SMPS to LDO and vice-versa on-the-fly.
28/149 DS14127 Rev 5

The VDDHPA pin is provided to connect to an external capacitor (typical value 470 nF).
Figure 3. Power supply overview with SMPS
RADIO domain
VDDANA
VDDRF
VDDRFPA 2.4 GHz RADIO
VDDHPA
VSSRF(2)
VDDA domain
VDDA ADC
Comparators
VSSA(2)
VDD domain
VDD I/O ring
Reset block
Temperature sensor
VCORE domain
1 x PLL
Internal RC oscillators Core
Standby circuitry
SRAM1
VDD (Wakeup logic, IWDG) SRAM2
Voltage regulator
LDO regulator Digital
VCORE peripherals
VDD11
VLXSMPS SMPS regulator
VDDSMPS
VSSSMPS Flash memory
Backup domain
VDD LSE crystal 32 kHz oscillator
RTC, TAMP, Backup registers,
VSS RCC_BDCR1.
(Exposed pad)(1)
(1) Exposed pad is only available on QFN packages.
(2) Not available on all packages. When not available connected to VSS pin.
MS55615V1
Caution: When SMPS devices are used in an LDO application, without inductor between VLXSMPS
and VDD11, VDDSMPS and VLXSMPS must be connected to ground.
DS14127 Rev 5 29/149

65
Figure 4. Power supply overview with LDO
RADIO domain
VDDRF 2.4 GHz RADIO

VDDRFPA
VDDHPA
VDDA domain
VDDA ADC
Comparators
VDD domain
VDD VCORE domain
I/O ring
Reset block Core
Temperature sensor
1 x PLL SRAM1
Internal RC oscillators SRAM2
Standby circuitry
VDD Digital
(Wakeup logic, IWDG) VCORE peripherals
VCAP
LDO regulator
Flash memory
Backup domain
VDD LSE crystal 32 kHz oscillator
RTC, TAMP, Backup registers, RCC_BDCR.
VSS
(Exposed pad)
MS55616V1
During power-up and power-down phases, respect the following requirements:

• When VDD is below 1 V, other power supplies (namely VDDA) must remain below
VDD + 300 mV.
• When VDD is equal to or above 1 V, other power supplies are independent.
• During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the
power-down transient phase.
30/149 DS14127 Rev 5

Figure 5. Power-up/down sequence

V
3.6
VDDX(1)
VDD
VBOR0
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
1. VDDX refers to power supply VDDA.
3.12.2 Power supply supervisor

The devices have an integrated ultra-low power BOR (brownout reset) active in all modes.
The BOR ensures proper operation after power-on and during power-down. The devices
remain in reset mode when the monitored supply voltage VDD is below a specified
threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded PVD (programmable voltage
detector) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below and/or rises above the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
The devices support dynamic voltage scaling to optimize its power consumption in Run
mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
• Range 1 (VCORE = 1.2 V) with CPU and peripherals running at up to 100 MHz
• Range 2 (VCORE = 0.9 V) with CPU and peripherals running at up to 16 MHz
Low-power modes
The devices support different low-power modes to achieve the best compromise between
low-power consumption, startup time, available peripherals, and available wake-up sources.
DS14127 Rev 5 31/149

65
32/149
Functional overview
Table 10. Operating modes overview
Flash
Mode Regulator(1) CPU SRAM Clocks DMA and peripherals(2) Wake-up source
memory
Range 1 All
Run Yes ON(3) ON Any N/A
Range 2 All except 2.4 GHz RADIO
Range 1 All
Sleep No ON ON(4) Any Any interrupt or event
Range 2 All except 2.4 GHz RADIO
BOR, PVD, RTC, TAMP, IWDG, Reset pin, all I/Os, BOR, PVD,
SLEEP_TIMER, RTC, TAMP, IWDG, SLEEP_TIMER,
ADC4(7) (temperature sensor), ADC4 (temperature sensor),
USARTx (x = 1, 2)(8), USARTx (x = 1, 2),
LPUART1, LPUART1,
LSE SPIx (x = 1, 2)(9),
Range 1 SPIx (x = 1, 2),
Stop 0 No OFF ON(5) LSI I2Cx (x = 1, 2)(10),
DS14127 Rev 5
(6)
I2Cx (x = 1, 2),
LPTIMx (x = 1, 2)(11), LPTIMx (x = 1, 2),
GPIO, GPDMA1(12), GPDMA1,
2.4 GHz RADIO 2.4 GHz RADIO
All other peripherals are frozen.
Range 2 All from Stop 0 Range 1 except 2.4 GHz RADIO
BOR, PVD, Reset pin, all I/Os,
RTC, TAMP, IWDG, SLEEP_TIMER, BOR, PVD, RTC, TAMP, IWDG, SLEEP_TIMER,
ADC4 and temperature sensor), ADC4 and temperature sensor,
USARTx (x = 1, 2), USARTx (x = 1, 2),
LSE LPUART1, LPUART1,
Stop 1(13) LPR No OFF ON(5)
LSI SPIx (x = 1, 2), SPIx (x = 1, 2),
I2Cx (x = 1, 2), I2Cx (x = 1, 2),
LPTIMx (x = 1, 2), LPTIMx (x = 1, 2)
STM32WBA5xxx
GPIO
All other peripherals are frozen.
Table 10. Operating modes overview (continued)
STM32WBA5xxx
Flash
Mode Regulator(1) CPU SRAM Clocks DMA and peripherals(2) Wake-up source
memory
BOR, RTC, TAMP, IWDG,

SLEEP_TIMER Reset pin,
Standby
LPR ON(5) All other peripherals are powered off. WKUPx (x = 1...8),
Powered off
retention
LSE I/O configuration can be retained, BOR, RTC, TAMP, IWDG, SLEEP_TIMER
OFF floating, pull-up or pull-down.
LSI
Powered
Standby OFF All from mode Standby retention, except SLEEP_TIMER
off
1. LPR means that the main regulator is OFF and the low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
4. The SRAM1 and SRAM2 clocks can be gated on or off independently.
DS14127 Rev 5
5. The SRAM can be individually powered off to save power consumption.

6. HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wake-up from Stop event detections.
7. The ADC conversion is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on conversion events.
8. U(S)ART and LPUART transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer
events.
9. SPI transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer events.
10. I2C transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer events.
11. LPTIM is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on all events.
12. GPDMA is functional and autonomous in Stop 0 mode, and can generate a wake-up interrupt on events.
13. Active peripherals ADC, U(S)ART, LPUART, SPI, I2C and LPTIM, can generate bus clock request and/or a wake-up interrupt on event.
Functional overview
33/149
By default, the microcontroller is in Run mode after a system or a power on reset. It is up to

the user to select one of the low-power modes described below:
• Sleep
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt or event occurs.
• Stop 0 and Stop 1
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the HSI16,
and the HSE32 crystal oscillators are disabled. The LSE or LSI is still running.
The RTC, TAMP, IWDG and SLEEP_TIMER can remain active.
Some peripherals are autonomous and can operate in Stop mode by requesting their
kernel clock and their bus clock when needed, in order to transfer data with DMA Stop
0 modes will be entered. Refer to PWR background autonomous mode (BAM) for more
details. In Stop modes the bus clocks when requested use HSI16.
Stop 0 offer the largest number of active peripherals, with or without DMA, and wake-up
sources, a smaller wake-up time but a higher consumption than Stop 1.
In Stop 0 mode, the main regulator remains ON, allowing a very fast wake-up time, but
with much higher power consumption.
Stop 1 is the lowest power mode with full retention, but the functional peripherals and
sources of wake-up are reduced.
The BOR can be configured in ultra-low power mode to further reduce power
consumption during Stop 1 mode.
The system clock when exiting from Stop 0 or Stop 1 modes is HSI16.
• Standby retention and Standby
The Standby mode is used to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16
and the HSE32 crystal oscillators are also switched off. The LSE or LSI is still running.
The RTC and IWDG can remain active.
The BOR always remains active in Standby mode.
The BOR can be configured in ultra-low power mode to further reduce power
consumption during Standby mode.
The state of each I/O during Standby mode can be retained with internal pull-up,
internal pull-down or floating.
After entering Standby mode, SRAMs and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, the full SRAM1 and/or SRAM2
can be retained in Standby mode, supplied by the low-power regulator (Standby with
RAM retention mode). Also optionally the 2.4 GHz RADIO can be retained in Standby
mode, supplied by the low-power regulator (Standby with 2.4 GHz RADIO retention
mode).
The device exits Standby modes when an external reset (NRST pin), an IWDG event or
reset, WKUP pin event (configurable rising or falling edge), an RTC event occurs
(alarm, periodic wake-up, timestamp), or a tamper detection. The tamper detection can
be raised either due to external pins or due to an internal failure detection.
When in Standby with 2.4 GHz RADIO retention mode also the SLEEP_TIMER can exit
the device from Standby mode.
The system clock after wake-up is HSI16.
34/149 DS14127 Rev 5

PWR background autonomous mode (BAM)

The devices support BAM (background autonomous mode), that allows peripherals to be
functional and autonomous in Stop mode (Stop 0 and Stop 1 modes), so without any
software running.
In Stop 0 modes, the autonomous peripherals are the following: ADC4, LPTIMx (x = 1, 2),
U(S)ARTx (x = 1, 2), LPUART1, SPIx (x = 1, 2), I2Cx (x = 1, 2), 2.4 GHz RADIO and
GPDMA1. In this mode the GPDMA1 can be used to transfer data or control peripherals and
access SRAM1 and SRAM2. The ADC4 can also be used to measure temperature. The
2.4 GHz RADIO is autonomous only in Stop 0 range 1.
In Stop 1 mode, the autonomous peripherals are the following: ADC4, LPTIMx (x = 1, 2),
U(S)ARTx (x = 1, 2), LPUART1, SPIx (x = 1, 2), I2Cx (x = 1, 2). These peripherals can
request a transition to Stop 0 mode allowing then data transfers with GPDMA1.
Those peripherals support the features detailed below:
• Functionality in Stop mode thanks to its own independent clock (named kernel clock)
request capability: the peripheral kernel clock is automatically switched on when
requested by a peripheral, and automatically switched off when no peripheral
requests it.
• DMA transfers supported in Stop 0 mode thanks to system clock request capability: the
system clock (HSI16) automatically switched on when requested by a peripheral, and
automatically switched off when no peripheral requests it. When the system clock is
requested by an autonomous peripheral, Stop 0 mode is automatically entered and the
system clock is woken up and distributed to all peripherals enabled in the RCC. This
allows the DMA to access the enabled SRAM, and any enabled peripheral register (for
instance GPIO registers). When no peripheral requests its bus clock Stop 1 mode is
automatically re-entered when Stop 1 mode selected as low-power mode.
• Automatic start of the peripheral thanks to hardware synchronous or asynchronous
triggers (such as I/Os edge detection and low-power timer event).
• Wake-up from Stop mode with peripheral interrupt.
The GPDMA is fully functional and the linked-list is updated in Stop 0 mode, allowing the
different DMA transfers to be linked without any CPU wake-up. This can be used to chain
different peripherals transfers, or to write peripherals registers in order to change their
configuration while remaining in Stop 0 mode.
The DMA transfers from memory to memory can be started by hardware synchronous or
asynchronous triggers, and the DMA transfers between peripherals and memories can also
be gated by those triggers.
DS14127 Rev 5 35/149

65
Here below some use-cases that can be done while remaining in Stop mode:
• A/D conversion triggered by a low-power timer (or any other trigger)
– wake-up from Stop mode on analog watchdog if the A/D conversion result is out of
programmed thresholds
– wake-up from Stop mode on DMA buffer event
• I2C slave reception or transmission, SPI reception, UART/LPUART reception
– wake-up at the end of peripheral transfer or on DMA buffer event
2
• I C master transfer, SPI transmission, UART/LPUART transmission, triggered by a
low-power timer (or any other trigger):
– example: sensor periodic read
– wake-up at the end of peripheral transfer or on DMA buffer event
• Bridges between peripherals
– example: ADC converted data transferred by communication peripherals
• Data transfer from/to GPIO to/from SRAM for:
– controlling external components
– implementing data transmission and reception protocols
Table 11. Functionalities depending on the working mode(1)

Standby
Run Sleep Stop 0 Stop 1 Standby
retention
Peripheral
capability
capability
capability
capability
Wake-up
Wake-up
Wake-up
Wake-up
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
- - -
CPU Y R R - R - - - - -
(2) O(2)
Flash memory O R - R - R - R -
SRAM1 O O O(3) - O(3) - O(3) - O(3) -
(3) O(4) O(3) O(3) O(3)
SRAM2 O O O - -
Backup registers O O O - R - R - R -
ICACHE O R R - R - - - - -
2.4 GHz RADIO O R O R O R O R - - - - -
2.4 GHz RADIO SRAM O R O R O R - R - R - - -
SLEEP_TIMER O O O O O O O O - -
BOR Y Y Y Y Y Y Y Y Y Y
PVD O O O O O O - - - -
(5)
HSI16 O O O - O(5) - - - - -
HSE32 O O O(6) - - - - - - - -
LSI O O O - O - O - O -
LSE O O O - O - O - O -
HSECSS O O O - O - - - - - -
36/149 DS14127 Rev 5

Table 11. Functionalities depending on the working mode(1) (continued)

Standby
Run Sleep Stop 0 Stop 1 Standby
retention
Peripheral
capability
capability
capability
capability
Wake-up
Wake-up
Wake-up
Wake-up
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
- - -
LSECSS O O O O O O O O O O
IWDG O O O O O O O O O O
RTC O O O O O O O O O O
Up Up to Up to
TAMP tamper pins Up to 5 Up to 5 Up to 5 O O O O
to 5 5 5
GPIO pins O O O O O O O/R(7) O(8) O/R(7) O(8)
U(S)ARTx (x = 1, 2) O O O O(9) O O(9) - - - -
LPUART1 O O O O(9) O O(9) - - - -
I2Cx (x = 1, 2) O O O O(10) O O(10) - - - -
SPIx (x = 1, 2) O O O O(11) O O(11) - - - -
ADC4 O O O O(12) O O(12) - - - -
COMPx (x = 1, 2) O O O O O O - - - -
LPTIMx (x = 1, 2) O O O O(13) O O(13) - - - -
GPDMA1 O O O O(14) R - - - - -
PTACONV O O O R - R - - - - -
TIMx (x = 1, 2, 3, 16, 17) O O R - R - - - - -
SAI1 O O R - R - - - - -
TSC O O R - R - - - - -
RNG O O R - R - - - - -
AES and SAES O O R - R - - - - -
PKA O O R - R - - - - -
HASH O O R - R - - - - -
CRC O O R - R - - - - -
WWDG O O R - R - - - - -
SysTick timer O O R - R - - - - -
HSEM O R R - R - - - - -
DBGMCU O O O(15) - O(15) - O(16) - O(16) -
1. Legend: Y = yes (enabled). O = optional (disabled by default, can be enabled by software).R = retained, - = not available.
Gray cells highlight the wake-up capability in each mode.
2. The flash memory can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAMs can be powered on or off independently.
4. Parity error interrupt or NMI wake-up from Stop mode.
DS14127 Rev 5 37/149

65
5. Some peripherals with autonomous mode and wake-up from Stop capability can request HSI16 to be enabled. In this case,
the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.
6. The 2.4 GHz RADIO peripheral in autonomous mode request HSE32 to be enabled. In this case, the oscillator is kept
active by the peripheral, and is automatically put off when it no longer needs it.
7. I/O levels can be retained with pull-up, pull-down, or floating.
8. There are 16 wake-up pins available.
9. U(S)ART and LPUART reception and transmission are functional and autonomous in Stop mode in asynchronous and in
SPI master modes, and generate a wake-up interrupt on transfer events.
10. I2C reception and transmission is functional and autonomous in Stop mode and generates a wake-up interrupt on transfer
events.
11. SPI reception and transmission is functional and autonomous in Stop mode and generates a wake-up interrupt on transfer
events.
12. A/D conversion is functional and autonomous in Stop mode, and generates a wake-up interrupt on conversion events.
13. LPTIM is functional and autonomous in Stop mode, and generates a wake-up interrupt on events.
14. GPDMA transfers are functional and autonomous in Stop 0 mode, and generates a wake-up interrupt on transfer events.
15. DBGMCU remains accessible trough AP0.
16. DBGMCU remains accessible through AP0 when CDBGPWRUPREQ is set.
3.12.3 Reset mode

To improve the consumption under reset, the I/Os state under and after reset is “analog
state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.12.4 PWR TrustZone security

When TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security secures the following configuration:
• Low-power mode
• WKUP (wake-up) pins
• Voltage detection
• Backup domain control
Some of the PWR configuration bits security is defined by the security of other peripherals:
• The VOS (voltage scaling) configuration is secure when the system clock selection is
secure in RCC.
• The I/O Standby mode retention configuration is secure when the corresponding GPIO
is secure.
3.13 Reset and clock controller (RCC)

The RCC (reset and clock controller) manages device and peripheral reset and distributes
the clocks coming from the different oscillators to the core and to the peripherals. It also
manages the clock gating for low-power modes and ensures the clock robustness. It
features:
• Device reset source monitoring.
• Individual peripheral reset control.
38/149 DS14127 Rev 5

• Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
• Clock selection system: clock sources can be changed safely on-the-fly in Run mode
through a configuration register.
• Clock management: to reduce the power consumption, the clock controller can stop the
clock to the core, individual peripherals, or memory.
• System clock source: different clock sources can be used to drive the system clock
SYSCLK:
– HSE32 (32 MHz high-speed external crystal oscillator), trimmable by software.
The HSE32 can also be used with an external clock.
– HSI16 (16 MHz high-speed internal RC oscillator), trimmable by software.
– System PLL that can be fed by HSE32 or HSI16 with a maximum output frequency
at 100 MHz.
• Auxiliary clock source: three ultra-low power clock sources that can be used to drive,
for instance, the real-time clock:
– LSE (32.000 kHz or 32.768 kHz low-speed external crystal oscillator), supporting
programmable drive capability modes. The LSE can also be configured in bypass
mode for an external clock.
– LSI1 (32 kHz low-speed internal RC oscillators), also used to drive the
independent watchdog. The LSI1 clock absolute accuracy is ±5%, it can be
divided by 128 to output a 250 Hz as source clock.
– LSI2 (32 kHz high stability, ±500 ppm), can be used to drive the 2.4 GHz RADIO
sleep timer.
• Peripheral clock sources: several peripherals have their own independent kernel clock
whatever the system clock. The PLL has three independent outputs allowing the
highest flexibility and can generate clocks for the ADC and the RNG.
• Startup clock: after reset, the microcontroller restarts by default with the HSI16. The
prescaler ratio and clock source can be changed by the application program as soon
as the code execution starts.
• CSS (Clock security systems): these features can be enabled by software.
– If a HSE32 clock failure occurs, the system clock automatically switches to HSI16
and a software interrupt is generated if enabled.
– LSE failure can also be detected and generates an interrupt, in this case the clock
switches to LSI.
• Clock-out capability:
– MCO (microcontroller clock output): outputs one of the internal clocks for external
use by the application. (only available in Run, Sleep and Stop mode)
– LSCO (low-speed clock output): outputs LSI or LSE in all operating modes.
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 100 MHz, except for AHB5 domain, limited to
32 MHz.
DS14127 Rev 5 39/149

65
Figure 6. Clock tree
LSI2 RC 500 ppm(1)

to IWDG
LSI1 RC ~32 kHz
/1, 128 LSI
LSCO
LSE to RTC and TAMP
LSE OSC
OSC32_OUT 32.768 kHz or
32.000 kHz LSE
OSC32_IN
LSE CSS LSI to 2.4 GHz RADIO sleep timer
LSI /1000 HPRE hclk1 to CPU, AHB1, AHB2, Flash, SRAM1, SRAM2
/1,2,4,8,16
LSE to CPU FCLK
/32
HSE32 /8
LSI to CPU
sysclkpre LSE system timer
APB1 pclk1 to APB1
MCO hclk5 PPRE1
/1 - 16
/1,2,4,8,16 to TIM2, 3
pll1rclk /1 or /2
APB2 pclk2
HSI16 PLLRPRE to APB2
pll1rclk PPRE2
/1,2,4,8,16 to TIM1, 16, 17
pll1qclk HSE32 /1 or /2
HSEPRE SYSCLK
/1, 2
pll1pclk to AHB4
HSI16 APB7
OSC_OUT HSE OSC pclk7
PPRE7
32 MHz HSE32 to APB7
HPRE5 /1,2,4,8,16
HSE_RF /1,2,3,4,6 hclk5
OSC_IN HDIV5 to AHB5
HSE CSS
/1,2
SW, SWS
HSI16 RC system clock
16 MHz source control
to 2.4 GHz RADIO RF
HSI16 pclk1
to SAES kernel pclk2
/M hclk1
HSE32PRE SYSCLK
to UART2 kernel SYSCLK
to 2.4 GHz RADIO kernel to UART1
EN HSI16
HSI16 kernel
PLL1 HSI16
LSE
ref_ck pll1pclk pll1qclk LSE
xN /P /2
to RNG kernel
SYSCLK LSI pclk1
pll1qclk pclk7
/Q
HSI16 LSE HSI16
to LPTIM2 kernel SYSCLK to
/R pll1rclk LPUART1
pll1qclk to SAI1 kernel LSI
HSI16 kernel
hclk1 LSE
pll1pclk LSE
AUDIOCLK SYSCLK pclk7

to ADC4 kernel pclk2
HSE32 HSI16
to LPTIM1 kernel SYSCLK to SPI1 kernel
HSI16 LSI
HSI16
pll1pclk LSE
pclk7 pclk1 pclk7
SYSCLK to I2C3 kernel to I2C1 kernel to SPI3 kernel

SYSCLK SYSCLK
HSI16 HSI16 HSI16

MS55617V2
3.13.1 RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
The RCC TrustZone security secures some RCC system configuration and peripheral
configurations from being read or modified by non-secure accesses: when a peripheral is
secure, the related peripheral clock, reset, clock source selection, and clock enable during
low-power modes control bits are secure.
40/149 DS14127 Rev 5

A peripheral is in secure state:

• For securable peripherals, when the corresponding SEC security bit is set in the TZSC
(TrustZone security controller).
• For TrustZone-aware peripherals, when a security feature of the peripheral is enabled
through dedicated peripheral bits.
3.14 General-purpose input/output (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked, if needed, following a specific
sequence in order to avoid spurious writing to the I/Os registers.
The GPIO allows dynamic I/O control in Stop 0 mode thanks to GPDMA1. All I/Os can be
configured and controlled as input or output (open-drain or push-pull depending on GPIO
configuration).
When enabled in the PWR, latest I/Os output level can be retained by pulling the I/Os high
or low before entering Standby mode. I/O levels are retained after exit from Standby mode,
until they are reconfigured by software.
3.14.1 GPIO TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a non-secure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.
3.15 System configuration controller (SYSCFG)

The main purpose of the SYSCFG (system configuration controller) are the following:
• Managing robustness features
• Configuring FPU interrupts
• Enabling/disabling the I2C fast-mode plus high-drive mode of some I/Os and booster
for I/Os analog switches
• Managing the I/O compensation
• Provides memory erase status
• Communication channel with the RSS
3.15.1 SYSCFG TrustZone security

When TrustZone security is activated by the TZEN option bit, the SYSCFG is switched in
DS14127 Rev 5 41/149

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The SYSCFG TrustZone security secures the following configuration:

• FPU interrupt configuration
• Robustness features
• I/O compensation and memory erase status
Some of the SYSCFG configuration bits security is defined by the security of other
peripherals:
• The FMP high-drive mode of some I/Os configuration is secure when the
corresponding GPIO is secure.
• The booster for I/Os analog switches configuration is secure when the ADC4 is secure.
3.16 Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
3.17 General purpose direct memory access controller (GPDMA)

The general purpose direct memory access (GPDMA) controller is a bus master and system
peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
• Dual bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Run, Sleep and Stop 0 modes
• Transfers arbitration based on a four-grade programmed priority at a channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• Eight concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
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– Intra-channel DMA transfers chaining via programmable linked-list into memory,

supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– Linear source and destination addressing: either fixed or contiguously
incremented addressing, programmed at a block level, between successive single
transfers
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• TrustZone support:
– Support for secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source/destination and link sub-levels
– Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a non-secure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at a channel
level
– Privileged-aware AHB slave port.
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65
Table 12. GPDMA1 channels implementation and usage

Hardware parameters
Channel x Features
dma_fifo_ dma_
size[x] addressing[x]
Channel x is implemented with:

– a FIFO of 8 bytes, 2 words
x = 0 to 5 2 0 – fixed/contiguously incremented addressing
These channels may be also used for GPDMA transfers,
between an APB or AHB peripheral and SRAM.
Channel x is implemented with:
– a FIFO of 32 bytes, 8 words
– fixed/contiguously incremented addressing
x = 6 to 7 4 0
These channels may be also used for GPDMA transfers,
between a demanding AHB or APB peripheral and
SRAM.
Table 13. GPDMA1 autonomous mode and wake-up in low-power modes

Feature Low-power modes
Autonomous mode and wake-up Sleep, Stop 0 modes
3.18 Interrupts and events
3.18.1 Nested vectored interrupt controller (NVIC)

The devices embed a NVIC (nested vectored interrupt controller) that is able to manage 16
priority levels and to handle up to 70 maskable interrupt vectors plus the 16 interrupt vectors
of the Cortex-M33.
The NVIC benefits are the following:
• closely coupled NVIC giving low-latency interrupt processing
• interrupt entry vector table address passed directly to the core
• early processing of interrupts
• processing of late arriving higher priority interrupts
• support for tail chaining
• processor state automatically saved
• interrupt entry restored on interrupt exit with no instruction overhead
• TrustZone support: NVIC registers banked across secure and non-secure states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.18.2 Extended interrupt/event controller (EXTI)

The EXTI (extended interrupts and event controller) manages the individual CPU and
system wake-up through configurable event inputs. It provides wake-up requests to the
44/149 DS14127 Rev 5

power control, and generates an interrupt request to the CPU NVIC and events to the CPU
event input.
The EXTI wake-up requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run and Sleep
modes. The EXTI also includes the peripheral interconnect EXTI multiplexer I/O port
selection.
The EXTI main features are the following:
• All event inputs allowed to wake up the system
• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Selectable active trigger edge
– Interrupt pending status register bit independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wake-up, interrupt and event generation
– Software trigger possibility
• TrustZone secure events
– The access to control and configuration bits of secure input events can be made
secure
• EXTI I/O port selection for peripheral interconnect use.
3.19 Cyclic redundancy check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, that
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.
3.20 Analog-to-digital converter (ADC4)

The devices embed one successive approximation analog-to-digital converter.
Table 14. ADC features

ADC modes/features(1) ADC4
Resolution 12 bits
Maximum sampling speed for 14-bit resolution 2.5 Msps
Hardware offset calibration X
Hardware linearity calibration -
Single-ended inputs X
Differential inputs -
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Table 14. ADC features (continued)

ADC modes/features(1) ADC4
Injected channel conversion -

Oversampling Up to x256
Data register 16 bits
DMA support X
Autonomous mode X
Offset compensation -
Gain compensation -
Number of analog watchdogs 3
Wake-up from Stop mode X
1. X = supported.
3.20.1 Analog-to-digital converter (ADC4)

The 12-bit ADC4 is a successive approximation analog-to-digital converter. It has up to
19 multiplexed channels allowing it to measure signals from 9 external and 3 internal
sources (the other channels are reserved). ADC conversion of the various channels can be
performed in Single, Continuous, Scan or Discontinuous mode. The result of the ADC is
stored in a left-aligned or right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency. The ADC4 is autonomous in low-power modes down to Stop modes.
A built-in hardware oversampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
The ADC4 main features are:
• High performance
– 12-, 10-, 8- or 6-bit configurable resolution
– ADC conversion time: 0.4 µs for 12-bit resolution (2.5 MHz), faster conversion
times obtained by lowering resolution
– Self-calibration
– Programmable sampling time
– Data alignment with built-in data coherency
– DMA support
• Low-power
– PCLK frequency reduced for low-power operation while still keeping optimum
ADC performance
– Wait mode: ADC overrun prevented in applications with low frequency PCLK
– Auto-off mode: ADC automatically powered off except during the active
conversion phase, dramatically reducing the ADC power consumption
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– Autonomous mode: In low-power modes down to Stop 1 mode, the ADC4 is

automatically switched on when a trigger occurs to start conversion, and it is
automatically switched off after conversion. Data are transfered to SRAM with
DMA.
– ADC4 interrupts wake up the device from Stop modes.
• Analog input channels
– 9 external analog inputs
– One channel for the internal temperature sensor (VSENSE)
– One channel for the internal reference voltage (VREFINT)
– One channel for the internal digital core voltage (VCORE)
• Start-of-conversion can be initiated:
– By software
– By hardware triggers with configurable polarity (timer events or GPIO input
events)
• Conversion modes
– Conversion of a single channel or scan of a sequence of channels
– Selected inputs converted once per trigger in Single mode
– Selected inputs converted continuously in Continuous mode
– Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events, with wake-up from Stop
capability
• Three analog watchdogs
• ADC supply requirements: 1.62 V to 3.6 V
• ADC input range: VSSA < VIN < VDDA
Note: The ADC4 analog block clock frequency after the ADC4 prescaler must be between
140 kHz and 55 MHz.
Note: VSSA is connected to package pin VSS.
3.20.2 Temperature sensor (VSENSE)

The temperature sensor generates a voltage VSENSE that varies linearly with temperature.
The temperature sensor is internally connected to ADC4 input channel that is used to
convert the sensor output voltage into a digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by STMicroelectronics in the system memory area, accessible in read-only mode.
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Table 15. Temperature sensor calibration values

Calibration
Description Memory address
value name
Temperature sensor ADC4 12-bit raw data acquired at (30 ± 5) °C,

TS_CAL1 0x0BF9 0710 - 0x0BF9 0711
VDDA = 3.0 V (± 10 mV)
Temperature sensor ADC4 12-bit raw data acquired at (130 ± 5) °C,
TS_CAL2 0x0BF9 0742 - 0x0BF9 0743
VDDA = 3.0 V (± 10 mV)
3.20.3 Internal voltage reference (VREFINT)

The internal voltage reference voltage VREFINT provides a stable (bandgap) voltage for the
ADC. The VREFINT is internally connected to ADC4 input channel that is used to convert the
voltage into a digital value.
The precise voltage of VREFINT is individually measured for each part by
STMicroelectronics during production test and stored in the system memory area. It is
accessible in read-only mode.
Table 16. Internal voltage reference calibration values

Calibration
Description Memory address
value name
Internal voltage reference ADC4 12-bit raw data acquired

VREFINT_CAL 0x0BF9 07A5 - 0x0BF9 07A6
at (30 ± 5) °C, VDDA = 3.0 V (± 10 mV)
3.21 Comparators (COMP)

The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low-speed for low-power) and with selectable
output polarity.
The reference voltage can be an internal reference voltage or sub-multiple (1/4, 1/2, 3/4).
The voltage on an external I/O can be compared to the reference voltage.
All comparators can wake up from Stop 0 and Stop 1 modes, generate interrupts and breaks
for the timers and can also be combined into a window comparator.
3.22 Touch sensing controller (TSC)

The TSC (touch sensing controller) provides a simple solution to add capacitive sensing
functionality to any application. A capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (glass, plastic
or other). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The TSC is fully supported by the STMTouch touch sensing firmware library that is free to
use and allows touch sensing functionality to be implemented reliably in the end application.
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The TSC main features are the following:

• Proven and robust surface charge transfer acquisition principle
• Support of up to 20 capacitive sensing channels
• Up to six capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the packages and subject to
I/O availability.
3.23 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The true random generator:
• Delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
• Can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG)
• Produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
• Embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• Can be disabled to reduce power consumption, or enabled with an automatic
low-power mode (default configuration)
• Has an AHB slave peripheral, accessible through 32-bit word single accesses only
(else an AHB bus error is generated, and the write accesses are ignored)
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3.24 Secure advanced encryption standard hardware accelerator

(SAES) and encryption standard hardware accelerator (AES)
The devices embed two AES accelerators: SAES and AES. The SAES with hardware
unique key embeds protection against differential power analysis (DPA) and related side
channel attacks. The SAES can share its current key register information with the faster
AES using a dedicated hardware bus.
The SAES and the AES can be used to both encrypt and decrypt data using the AES
algorithm. It is a fully compliant implementation of the advanced encryption standard (AES)
as defined by Federal Information Processing Standards Publication (FIPS PUB 197, Nov
2001).
Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB, CBC, CTR,
CCM, GCM and GMAC chaining is supported by both SAES and AES.
SAES and AES support DMA single transfers for incoming and outgoing data (two DMA
channels required).
The SAES supports the selection of all the following key sources, while the AES support
only the first:
• 256-bit software key, written by the application in the key registers (write only)
• 256-bit DHUK (derived hardware unique key), computed inside the SAES engine from
a non-volatile OTP based RHUK (root hardware unique key)
• 256-bit BHK (boot hardware key), stored in tamper-resistant secure backup registers,
written by a secure code during boot. Once written, this key cannot be read or write by
any application until the next product reset.
• XOR of DHUK (provisioned chip secret) and BHK (software secret)
DHUK, BHK and their XOR are not visible by any software (even secure).
Note: 128-bit key size can also be selected.
BHK key is cleared in case of tamper or RDP regression.
When the SAES is secure (respectively non-secure), DHUK secure (respectively non-
secure) is used.
The SAES peripheral is connected by hardware to the true random number generator RNG
(for side-channel resistance).
The SAES and AES peripherals support:
• Compliant implementation of standard NIST Special Publication 197, Advanced
Encryption Standard (AES) and Special Publication 800-38A, Recommendation for
Block Cipher Modes of Operation
• 128-bit data block processing
• Support for cipher keys length of 128-bit and 256-bit
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode
– Counter (CTR) mode
– Galois counter mode (GCM)
– Galois message authentication code (GMAC) mode
– Counter with CBC-MAC (CCM) mode
50/149 DS14127 Rev 5

• 528 or 743 clock cycle latency in ECB encryption mode for SAES processing one
128-bit block of data with, respectively, 128- or 256-bit key
• 51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit
block of data with, respectively, 128- or 256-bit key
• Integrated round key scheduler to compute the last round key for AES ECB/CBC
decryption
• 256-bit register for storing the cryptographic key (four 32-bit registers), with key
atomicity enforcement
• 128-bit registers for storing initialization vectors (four 32-bit registers)
• One 32-bit input buffer and one 32-bit output buffer
• Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)
• Data swapping logic to support 1-, 8-, 16- or 32-bit data
• Possibility for software to suspend a message if the SAES/AES needs to process
another message with a higher priority (suspend/resume operation)
• SAES additional features:
– Security context enforcement for keys
– Hardware secret key encryption/ decryption (wrapped key mode) and sharing with
faster AES peripheral (Shared key mode)
– Protection against DPA (differential power analysis) and related side-channel
attacks
– Optional hardware loading of two hardware secret keys (BHK, DHUK) that can be
XORed together
On top of standard AES encryption and decryption with a key loaded by software, SAES
peripheral makes possible the following advanced use cases:
• Allow or deny the sharing of a key between a secure and a non-secure application,
enforced by hardware
• Encrypt once a key using side-channel resistant AES, then share it to a faster AES
engine by decrypting it (Shared key mode)
• On-chip encrypted storage using secret DHUK
• Transport key generation by encrypting the device public unique ID with the application
secret BHK
• Binding of device secure storage keys, using the secret derived hardware unique key
(DHUK) XORed with the secret boot hardware key (BHK). If BHK is lost, the whole
device secure storage is lost.
Note: Encrypted storage or derived keys that are using DHUK or BHK, cannot be used anymore
when a security breach is detected.
Table 17. AES/SAES features

AES/SAES modes/features(1) AES SAES
ECB, CBC chaining X X

CTR, CCM, GCM chaining X X
AES 128-bit ECB encryption in cycles 51 528
DHUK and BHK key selection - X
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Table 17. AES/SAES features (continued)

AES/SAES modes/features(1) AES SAES
Side-channel attacks resistance - X

Shared key between SAES and AES X
1. X = supported.
3.25 HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA2-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and
the keyed-hash message authentication code (HMAC) algorithm. HMAC is suitable for
applications requiring message authentication.
The HASH computes Federal information processing standards (FIPS) approved digests of
length of 160, 224, 256 bits, for messages of up to (264 – 1) bits. It also computes 128 bits
digests for the MD5 algorithm.
The HASH main features are:
• Suitable for data authentication applications, compliant with:
– Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
– Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5
Message-Digest Algorithm
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA2-224, SHA-256, and MD5
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
– 66 clock cycles for processing one 512-bit block of data using MD5 algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
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• Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of 4 supported.
• Interruptible message digest computation, on a per-32-bit word basis
– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including using DMA
3.26 Public key accelerator (PKA)

The PKA is intended for the computation of cryptographic public key primitives, specifically
those related to RSA, DU (Diffie-Hellmann) or (ECC) elliptic curve cryptography over GF(p)
(Galois fields). To achieve high performance at a reasonable cost, these operations are
executed in the Montgomery domain.
All needed computations are performed within the accelerator, so no further
hardware/software elaboration is needed to process the inputs or the outputs.
The PKA main features are:
• Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery
method for fast modular multiplications. More specifically:
– RSA modular exponentiation, RSA CRT (Chinese remainder theorem)
exponentiation
– ECC scalar multiplication, point on curve check, complete addition, double base
ladder, projective to affine
– ECDSA signature generation and verification
• Capability to handle operands up to 4160 bits for RSA/DH and 640 bits for ECC
• Arithmetic and modular operations such as addition, subtraction, multiplication,
modular reduction, modular inversion, comparison, and Montgomery multiplication
• Built-in Montgomery domain inward and outward transformations
• Protection against DPA (differential power analysis) and related side-channel attacks.
3.27 Timers and watchdogs

The devices include one advanced control timer, four general-purpose timers, two
low-power timers, two watchdog timers and two SysTick timers.
Table 18 compares the features of the advanced control, general-purpose and basic timers.
Table 18. Timers comparison

Counter Counter Prescaler DMA request Capture/compare Complementary
Type Timer
resolution type factor generation channels outputs
Advanced Up, down,

TIM1 16 bits 4 3
control up/down
TIM2 32 bits Any integer
Up, down,
between 1 Yes 4 No
General- TIM3 16 bits up/down
and 65536
purpose
TIM16,
16 bits Up 1 1
TIM17
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3.27.1 Advanced-control timers (TIM1)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted
dead-times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes) with full modulation capability
(0 - 100%)
• One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.
3.27.2 General-purpose timers (TIM2, TIM3, TIM16, TIM17)

There are up to four synchronizable general-purpose timers embedded in the device (see
Table 18 for differences). Each general-purpose timer can be used to generate PWM
outputs, or act as a simple time base.
• TIM2 and TIM3
– They are full-featured general-purpose timers with TIM2 32-bit auto-reload
up/downcounter, TIM3 16-bit auto-reload up/downcounter, both with 16-bit
prescaler.
– These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other
general-purpose timers via the Timer Link feature for synchronization or event
chaining.
– The counters can be frozen in Debug mode.
– All have independent DMA request generation and support quadrature encoders.
• TIM16 and 17
– They are general-purpose timers with mid-range features.
– They have 16-bit auto-reload upcounters and 16-bit prescalers. and have one
channel and one complementary channel.
– All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
– The timers can work together via the Timer Link feature for synchronization or
event chaining. The timers have independent DMA request generation.
– The counters can be frozen in Debug mode.
– All have independent DMA request generation.
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3.27.3 Low-power timers (LPTIM1, LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by HSI16, LSE, LSI or an external clock. They are
able to wake up the system from Stop mode.
LPTIM1, LPTIM2 are active in Stop modes.
The low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 3-bit prescaler with following possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
• Selectable clock
– Internal clock sources: LSE, LSI, HSI16 or APB clock
– External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
• 16-bit ARR autoreload register
• 16-bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
• Encoder mode
• Repetition counter
• Up to two independent channels for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on ten events
• DMA request generation on the following events:
– Update event
– Input capture
3.27.4 Infrared interface (IRTIM)

An infrared interface (IRTIM) for remote control is available on the device. It can be used
with an infrared LED to perform remote control functions. It uses internal connections with
TIM16 and TIM17.
3.27.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and a 10-bit prescaler. It is
clocked from the independent LSI and, as it operates independently from the main clock, it
can operate in Stop and Standby modes. It can be used either as a watchdog to reset the
device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software enabled through the option bytes. The counter can
be frozen in low-power and Debug mode.
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3.27.6 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
3.27.7 SysTick timer

The Cortex-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, secure instance
• SysTick, non-secure instance
When TrustZone is disabled, only one SysTick timer is available.
This timer (secure or non-secure) is dedicated to real-time operating systems, but can also
be used as a standard down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
3.28 Real-time clock (RTC)

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar with programmable alarm interrupts.
As long as the VDD supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, low-power mode or under reset).
The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in binary-coded decimal (BCD) format
• Binary mode with 32-bit free-running counter
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a reference clock
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event
• 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable
resolution and period
– RTC fully securable
56/149 DS14127 Rev 5

– Alarm A, alarm B, wake-up timer and timestamp individual secure or non-secure

configuration
– Alarm A, alarm B, wake-up timer and timestamp individual privileged protection
The RTC is supplied from the VDD supply.
The RTC clock sources can be one of the following:
• LSE, used as 32.768 kHz external crystal oscillator
• LSE, with external resonator or oscillator
• LSI, internal low-power RC oscillator (with typical frequency of 32 kHz)
• HSE32, high-speed external clock divided by a prescaler in the RCC.
The RTC is functional in all low-power modes when it is clocked by the LSE or LSI.
All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake up
the device from the low-power modes.
3.29 Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32
32-bit backup registers are retained in all low-power modes. The backup registers, as well
as other secrets in the device, are protected by this anti-tamper detection circuit with up to
five tamper pins and nine internal tampers. The external tamper pins can be configured for
level detection with or without filtering, or active tamper that increases the security level by
auto checking that the tamper pins are not externally opened or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, SRAM2, ICACHE and
cryptographic peripherals.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the Backup domain that
remains powered-on by VDD power.
• Up to six tamper pins for external tamper detection events:
– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
– Flexible active tamper I/O management: from two (each input associated to its
own exclusive output) to four meshes (single output shared for up to four tamper
inputs)
– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
– Configurable digital filter
• Nine internal tamper events to protect against transient or environmental perturbation
attacks:
– LSE monitoring
– RTC calendar overflow
– JTAG/SWD access if RDP different from 0
– Monotonic counter overflow
– Cryptographic peripherals fault (RNG, SAES, AES, PKA)
– Independent watchdog reset when tamper flag is already set
DS14127 Rev 5 57/149

65
– Three ADC4 watchdogs

• Each tamper can be configured in two modes:
– Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Software mode: erase of secrets following a tamper detection launched by
software
• Any tamper detection can generate an RTC time stamp event.
– Tamper secure or non-secure configuration.
– Backup registers configuration in three configurable-size areas:
- a read/write secure area
- a write secure/read non-secure area
- a read/write non-secure area
– Secret boot hardware key (BHK) only usable by secure SAES peripheral, stored in
backup registers, protected against read and write access
• Tamper configuration and backup registers privilege protection
• Monotonic counter
3.30 Inter-integrated circuit interface (I2C)

The device embeds two I2C, refer to Table 19 for the features implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multi-master capability
– Standard-mode (Sm), with a bit rate up to 100 Kbit/s
– Fast-mode (Fm), with a bit rate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 3.0 compatibility:
– Hardware packet error checking (PEC) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus) specification rev 1.3 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Autonomous functionality in Stop modes with wake-up from Stop capability
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
58/149 DS14127 Rev 5

Table 19. I2C implementation

I2C features(1) I2C1 I2C3
Standard-mode (up to 100 Kbit/s) X X

Fast-mode (up to 400 Kbit/s) X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X
Programmable analog and digital noise filters X X
SMBus/PMBus hardware support X X
Independent clock X X
Autonomous in Stop modes with wake-up capability X X
1. X: supported
3.31 Universal synchronous/asynchronous receiver transmitter

(USART/UART) and low-power universal asynchronous
receiver transmitter (LPUART)
The devices have two embedded universal synchronous receiver transmitters (USART1,
USART2) and one low-power universal asynchronous receiver transmitter (LPUART1).
Table 20. U(S)ART and LPUART features

USART modes/features(1) USART1 USART2 LPUART1
Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode (master/slave) X X -
Smartcard mode X X -
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X X -
LIN mode X X -
Dual-clock domain and wake-up from Stop modes X X X
Receiver timeout interrupt X X -
Modbus communication X X -
Auto-baud rate detection X X -
Driver enable X X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size 8 bytes
Autonomous mode X X X
1. X = supported.
DS14127 Rev 5 59/149

65
3.31.1 USART/UART
The U(S)ART offers a flexible means to perform full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The U(S)ART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.
High-speed data communications up to 20 Mbauds are possible by using the direct memory
access (DMA) for multibuffer configuration.
The U(S)ART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous Master/Slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wake-up from stop capability
• LIN master synchronous break send capability and LIN slave break detection capability
60/149 DS14127 Rev 5

– 13-bit break generation and 10/11-bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode
• Smartcard mode
– Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation
• Support for Modbus communication
– Timeout feature
– CR/LF character recognition
3.31.2 LPUART
The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baudrates.
The LPUART interface can be served by the DMA controller.
The LPUART main features are:
• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for FIFOs
states.
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Programmable data word length (7 or 8 or 9 bits)
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
DS14127 Rev 5 61/149

65
– Busy and end of transmission flags

• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Four error detection flags:
– Overrun error
– Noise detection
– Frame error
– Parity error
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wake-up from Stop capability
3.32 Serial peripheral interface (SPI)

The devices embed two SPI (serial peripheral interfaces) that can be used to communicate
with external devices while using the specific synchronous protocol. The SPI protocol
supports half-duplex, full-duplex and simplex synchronous, serial communication with
external devices.
The interface can be configured as master or slave and can operate in multi-slave or multi-
master configurations. The device configured as master provides communication clock
(SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied
optionally just to setup communication with concrete slave and to assure it handles the data
flow properly. The Motorola data format is used by default, but some other specific modes
are supported as well.
The SPI main features are:
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
• Multi master or multi slave mode capability
• Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
• Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO and MOSI swap capability
• Programmable clock polarity and phase
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola and TI formats support
62/149 DS14127 Rev 5

• Hardware CRC feature can secure communication at the end of transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode
• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
• Two 16 x or 8 x 8-bit embedded Rx and TxFIFOs with DMA capability
• Programmable number of data in transaction
• Configurable FIFO thresholds (data packing)
• Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
• Autonomous functionality in Stop modes (handling of the transaction flow and required
clock distribution) with wake-up from stop capability
• Optional status pin RDY signalizing the slave device ready to handle the data flow.
Table 21. SPI features

SPI1 SPI3
SPI feature(1)
(full feature set instances) (limited feature set instance)
Data size Configurable from 4- to 32-bit 8- and 16-bit

CRC polynomial length, CRC polynomial length,
CRC computation
configurable from 5- to 33-bit configurable from 9- to 17-bit
Size of FIFOs 16 x 8-bit 8 x 8-bit
Number of transfered data Unlimited, expandable Up to 1024, no data counter
Autonomous in Stop modes
X X
with wake-up capability
1. X: supported
DS14127 Rev 5 63/149

65
3.33 Serial audio interfaces (SAI)

The devices embed one SAI, refer to Table 22 for its features. The SAI bus interface
handles communications between the microcontroller and the serial audio protocol.
Depending upon the device, the SAI peripheral can support:
• Two independent audio sub-blocks that can be transmitters or receivers with their
respective FIFOs
• 8-word integrated FIFOs for each audio sub-block
• Synchronous or Asynchronous mode between the audio sub-blocks
• Master or slave configuration independent for both audio sub-blocks
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode
• Data size configurable: 8-, 10-, 16-, 20-, 24- and 32-bit
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
• Number of bits by frame may be configurable
• Frame synchronization active level configurable (offset, bit length, level)
• First active bit position in the slot is configurable
• LSB first or MSB first for data transfer
• Mute mode
• Stereo/mono audio frame capability
• Communication clock strobing edge configurable (SCK)
• Error flags with associated interrupts if enabled respectively
– Overrun and underrun detection
– Anticipated frame synchronization signal detection in Slave mode
– Late frame synchronization signal detection in Slave mode
– Codec not ready for the AC’97 mode in reception
• Interruption sources when enabled:
– Errors
– FIFO requests
• DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block
Table 22. SAI implementation(1)

Features SAI1
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X

Mute mode X
Stereo/mono audio frame capability X
16 slots X
Data size configurable: 8-, 10-, 16-, 20-, 24- and 32-bit X
64/149 DS14127 Rev 5

Table 22. SAI implementation(1) (continued)

Features SAI1
FIFO size X (8 words)

SPDIF X
PDM X
1. X: supported.
3.34 Development support
3.34.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
DS14127 Rev 5 65/149

65
Pinouts and pin description STM32WBA5xxx
4 Pinouts and pin description
Figure 7. UFQFPN32 pinout(1) (2)
OSC_OUT
VDDRFPA
VDDHPA
OSC_IN
VDDRF
VCAP
VDD
RF
32
31
30
29
28
27
26
25
PB12 1 24 NRST
PA8 2 23 VDD
PA7 3 22 PH3-BOOT0
PA6 4 21 PB15
VDDA 5
UFQFPN32 20 PA12
PA5 6 19 PA13
PA2 7 exposed pad VSS 18 PA14
PA1 8 17 PA15
10
12
13
14
15
16
11
9
PB9
PB8
PC15-OSC32_OUT
PC14-OSC32_IN
VDD
PB4
PB3
PA0
MS55611V1
1. The above figure shows the package top view.

2. The exposed pad must be connected to ground plane.
Figure 8. UFQFPN48 pinout(1) (2)

OSC_OUT
VDDRFPA
VDDHPA
OSC_IN
VDDRF
VCAP
PB13
PB14
PA10
VDD
PA9
RF
48
47
46
45
44
43
42
41
40
39
38
37
PB12 1 36 NRST
PB11 2 35 VDD
PA8 3 34 PH3-BOOT0
PA7 4 33 PB15
PA6 5 32 PB0
VDDA 6 31 PB1
PA5 7
UFQFPN48 30 PB2
PA3 8 29 PA11
PB10 9 28 PA12
PA2 10 27 PA13
VDD 11 exposed pad VSS 26 PA14
PA1 12 25 PA15
13
14
15
16
17
18
19
20
21
22
23
24
PB9
PB8
PC15-OSC32_OUT
PC14-OSC32_IN
PC13
PB7
PB6
PB5
VDD
PB4
PB3
PA0
MS55605V1

66/149 DS14127 Rev 5

STM32WBA5xxx Pinouts and pin description
Figure 9. UFQFPN48 SMPS pinout(1) (2)
OSC_OUT
VDDRFPA
VDDANA
VDDHPA
OSC_IN
VDDRF
VDD11
PB14
PA10
VDD
PA9
RF
48
47
46
45
44
43
42
41
40
39
38
37
VSSSMPS 1 36 NRST
VDDSMPS 2 35 VDD
VLXSMPS 3 34 PH3-BOOT0
PB12 4 33 PB15
PA8 5 32 PB0
PA7 6 31 PB1
PA6 7
UFQFPN48 30 PB2
VDDA 8 29 PA11
PA5 9 28 PA12
PA2 10 27 PA13
VDD 11 exposed pad VSS 26 PA14
PA1 12 25 PA15
13
14
15
16
17
18
19
20
21
22
23
24
PB9
PB8
PC15-OSC32_OUT
PC14-OSC32_IN
PC13
PB7
PB6
PB5
VDD
PB4
PB3
PA0
MS55612V1

Figure 10. UFBGA59 SMPS ballout(1)

1 2 3 4 5 6 7 8
VSS VDD OSC_

A SMPS
PB14 PA10
RFPA OUT
VDDRF VSSRF RF
VDD VDD VDD

B SMPS
PB13 PA9
HPA
OSC_IN
ANA
VSSRF NRST
VLX PH3_
C SMPS
PB12 VDD11 VDD
BOOT0
PB15
D PA8 PB11 VSS VDD VSS PB0 PB1
E PA6 PA7 VSS VDD VSS PB2 PA11
F VDDA VSSA PA5 VDD PA14 PA12 PA13
PC15_
G PA4 PA3 PA2 OSC32_ PC13 PB6 PB3 PA15
OUT
PC14_
H PA0 PA1 PB9 OSC32_ PB8 PB7 PB5 PB4
IN
MS55613V1
DS14127 Rev 5 67/149

76
Table 23. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V-tolerant I/O
TT 3.6 V-tolerant I/O
RF RF I/O
I/O structure RST Bidirectional reset pin with weak pull-up resistor
Option for TT or FT I/Os(1)
_f I/O, Fm+ capable
_a I/O, with analog switch function supplied by VDDA
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 24 are a concatenation of various options. Examples: FT_a, FT_fa, FT_f.
68/149 DS14127 Rev 5

Table 24. Device pin definitions

Pin
Number
I/O structure
UFQFPN48 SMPS
Notes
UFBGA59 SMPS
Alternate functions Additional functions

UFQFPN32
UFQFPN48
Name (function
Type
after reset)
- - 1 A1 VSSSMPS S - - - -
- - 2 B1 VDDSMPS S - - - -
- - 3 C1 VLXSMPS S - - - -
- - - D4 VSS S - - - -
TIM2_CH1, TIM2_ETR, SPI1_RDY,

1 1 4 C2 PB12 I/O FT_ - USART1_TX, TSC_SYNC, SAI1_SD_A, -
TIM3_ETR, EVENTOUT
LPTIM1_CH1, LPTIM1_ETR,
- 2 - D2 PB11 I/O FT_ -
LPUART1_TX, EVENTOUT
MCO, TIM2_CH2, LPTIM1_CH2,
2 3 5 D1 PA8 I/O FT_a - SPI3_RDY, USART1_RX, TSC_G1_IO1, ADC4_IN1
SAI1_FS_A, EVENTOUT
TIM2_CH3, I2C3_SDA, USART1_CTS,

ADC4_IN2, WKUP8,
3 4 6 E2 PA7 I/O FT_fa - TSC_G1_IO2, COMP1_OUT,
TAMP_IN1/TAMP_OUT2
SAI1_SCK_A, EVENTOUT
CSTOP, TIM2_CH4, SAI1_CK2,
I2C3_SCL, SPI3_RDY,
4 5 7 E1 PA6 I/O FT_fa - ADC4_IN3, WKUP7
USART1_RTS_DE, TSC_G1_IO3,
SAI1_MCLK_A, EVENTOUT
- - - F2 VSSA S - - - -
5 6 8 F1 VDDA S - - - -
CSLEEP, TIM2_CH1, TIM2_ETR,

SAI1_D2, SPI3_NSS, USART1_CK,
6 7 9 F3 PA5 I/O FT_a - ADC4_IN4, WKUP6
TSC_G1_IO4, AUDIOCLK,
LPTIM2_ETR, EVENTOUT
USART1_CTS, TSC_G4_IO1, ADC4_IN5, WKUP2,

- - - G1 PA4 I/O FT_a -
AUDIOCLK, TIM16_CH1, EVENTOUT TAMP_IN6/TAMP_OUT3
USART1_RTS_DE, TSC_G4_IO2,
- 8 - G2 PA3 I/O FT_a - ADC4_IN6, WKUP5
TIM16_CH1N, EVENTOUT
USART1_CK, TSC_G4_IO3,
- 9 - - PB10 I/O FT_a - -
TIM16_BKIN, EVENTOUT
TIM1_BKIN, TIM3_CH1, SAI1_D1, COMP1_INP1,

7 10 10 G3 PA2 I/O FT_a - USART1_RTS_DE, LPUART1_TX, ADC4_IN7, WKUP4,
TSC_G4_IO4, TIM16_CH1, EVENTOUT LSCO
- 11 11 - VDD S - - - -
TIM1_CH1N, TIM3_CH2, SAI1_CK1,

SPI1_RDY, USART1_CK, COMP1_INM1,
8 12 12 H2 PA1 I/O FT_a -
LPUART1_RX, TSC_G2_IO1, ADC4_IN8, WKUP3
LPTIM2_CH2, TIM17_CH1, EVENTOUT
DS14127 Rev 5 69/149

76
Table 24. Device pin definitions (continued)

Pin
Number
I/O structure
UFQFPN48 SMPS
Notes
UFBGA59 SMPS

UFQFPN32
UFQFPN48
Name (function
Type
after reset)
LPTIM1_IN1, TIM1_CH2N, TIM3_CH3,

COMP2_INP1,
9 13 13 H1 PA0 I/O FT_a - SPI3_SCK, LPUART1_CTS,
ADC4_IN9, WKUP1
TSC_G2_IO2, TIM3_ETR, EVENTOUT
IR_OUT, TIM1_CH3N, TIM3_CH4,

SPI3_MISO, LPUART1_RTS_DE, COMP2_INM1,
10 14 14 H3 PB9 I/O FT_a -
TSC_G2_IO3, LPTIM2_IN1, ADC4_IN10, WKUP8
TIM16_CH1, EVENTOUT
LPTIM1_ETR, TIM1_CH1, USART2_RX,

SPI3_MOSI, TSC_G2_IO4,
11 15 15 H5 PB8 I/O FT_a - PVD_IN
COMP1_OUT, TIM3_ETR,
TIM16_CH1N, EVENTOUT
12 16 16 G4 PC15-OSC32_OUT I/O FT_ - EVENTOUT OSC32_OUT
13 17 17 H4 PC14-OSC32_IN I/O FT_ - EVENTOUT OSC32_IN
- - - E3 VSS S - - - -
WKUP2,
TIM1_BKIN2, TSC_G5_IO1,
- 18 18 G5 PC13 I/O FT_a - RTC_TS/RTC_OUT1,
EVENTOUT
TAMP_IN4/TAMP_OUT5
TIM1_CH4N, TSC_G5_IO2, WKUP5,

- 19 19 H6 PB7 I/O FT_a -
SAI1_SD_B, EVENTOUT TAMP_IN5/TAMP_OUT4
14 - - F5 VDD S - - - -
- - - E5 VSS S - - - -
TIM2_CH1, TIM2_ETR, TSC_G5_IO3,

- 20 20 G6 PB6 I/O FT_a - WKUP3
SAI1_SCK_B, EVENTOUT
TIM3_CH1, SAI1_D2, LPUART1_TX,

- 21 21 H7 PB5 I/O FT_a - -
TSC_G5_IO4, SAI1_FS_B, EVENTOUT
- 22 22 - VDD S - - - -
NJTRST, TIM1_CH3, LPTIM2_IN2,

USART2_RX, SPI1_SCK, TSC_G3_IO1,
15 23 23 H8 PB4 I/O FT_a - SAI1_MCLK_B, TIM17_CH1, -
PTA_ACTIVE, PTA_PRIORITY,
EVENTOUT
JTDO/TRACESWO, TIM1_CH4,
LPTIM1_IN2, USART2_CK, I2C1_SDA,
16 24 24 G7 PB3 I/O FT_fa - SPI1_MISO, TSC_G3_IO2, -
TIM17_CH1N, PTA_ACTIVE,
EVENTOUT
70/149 DS14127 Rev 5


Pin
Number
I/O structure
UFQFPN48 SMPS
Notes
UFBGA59 SMPS

UFQFPN32
UFQFPN48
Name (function
Type
after reset)
JTDI, TIM1_ETR, LPTIM1_CH2,

USART2_RTS_DE, I2C1_SCL,
17 25 25 G8 PA15 I/O FT_fa - SPI1_MOSI, TSC_G3_IO3, -
TIM17_BKIN, PTA_STATUS,
EVENTOUT
JTCK/SWCLK, USART2_TX,
18 26 26 F6 PA14 I/O FT_ - COMP2_OUT, PTA_STATUS, TAMP_IN3/TAMP_OUT6
EVENTOUT
JTMS/SWDIO, IR_OUT,
19 27 27 F8 PA13 I/O FT_ - -
PTA_PROIORITY, EVENTOUT
TIM1_CH2, USART2_TX, SPI1_NSS,

TSC_G3_IO4, RF_ANTSW0,
20 28 28 F7 PA12 I/O FT_a - WKUP6
COMP2_OUT, PTA_STATUS,
EVENTOUT
TIM1_CH1, USART2_RX, RF_ANTSW1,

- 29 29 E8 PA11 I/O FT_ - -
LPTIM2_CH1, EVENTOUT
TIM1_CH1N, USART2_CTS, I2C1_SCL,

- 30 30 E7 PB2 I/O FT_f - WKUP1, RTC_OUT2
I2C3_SCL, RF_ANTSW2, EVENTOUT
TIM1_CH2N, USART2_RTS_DE,
- 31 31 D8 PB1 I/O FT_f - WKUP4
I2C1_SDA, I2C3_SDA, EVENTOUT
TIM1_CH3N, LPTIM2_IN2,
- 32 32 D7 PB0 I/O FT_ - -
USART2_TX, EVENTOUT
TIM1_BKIN2, USART2_CTS,
I2C1_SMBA, I2C3_SMBA,
21 33 33 C8 PB15 I/O TT_ - -
LPUART1_CTS, RF_EXTPABYP,
TIM16_BKIN, PTA_GRANT, EVENTOUT
RF_EXTPABYP, PTA_GRANT,
22 34 34 C7 PH3-BOOT0 I/O TT_ - TAMP_IN2/TAMP_OUT1
EVENTOUT
23 35 35 C6 VDD S - - - -
- - - D6 VSS S - - - -
24 36 36 B8 NRST I/O RST - - -
25 37 37 A8 RF I/O RF - - -
- - - A7 VSSRF S - - - -
26 38 38 B4 VDDHPA S - - - -
- - - B7 VSSRF S - - - -
- - 39 B6 VDDANA S - - - -
27 39 40 A6 VDDRF S - - - -
28 40 41 A5 OSC_OUT O RF - - -
DS14127 Rev 5 71/149

76

Pin
Number
I/O structure
UFQFPN48 SMPS
Notes
UFBGA59 SMPS

UFQFPN32
UFQFPN48
Name (function
Type
after reset)
29 41 42 B5 OSC_IN I RF - - -
30 42 43 A4 VDDRFPA S - - - -
- - - E4 VDD S - - - -
31 43 44 D5 VDD S - - - -
32 44 - - VCAP S - - - -
- - 45 C3 VDD11 S - - - -
TIM3_CH1, SAI1_D1, LPUART1_RX,

- 45 46 A3 PA10 I/O FT_ - -
EVENTOUT
TIM3_CH2, SAI1_CK1,
- 46 47 B3 PA9 I/O FT_ - -
LPUART1_RTS_DE, EVENTOUT
RTC_REFIN, TIM3_CH3, USART1_TX,

- 47 48 A2 PB14 I/O FT_a - WKUP7
TSC_G6_IO1, SAI1_SD_A, EVENTOUT
- 48 - B2 PB13 I/O FT_a - TIM3_CH4, TSC_G6_IO2, EVENTOUT -
33 49 49 - VSS (exposed pad) S - - - -
72/149 DS14127 Rev 5

4.1 Alternate functions
STM32WBA5xxx
Table 25. Alternate function AF0 to AF7(1)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Port
LPTIM1/2
LPTIM1/SYS_AF TIM1/2 USART2 I2C1/3 SPI1 I2C3/SPI3 USART1
/TIM1/2/3
PA0 LPTIM1_IN1 TIM1_CH2N TIM3_CH3 - - - SPI3_SCK -

PA1 - TIM1_CH1N TIM3_CH2 - - SPI1_RDY - USART1_CK
PA2 - TIM1_BKIN TIM3_CH1 - - - - USART1_RTS_DE
PA3 - - - - - - - USART1_RTS_DE
PA5 CSLEEP TIM2_CH1 TIM2_ETR - - - SPI3_NSS USART1_CK
PA6 CSTOP TIM2_CH4 - - I2C3_SCL - SPI3_RDY USART1_RTS_DE
PA7 - TIM2_CH3 - - I2C3_SDA - USART1_CTS
DS14127 Rev 5
A PA8 MCO TIM2_CH2 LPTIM1_CH2 - - - SPI3_RDY USART1_RX

PA9 - - TIM3_CH2 - - - - -
PA10 - - TIM3_CH1 - - - - -
PA11 - TIM1_CH1 - USART2_RX - - - -
PA12 - TIM1_CH2 - USART2_TX - SPI1_NSS - -
PA13 JTMS/SWDIO IR_OUT - - - - - -
PA14 JTCK/SWCLK - - USART2_TX - - - -
Pinouts and pin description

PA15 JTDI TIM1_ETR LPTIM1_CH2 USART2_RTS_DE I2C1_SCL SPI1_MOSI - -
73/149
Table 25. Alternate function AF0 to AF7(1) (continued)
74/149

Port
LPTIM1/2
LPTIM1/SYS_AF TIM1/2 USART2 I2C1/3 SPI1 I2C3/SPI3 USART1
/TIM1/2/3
PB0 - TIM1_CH3N LPTIM2_IN2 USART2_TX - - - -

PB1 - TIM1_CH2N - USART2_RTS_DE I2C1_SDA - I2C3_SDA -
PB2 - TIM1_CH1N - USART2_CTS I2C1_SCL - I2C3_SCL -
JTDO/
PB3 TIM1_CH4 LPTIM1_IN2 USART2_CK I2C1_SDA SPI1_MISO - -
TRACESWO
PB4 NJTRST TIM1_CH3 LPTIM2_IN2 USART2_RX - SPI1_SCK - -
PB5 - - TIM3_CH1 - - - - -
PB6 - TIM2_CH1 TIM2_ETR - - - - -
PB7 - TIM1_CH4N - - - - -
DS14127 Rev 5
B
PB8 LPTIM1_ETR TIM1_CH1 TIM3_ETR USART2_RX - - SPI3_MOSI -
PB9 - TIM1_CH3N TIM3_CH4 IR_OUT - - SPI3_MISO -
PB10 - - - - - - - USART1_CK
PB11 LPTIM1_CH1 - LPTIM1_ETR - - - - -
PB12 - TIM2_CH1 TIM2_ETR - - SPI1_RDY - USART1_TX
PB13 - - TIM3_CH4 - - - - -
PB14 RTC_REFIN - TIM3_CH3 - - - - USART1_TX
PB15 - TIM1_BKIN2 - USART2_CTS I2C1_SMBA - I2C3_SMBA -
PC13 - - TIM1_BKIN2 - - - - -
C PC14 - - - - - - - -
STM32WBA5xxx
PC15 - - - - - - - -
H PH3 - - - - - - - -
1. For AF8 to AF15 refer to Table 26.
Table 26. Alternate function AF8 to AF15(1)
STM32WBA5xxx
Port
LPTIM2/
LPUART1 TSC - - - LPTIM2 EVENTOUT
TIM3/16/17
PA0 LPUART1_CTS TSC_G2_IO2 - - - - TIM3_ETR EVENTOUT

PA1 LPUART1_RX TSC_G2_IO1 - - - LPTIM2_CH2 TIM17_CH1 EVENTOUT
PA2 LPUART1_TX TSC_G4_IO4 - - - - TIM16_CH1 EVENTOUT
PA3 - TSC_G4_IO2 - - - - TIM16_CH1N EVENTOUT
PA5 - TSC_G1_IO4 - - - - LPTIM2_ETR EVENTOUT
PA6 - TSC_G1_IO3 - - - - - EVENTOUT
A PA8 - TSC_G1_IO1 - - - - - EVENTOUT
DS14127 Rev 5
PA9 LPUART1_RTS_DE - - - - - - EVENTOUT

PA10 LPUART1_RX - - - - - - EVENTOUT
PA11 - - - - - - LPTIM2_CH1 EVENTOUT
PA13 - - - - - - - EVENTOUT
PA14 - - - - - - - EVENTOUT
PA15 - TSC_G3_IO3 - - - - TIM17_BKIN EVENTOUT

75/149
Table 26. Alternate function AF8 to AF15(1) (continued)
76/149

Port
LPTIM2/
LPUART1 TSC - - - LPTIM2 EVENTOUT
TIM3/16/17
PB0 - - - - - - - EVENTOUT
PB1 - - - - - - - EVENTOUT
PB2 - - - - - - - EVENTOUT
PB3 - TSC_G3_IO2 - - - - TIM17_CH1N EVENTOUT
PB4 - TSC_G3_IO1 - - - - TIM17_CH1 EVENTOUT
PB5 LPUART1_TX TSC_G5_IO4 - - - - - EVENTOUT
PB6 - TSC_G5_IO3 - - - - - EVENTOUT
B
DS14127 Rev 5
PB8 - TSC_G2_IO4 - - - - TIM16_CH1N EVENTOUT

PB9 LPUART1_RTS_DE TSC_G2_IO3 - - - LPTIM2_IN1 TIM16_CH1 EVENTOUT
PB10 - TSC_G4_IO3 - - - - TIM16_BKIN EVENTOUT
PB11 LPUART1_TX - - - - - - EVENTOUT
PB12 - TSC_SYNC - - - - TIM3_ETR EVENTOUT
PB15 LPUART1_CTS - - - - - TIM16_BKIN EVENTOUT
PC13 - TSC_G5_IO1 - - - - - EVENTOUT
C PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
STM32WBA5xxx
H PH3 - - - - - - - EVENTOUT
1. For AF0 to AF7 refer to Table 25.
STM32WBA5xxx Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TA max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3σ).
5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C and supply voltage
VDD = VDDA = VDDRF = 3 V. They are only given as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error lower than or equal to the value indicated (mean ± 2σ).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines, and are
not tested.
5.1.4 Loading capacitor

Unless otherwise specified, the loading conditions used for pin parameter measurement are
shown in Figure 11.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions Figure 12. Pin input voltage
MCU pin MCU pin

C = 50 pF
VIN
MS19210V1
MS19211V1
DS14127 Rev 5 77/149

136
Electrical characteristics STM32WBA5xxx
5.1.6 Power supply scheme
Figure 13. Power supply scheme with LDO
VCAP Backup circuitry

4.7 μF (LSE, RTC, TAMP
and backup registers)
VDD VCORE
n x VDD VDDIO
Regulator
n x 100 nF
+ 10 μF
OUT
Level shifter
GPIOs IO (CPU, digital
IN
logic and memories)
VSS
VDDA
VDDA VDDA
100 nF VREF+
+ 1 μF
VREF- ADC
VSSA
VDD
VDDRFPA
100 nF
VDDHPA
2.4 GHz RADIO
470 nF VDD
VDDRF
100 nF VSSRF
DT56257V2
(Exposed pad) VSS VSS
To all modules
78/149 DS14127 Rev 5

Figure 14. Power supply scheme with SMPS
Backup circuitry
(LSE, RTC, TAMP,
VDD VCORE
n x VDD VDDIO
Regulator
n x 100 nF
+ 10 μF
OUT
Level shifter
GPIOs IO (CPU, digital
IN
logic and memories)
VSS
VDDA
VDDA VDDA
100 nF VREF+
+ 1 μF ADC
VREF- COMPs
VSSA(1) VSSA 1. VSSA pin is not available
VDD on all packages. When not
available, it is connected to
VDDSMPS VSS pin.
SMPS / LDO
10 μF VLXSMPS regulator 2. VSSRF pin is not
available on all packages.
2.2 μH When not available, it is
VDD11 connected to VSS pin.
4.7 μF
VSSSMPS
VDDANA
100 nF
VDDRFPA
100 nF VDDHPA 2.4 GHz RADIO

470 nF VDD
VDDRF
100 nF
n x VSSRF(2) VSSRF
MS56522V1
(Exposed pad) n x VSS VSS

To all modules
DS14127 Rev 5 79/149

136
Figure 15. Power supply scheme with SMPS (high RF power)
Backup circuitry
(LSE, RTC, TAMP,
VDD VCORE
n x VDD VDDIO
Regulator
n x 100 nF
+ 10 μF
OUT
Level shifter
GPIOs IO (CPU, digital,
IN
logic and memories)
VSS
VDDA
VDDA VDDA
100 nF VREF+
+ 1 μF ADC
VREF- COMPs
1. VSSA pin is not available
VSSA(1) VSSA on all packages. When not
VDD available, it is connected to
VSS pin.
VDDSMPS
SMPS / LDO 2. VSSRF pin is not available
10 μF VLXSMPS regulator on all packages. When not
available, it is connected to
2.2 μH
VSS pin.
VDD11
4.7 μF
VSSSMPS
VDDANA
100 nF
VDD VDDRFPA
VDDHPA 2.4 GHz RADIO

100 nF
470 nF VDD
VDDRF
100 nF
n x VSSRF(2) VSSRF
MS56524V1
(Exposed pad) n x VSS VSS

To all modules
Caution: Each power supply pair (VDD / VSS, VDDA / VSS, VDDRFPA / VSS, VDDRF / VSS) must be
decoupled with filtering ceramic capacitors as shown. These capacitors must be placed as
close as possible to (or below) the appropriate pins to ensure correct device functionality.
Caution: VDD and VDDRF must be connected to the same supply.
5.1.7 Current consumption measurement

The IDD parameters in the tables in the next sections represent the total MCU consumption,
including the current supplying VDD, VDDA, VDDRF, VDDRFPA, and VDDSMPS (if the device
embeds the SMPS), or the total 2.4 GHz RADIO current supplying VDDRF and VDDRFPA.
80/149 DS14127 Rev 5

Figure 16. Current consumption measurement scheme
SMPS supply scheme SMPS supply scheme

LDO supply scheme
High transmit output power Low transmit output power
IDD IDD IDD

VDD VDD VDD
VDDSMPS VDDSMPS
VDDA VDDA VDDA
VDDRF VDDRF VDDRF
DT56256V1
VDDRFPA VDDRFPA
5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 27, Table 28, and Table 29
can cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods can affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended
mission profiles are available on demand.
Table 27. Voltage characteristics(1)

Symbol Ratings Min Max Unit
External main supply voltage

VDDX - VSS (including VDD, VDDA, VDDRF, VDDRFPA, -0.3 4.0
VDDANA, VDDSMPS)
V
Input voltage on FT_ (any option) pins min (min (VDD, VDDA) + 4.0, 6.0)(3)(4)
VIN(2) VSS - 0.3
Input voltage on any other pin 4.0
Variations between different VDDX power
|∆VDDx| - 50.0
pins of the same domain
mV
Variations between all the different
|VSSx-VSS| - 50.0
ground pins
1. All main power (VDD, VDDA, VDDRF, VDDRFPA, VDDANA, VDDSMPS) and ground (VSS, VSSA, VSSRF, VSSSMPS)
pins must always be connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 28 for the maximum allowed injected current values.
3. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
4. This formula applies only to power supplies related to the I/O structure described by the pin definition table. The maximum
I/O input voltage is the smallest value between min (VDD, VDDA) + 4.0 V, and 6.0 V.
DS14127 Rev 5 81/149

136
Table 28. Current characteristics

Symbol Ratings Max Unit
∑IVDD Total current into sum of all VDD power lines (source)(1) 200
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 200
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
IIO Output current sunk by any I/O and control pin 20 mA
(2)
Total output current sunk by sum of all I/Os and control pins 120
∑I(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 120
IINJ(PIN)(3)(4) Injected current on FT_xxx, TT_xx, RST pins –5/+0
∑|IINJ(PIN)| (5)
Total injected current (sum of all I/Os and control pins) ±25
1. All main power (VDD, VDDA, VDDRF, VDDRFPA, VDDANA, VDDSMPS) and ground (VSS, VSSA, VSSRF, VSSSMPS)
pins must always be connected to the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 27 for the maximum
allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
Table 29. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150

°C
TJMAX Maximum junction temperature 140
5.3 Operating conditions
5.3.1 Summary of main performance
Table 30. Main performance at VDD = 3.3 V

Parameter Test conditions Typ Unit
Standby (64 Kbytes RAM retention) 0.93

µA
Stop 1 6.5
Core current Sleep (VDD = 3.0 V, 16 MHz) 0.22

IDD
consumption Run (100 MHz) 3.35
mA
Radio BLE Rx 1 Mbps(1) 4.41
Radio BLE Tx 0 dBm output power(1) 5.24
82/149 DS14127 Rev 5

Table 30. Main performance at VDD = 3.3 V (continued)

Parameter Test conditions Typ Unit
Advertising using Standby mode(2)

Peripheral 10.7
(Tx = 0 dBm; Period 1.28 s; 31 bytes, 3 channels)
IDD current BLE µA
consumption Advertising using Standby mode(2)
2.6
(Tx = 0 dBm, 6 bytes; period 10.24 s, 3 channels)
1. Power consumption including RF subsystem and digital processing.
2. Power consumption integrated over 100 s, including Cortex-M33, 2.4 GHz RADIO subsystem and digital processing.
5.3.2 General operating conditions
Table 31. General operating conditions

Symbol Parameter Conditions Min Typ Max Unit
VDD Standard operating voltage - 1.71(1) - 3.6 V

Supply voltage for internal
VDDSMPS - VDD V
SMPS step-down converter
ADC used 1.62 -
VDDA Analog supply voltage COMP used 1.58 - 3.6 V
ADC, COMP not used 0 -
VDDRF RF operating voltage - 1.71 - 3.6 V
RF power amplifier
VDDRFPA - 1.15(2) - 3.6 V
operating voltage
All I/Os FT_ Min (min (VDD, VDDA) +
VIN I/O input voltage –0.3 - V
(any option) pins 3.6 , 5.5 )(3)(4)
Range 1 1.15 1.21 1.27
VCORE Internal regulator ON V
Range 2 0.81 0.90 0.99
Internal AHB1, AHB2, and Range 1 - - 100

fHCLK
AHB4 clock frequency Range 2 - - 16
Internal APB1, APB2, and Range 1 - - 100

fPCLK MHz
APB7 clock frequency Range 2 - - 16
Internal AHB5 clock Range 1 - - 32

fHCLK5
frequency Range 2 - - 12
Internal AHB1, AHB2 and
∆fHCLK1 AHB4 clock incremental - - - 84 MHz
frequency step(5)
See Section 6.5 for appropriate thermal
Power dissipation at
resistance and package. Power
TA = 85 °C (suffix 6 version) UFQFPN32
dissipation is calculated according to
PD or UFQFPN48 mW
ambient temperature (TA), maximum
TA = 105 °C (suffix 7 UFBGA59 junction temperature (TJ), and selected
version)
thermal resistance.
DS14127 Rev 5 83/149

136
Table 31. General operating conditions (continued)

Ambient temperature Max power dissipation 85

TA –40 - °C
(suffix 6 version) Low-power dissipation(6) 105
Ambient temperature for Max power dissipation 105

TA –40 - °C
the suffix 7 version Low-power dissipation (6)
120
Suffix 6 version - 105
TJ Junction temperature range –40 °C
Suffix 7 version(7) 120
1. When RESET is released functionality is guaranteed down to VBORx min.
2. When the 2.4 GHz RADIO is active, when inactive supply can go down to 0 V.
3. This formula applies only to power supplies related to the I/O structure described by the pin definition table. The maximum
I/O input voltage is the smallest value between min (VDD, VDDA) + 3.6 V and 5.5 V.
4. For operation with voltages higher than min (VDD, VDDA) + 0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Without system clock frequency step limiting.
6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Section 6.5).
7. Junction temperature above 105 °C must be limited to 30% of 10 years life time.
5.3.3 RF characteristics
Table 32. Generic RF transmitter characteristics(1)

Symbol Parameter Test conditions Standard Min Typ Max Unit
VDDRFPA ≥ 2.50 V - - 9.5 -

Ptxmax Maximum output power
VDDRFPA ≥ 1.71 V - - 7.5 - dBm
Ptxmin Minimum output power - - - -20 -
∆Ptx Output power step - - - 1 -
Output power ± variation over Ptxmax max setting - - 0.4 -

Pfreqband dB
the frequency band
Output power ± variation over Ptxmax max setting

Ptemp - - 2.9 -
the temperature -40 °C ≤ Tj ≤ +105 °C
P2ndHARM Second harmonic Ptxmax max setting - - TBD -

P3rdHARM Third harmonic Ptxmax max setting - - TBD -
Out of band spurious < 1 GHz Ptxmax max setting - TBD -

OBSE1Mbps (2) dBm
emission 1 Mbps ≥ 1 GHz Ptxmax max setting - TBD -

OBSE2Mbps (2)
1. Evaluated by characterization, not tested in production, unless otherwise specified. Measured in conducted mode, based
on reference design (see AN5165), using output power specific external RF filter and impedance matching networks to
interface with a 50 Ω antenna.
2. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440
Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
84/149 DS14127 Rev 5

Table 33. Generic RF receiver characteristics(1)

Rssimax RSSI maximum value - - - -32 -

dBm
Rssimin RSSI minimum value - - - -75 -
Rssiaccu RSSI accuracy - - - ±6 - dB
Table 34. RF Bluetooth Low Energy characteristics

Symbol Parameter Test conditions Min Typ Max Unit
Fop Frequency channel operating band - 2402 - 2480 MHz
∆F Delta frequency - - 250 - kHz
Rgfsk On air data rate - 0.125 - 2 Mbps
PLLres RF channel spacing - - 2 - MHz
Table 35. RF transmitter Bluetooth Low Energy characteristics(1)

BW6dB1Mbps 6 dB signal bandwidth Ptxmax max setting - - TBD -

kHz
BW6dB2Mbps 6 dB signal bandwidth Ptxmax max setting - - TBD -
2 MHz - -20 - -41 -20

IBSE1Mbps In band spurious emission dBm
≥ 3 MHz - -30 - -47.5 -30
4 MHz - -20 - -42.5 -20
IBSE2Mbps In band spurious emission 5 MHz - -20 - -44 -20 dBm
≥ 6 MHz - -30 -45 -30
fd Frequency drift - ±50 -50 - +50 kHz
Uncoded - ±20 -20 - +20 kHz/

drmax Maximum drift rate
- ±19.2 -19.2 - +19.2 50 µs
Coded
fo Frequency offset - ±150 -150 - +150
∆f11Mbps Frequency deviation average 1 Mbps - 225 - 275 225 - 275
∆f12Mbps Frequency deviation average 2 Mbps - 450 - 550 450 - 550
Frequency deviation average kHz

∆f1CodedS8 - 225 - 275 225 - 275
Coded S = 8
∆f21Mbps Frequency deviation 99.9% 1 Mbps 185 185 - -
∆f22Mbps Frequency deviation 99.9% 2 Mbps 370 370 - -
DS14127 Rev 5 85/149

136
Table 36. RF receiver Bluetooth Low Energy characteristics (1)

Prxmax Maximum input signal PER ≤ 30.8% -10 - 6 - dBm

SMPS bypass(3) - TBD -
Psens2Mbps(2) Sensitivity 2 Mbps -70
SMPS on(3) - -93 -
Psens1Mbps(2) Sensitivity 1 Mbps
(3)
-70
SMPS on - -96 -
dBm
Psens500kbps(2) Sensitivity 500 kbps -75
SMPS on(3) - -99 -
Psens125kbps(2) Sensitivity 125 kbps -82
SMPS on(3) - -102 -
|f2 - f1| = 3 MHz -50 -37 -
PIMD1Mbps Intermodulation 1Mbps |f2 - f1| = 4 MHz -50 -50 -27 -
|f2 - f1| = 5 MHz -50 -28 -
30 to 2000 MHz -30 -30 -10 - dBm
Out of band blocking (for desired 2000 to 2399 MHz -35 -35 -22 -
POBB1Mbps
signal at -67 dBm and 1 Mbps) 2484 to 2999 MHz -35 -35 -15 -
3 to 12.75 GHz -30 -30 -10 -
|f2 - f1| = 3 MHz -50 -37 -
PIMD2Mbps Intermodulation 2Mbps |f2 - f1| = 4 MHz -50 -50 -30 -
|f2 - f1| = 5 MHz -50 -30 -
30 to 2000 MHz -30 -30 -10 - dBm
Out of band blocking (for desired 2000 to 2399 MHz -35 -35 -33 -
POBB2Mbps
signal at -67 dBm and 2 Mbps) 2484 to 2999 MHz -35 -35 -19 -
3 to 12.75 GHz -30 -30 -10 -
C/Ico125kbps Co-channel rejection 125 kbps - 12 - 3 -
Adj = ±1 MHz 6 - -2 6
Adj = 2 MHz -26 - -38 -26
Adjacent channel interference Adj-Image = -2 MHz -18 - -27 -18 dB

C/I125kbps
125 kbps Adj ≥ 3 MHz -36 - -43 -36
Adj = -3 MHz -24 - -28 -24
Adj ≤ -4 MHz -36 - -43 -36
86/149 DS14127 Rev 5

Table 36. RF receiver Bluetooth Low Energy characteristics (1) (continued)

C/Ico250kbps Co-channel rejection 250 kbps - 17 - 5 17
Adj = ±1 MHz 11 - -2 11
Adj = 2 MHz -21 - -34 -21
Adjacent channel interference Adj-Image = -2 MHz -13 - -26 -13

C/I500kbps
500 kbps Adj ≥ 3 MHz -31 - -39 -31
Adj = -3 MHz -19 - -27 -19
Adj ≤ -4 MHz -31 - -37 -31
C/Ico1Mbps Co-channel rejection 1 Mbps - 21 - 8 21
Adj = ±1 MHz 15 - 0 15
Adj = 2 MHz -17 - -38 -17

C/I1Mbps
1 Mbps Adj ≥ 3 MHz -27 - -36 -27
Adj = -3 MHz -15 - -27 -15
Adj ≤ -4 MHz -27 - -38 -27
C/Ico2Mbps Co-channel rejection 2 Mbps - 21 - 8 21
Adj = ±2 MHz 15 - 0 15
Adj = 4 MHz -17 - -35 -17

C/I2Mbps
2 Mbps Adj = ≥ 6 MHz -27 - -33 -27
Adj = -6 MHz -15 - -26 -15
Adj = ≤ -8 MHz -27 - -34 -27
2. With ideal transmitter.
3. BER (%) for maximum supported payload length, as defined in the Bluetooth core specification v5.4.
Table 37. RF Bluetooth Low Energy power consumption for VDD = 3.3 V(1)(2)
Symbol Parameter Typ Unit
Tx 0 dBm output power consumption (LDO) 10.51

Tx 0 dBm output power consumption (SMPS ON, VDDRFPA connected to VDD) 5.54
Itx Tx 0 dBm output power consumption (SMPS ON, VDDRFPA connected to VDD11) 5.24 mA
Tx +10 dBm output power consumption (LDO) 21.15
Tx +10 dBm output power consumption (SMPS ON, VDDRFPA connected to VDD) 19.40
DS14127 Rev 5 87/149

136
Table 37. RF Bluetooth Low Energy power consumption for VDD = 3.3 V(1)(2) (continued)
Rx consumption 1 Mbps (LDO) 7.91

Rx consumption 1 Mbps (SMPS ON, VDDRFPA connected to VDD) 5.22
Rx consumption 1 Mbps (SMPS ON, VDDRFPA connected to VDD11) 4.41
Irx mA
Rx consumption 2 Mbps (LDO) TBD
Rx consumption 2 Mbps (SMPS ON, VDDRFPA connected to VDD) TBD
Rx consumption 2 Mbps (SMPS ON, VDDRFPA connected to VDD11) TBD
1. Evaluated by characterization, not tested in production, unless otherwise specified.
2. Power consumption including 2.4 GHz RADIO subsystem and digital processing.
5.3.4 RF IEEE802.15.4 characteristics
Table 38. RF IEEE802.15.4 characteristics(1)

Symbol Parameter Conditions Standard Min Typ Max Unit
Fop Frequency channel operating band - - 2405 - 2480

MHz
∆F Delta frequency - - - 5 -
Roqpsk On air data rate - - 250 - kbps
PLLres RF channel spacing - - - 5 - MHz
1. Guaranteed by characterization results, unless otherwise specified. Measured in conducted mode, based on reference
design (see AN5165), using output power specific external RF filter and impedance matching networks to interface with a
50 Ω antenna.
Table 39. RF transmitter IEEE802.15.4 characteristics(1)

VDDRFPA ≥ 2.50 V - - 9.5 -

Ptxmax Maximum output power
VDDRFPA ≥ 1.71 V - - 7.5 - dBm
Ptxmin Minimum output power - - - -15 -
∆Ptx Output power step - - 0.5 1 2
Output power ± variation over Ptxmax max setting - - 0.5 -

Pfreqband dB
the frequency band
Output power ± variation over Ptxmax max setting

Ptemp - - TBD -
the temperature -40 °C ≤ Tj ≤ +130 °C
P2ndHARM Second harmonic Ptxmax max setting - - TBD -

P3rdHARM Third harmonic Ptxmax max setting - - TBD -

OBSE1Mbps (2) dBm

OBSE2Mbps (2)
88/149 DS14127 Rev 5

2. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440
Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
Table 40. RF receiver IEEE802.15.4 characteristics(1)

Symbol Parameter Conditions Standard Min Typ Max Unit
Prxmax Maximum input signal PER ≤ 1 % -20 - -20 -

Sensitivity 250 kbps (LDO) -85 - -97.5 -
Psens250kbps PER ≤ 1 %
Sensitivity 250 kbps (SMPS ON) -85 - -97.5 - dBm
C/Iadj Adjacent channel rejection - 0 - 10 -

dB
C/Ialt Alternate channel rejection - 30 - 30 -
1. Guaranteed by characterization results, unless otherwise specified. Measured in conducted mode, based on reference
design (see AN5165), using output power specific external RF filter and impedance matching networks to interface with a
50 Ω antenna.
Table 41. RF IEEE802.15.4 power consumption for VDD = 3.3 V(1)(2)

Tx 0 dBm output power consumption (LDO) 13.6

Tx 0 dBm output power consumption (SMPS ON, VDDRFPA connected to VDD) 7.2
Itx Tx 0 dBm output power consumption (SMPS ON, VDDRFPA connected to VDD11) TBD
Tx +10 dBm output power consumption (LDO) 25.3
mA
Tx +10 dBm output power consumption (SMPS ON, VDDRFPA connected to VDD) 22.7
Rx consumption (LDO) 10.2
Irx Rx consumption (SMPS ON, VDDRFPA connected to VDD) 6.25
Rx consumption (SMPS ON, VDDRFPA connected to VDD11) TBD
1. Guaranteed by characterization results, unless otherwise specified.
2. Power consumption including 2.4 GHz RADIO subsystem and digital processing.
5.3.5 Operating conditions at power-up/power-down

The parameters in Table 42 are evaluated by characterization under ambient temperature
and supply voltage conditions summarized in Table 31.
Table 42. Operating conditions at power-up / power-down(1)

Symbol Parameter Conditions Min Max Unit
VDD rise time rate - 0 ∞ µs/V

tVDD ULPMEN = 0 20 ∞ µs/V
VDD fall time rate
Standby mode with ULPMEN = 1 250 ∞ ms/V
DS14127 Rev 5 89/149

136
5.3.6 Embedded reset and power control block characteristics

The parameters in Table 43 are derived under ambient temperature and supply voltage
conditions summarized in Table 31.
Table 43. Embedded reset and power control block characteristics

tRSTTEMPO(1) Reset temporization after VBOR0 threshold detection VDD rising - - 900 μs
VDD rising 1.60 1.66 1.71
VBOR0(2) Brown-out reset threshold 0
VDD falling 1.58 1.64 1.69
VDD rising 1.98 2.08 2.17
VDD falling 1.90 2.00 2.10
VDD rising 2.18 2.29 2.39
VBOR2(2) Brown-out reset threshold 2 V
VDD falling 2.08 2.18 2.25
VDD rising 2.48 2.59 2.70
VDD falling 2.39 2.50 2.61
VDD rising 2.76 2.88 3.00
VDD falling 2.67 2.79 2.90
VDD rising 2.03 2.13 2.23
VPVD0(2) Programmable voltage detector threshold 0
VDD falling 1.93 2.03 2.12
VDD rising 2.18 2.29 2.39
VPVD1(2) PVD threshold 1
VDD falling 2.08 2.18 2.28
VDD rising 2.33 2.44 2.55
VDD falling 2.23 2.34 2.44
VDD rising 2.47 2.59 2.70
VPVD3(2) PVD threshold 3 V
VDD falling 2.39 2.50 2.61
VDD rising 2.60 2.72 2.83
VDD falling 2.50 2.62 2.73
VDD rising 2.76 2.88 3.00
VDD falling 2.66 2.78 2.90
VDD rising 2.83 2.96 3.08
VDD falling 2.76 2.88 3.00
Vhyst_BOR0(2) BOR0 hysteresis voltage - - 20 -
mV
Vhyst_BOR_PVD(2) BOR1, 2, 3, 4 and PVD hysteresis voltage - - 80 -
tsampling_BOR0(2) BOR0 ultra-low power sampling monitoring period ULPEN = 1 - 12 30 ms
BOR1, 2, 3, 4 and PVD consumption from VDD,
IDD_BOR_PVD(1) and additional BOR0 consumption for ULPMEN = 0 - - 1.7 2.5 μA
vs. ULPMEN = 1 (3)
1. Specified by design, not tested in production.
90/149 DS14127 Rev 5

2. Evaluated by characterization, not tested in production.

3. BOR0 is enabled in all modes, its consumption is therefore included in the supply current characteristics tables.
5.3.7 Embedded voltage reference

The parameters in Table 44 are derived under ambient temperature and supply voltage
conditions summarized in Table 31.
Table 44. Embedded internal voltage reference

Range 1 1.175 1.209 1.243

VREFINT(1) Internal reference voltage Range 2 V
1.170 1.206 1.248
and low power modes
ADC sampling time when reading
tS_vrefint(2) - 11.25 - -
the internal reference voltage(3)
µs
Start time of reference voltage
tstart_vrefint(2) - - 4 6
buffer when ADC is enabled
Internal reference voltage spread VDD = 3 V,
∆VREFINT(4) - 8.2 - mV
over the temperature range –40 °C ≤ TJ ≤ +130 °C
TCoeff(4) Temperature coefficient –40 °C ≤ TJ ≤ +130 °C - 40 - ppm/°C
ACoeff(2) Long term stability 1000 hours, T = 25 °C - 400 - ppm
VDDCoeff(4) Voltage coefficient 3.0 V ≤ VDD ≤ 3.6 V - 500 - ppm/V
1. VREFINT does not take into account package and soldering effects.
3. The shortest sampling time can be determined in the application by multiple iterations.
Figure 17. VREFINT vs. temperature
DS14127 Rev 5 91/149

136
5.3.8 Supply current characteristics

The current consumption is measured as described in Section 5.1.7. It depends upon
several parameters, such as operating voltage, ambient temperature, I/O pin loading, device
software configuration, operating frequency, I/O pin switching rate, program location in
memory, and executed binary code.
Typical and maximum current consumption

The MCU is put under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled, except when otherwise mentioned
• The flash memory and SRAM access time is adjusted with the minimum wait states
number, depending upon the fHCLK frequency (refer to tables in the reference manual).
• When the peripherals are enabled fPCLKx = fHCLK1
• The voltage scaling is adjusted to fHCLK frequency as follows:
– Voltage range 1 for 16 MHz < fHCLK1 ≤ 100 MHz and 12 MHz < fHCLK5 ≤ 32 MHz
– Voltage range 2 for fHCLK1 ≤ 16 MHz and fHCLK5 ≤ 12 MHz
The parameters given in Table 45 and Table 46 are evaluated by characterization under
ambient temperature and supply voltage conditions summarized in Table 31.
Table 45. Current consumption in Run modes on LDO, code with data processing running
from flash memory, Cache ON (1-way), prefetch OFF, VDD = 3.3 V(1)(2)(3)
Conditions Typ
Symbol Parameter Unit
- Voltage fHCLK1 25 °C 55 °C 85 °C
scaling
fHCLK1 = fHSI16 = 16 MHz Range 2 16 MHz 0.91 0.95 1.10
Supply
IDD(Run) current in fHCLK1 = fHSE32 = 32 MHz 32 MHz 2.29 2.41 2.73 mA
Run mode Range 1
fHCLK1 = HSE32 + PLL > 32 MHz 100 MHz 6.16 6.30 6.63
2. Reduced code used for characterization.
3. All peripherals disabled, SRAM1 and SRAM2 enabled.
Table 46. Current consumption in Run modes on SMPS, code with data processing running
from flash memory, Cache ON (1-way), prefetch OFF, VDD = 3.3 V(1)(2)(3)
Conditions Typ
- Voltage fHCLK1 25 °C 55 °C 85 °C
scaling
Supply
IDD(Run) current in fHCLK1 = fHSE32 = 32 MHz 32 MHz 1.47 1.55 1.73 mA
Run mode Range 1
2. Reduced code used for characterization results
3. All peripherals disabled, SRAM1 and SRAM2 enabled.
92/149 DS14127 Rev 5

STM32WBA5xxx
Table 47. Current consumption in Run mode on LDO, with different codes running
from flash memory, Cache ON (2-way), Prefetch OFF(1)
Typ Typ
Conditions
Symbol Parameter 25 °C Unit 25 °C Unit
- Voltage scaling Code 1.8 V 3.0 V 3.3 V 1.8 V 3.0 V 3.3 V
Reduced code 0.96 0.96 0.96 59.7 59.7 59.8

®
Coremark 0.96 0.96 0.96 60.2 60.2 60.2
Range 2, SecureMark 1.00 1.00 1.01 62.8 62.8 62.8

fHCLK1 = fHSI16 = 16 MHz Dhrystone 2.1 1.03 1.03 1.03 64.1 64.1 64.2
Fibonacci 0.86 0.86 0.86 53.7 53.7 53.7
While(1) 0.67 0.67 0.67 41.8 41.8 41.8
DS14127 Rev 5
Reduced code 2.25 2.37 2.41 70.3 74.2 75.2

®
All peripherals Coremark 2.26 2.39 2.42 70.6 74.6 75.6
Supply disabled, SecureMark 2.40 2.52 2.56 74.9 78.8 79.8
IDD Range 1,
current in SRAM1 and mA µA/MHz
(Run) fHCLK1 = fHSE32 = 32 MHz Dhrystone 2.1 2.42 2.55 2.58 75.7 79.6 80.7
Run mode SRAM2
enabled Fibonacci 2.06 2.18 2.22 64.3 68.2 69.2
While(1) 1.64 1.77 1.80 51.3 55.3 56.3
Reduced code 6.37 6.49 6.52 63.7 64.9 65.2
®
Coremark 6.41 6.53 6.56 64.1 65.3 65.6
Electrical characteristics
fHCLK1 = HSE32 + PLL at
100 MHz Dhrystone 2.1 6.92 7.04 7.07 69.2 70.4 70.7
Fibonacci 5.85 5.97 6.01 58.5 59.7 60.1
While(1) 4.45 4.58 4.61 44.5 45.8 46.1
93/149
Table 48. Current consumption in Run mode on SMPS, with different codes running
94/149
Electrical characteristics
from flash memory, Cache ON (2-way), Prefetch OFF(1)
Typ Typ
Conditions
Symbol
25 °C 25 °C
Parameter Unit Unit
- Voltage scaling Code 1.8 V 3.0 V 3.3 V 1.8 V 3.0 V 3.3 V
Reduced code 0.64 0.48 0.46 40.2 30.3 29.0

Coremark® 0.65 0.49 0.47 40.7 30.5 29.1

fHCLK1 = fHSI16 = 16 MHz Dhrystone 2.1 0.69 0.51 0.49 43.1 32.0 30.5
Fibonacci 0.56 0.45 0.43 34.7 28.0 26.8
While(1) 0.47 0.37 0.36 29.3 23.4 22.6
DS14127 Rev 5
Reduced code 1.91 1.55 1.52 59.7 48.6 47.5
All peripherals Coremark® 1.92 1.56 1.52 60.0 48.8 47.6

Supply disabled, SecureMark 2.02 1.63 1.59 63.3 50.9 49.7
IDD Range 1,
current in SRAM1 and mA µA/MHz
(Run) fHCLK1 = fHSE32 = 32 MHz Dhrystone 2.1 2.04 1.64 1.60 63.9 51.3 50.0
Run mode SRAM2
enabled Fibonacci 1.76 1.46 1.43 55.1 45.6 44.7
While(1) 1.44 1.25 1.24 45.0 39.1 38.7
Reduced code 5.15 3.71 3.52 51.5 37.1 35.2
®
Coremark 5.18 3.73 3.54 51.8 37.3 35.4
fHCLK1 = HSE32 + PLL at
100 MHz Dhrystone 2.1 5.57 3.99 3.78 55.7 39.9 37.8
Fibonacci 4.73 3.44 3.28 47.3 34.4 32.8
STM32WBA5xxx
While(1) 3.65 2.74 2.63 36.5 27.4 26.3
Table 49. Current consumption in Sleep modes, flash memory in power-down(1)(2)

Conditions Typ
Voltage
- - fHCLK 25 °C 55 °C 85 °C
scaling

fHCLK1 = fHSE32 = 32 MHz LDO 32 MHz 0.95 1.06 1.36
Supply Range 1
IDD current in fHCLK1 = HSE32 + PLL > 32 MHz 100 MHz 2.14 2.25 2.56
mA
(Sleep) Sleep fHCLK1 = fHSI16 = 16 MHz Range 2 16 MHz 0.22 0.24 0.29
mode
fHCLK1 = fHSE32 = 32 MHz SMPS 32 MHz 0.82 0.89 1.07
Range 1
2. All peripherals disabled.
Table 50. Flash memory static power consumption(1)

Typ
Symbol Parameter Conditions Unit
25 °C 55 °C 85 °C
IDD (Flash) Static consumption in normal mode PD = 1 versus PD = 0 44.6 48.5 59.0
Additional static consumption in µA
IDD (Flash_LPM) LPM = 1 versus LPM = 0 25.2 26.2 28.7
normal versus low-power mode
Table 51. Current consumption in Stop 0 mode(1)

Conditions Typ
- - VDD 25 °C 55 °C 85 °C
1.8 V 48 79 181
2.4 V 48 79 180
Supply current in Stop 0 mode,
3.0 V 49 80 182
SRAM2 + CACHE retained
3.3 V 49 82 186
3.6 V 50 82 197
IDD(Stop 0) LDO Range 2 µA
1.8 V 49 81 186
2.4 V 49 81 186
3.0 V 49 82 188
all RAMs + CACHE retained
3.3 V 50 83 190
3.6 V 51 84 203
DS14127 Rev 5 95/149

136
Table 51. Current consumption in Stop 0 mode(1) (continued)

Conditions Typ
- - VDD 25 °C 55 °C 85 °C
1.8 V 15 32 94
2.4 V 12 26 74
3.0 V 11 23 63
SRAM2 + CACHE retained
3.3 V 11 22 60
3.6 V 11 22 70
IDD(Stop 0) SMPS Range 2 µA
1.8 V 15 33 98
2.4 V 13 27 77
3.0 V 12 24 66
all RAMs + CACHE retained
3.3 V 12 23 62
3.6 V 12 23 72
QDD Electrical charge consumed LDO TBD TBD TBD

Range 2 3.0 V nAs
(wake-up from Stop 0) during wake-up from Stop 0(2) SMPS TBD TBD TBD

2. Wake-up with code execution from flash memory. Average value given for a typical wake-up time, as specified in Table 56
and Table 57.
Table 52. Current consumption in Stop 1 mode(1)

Conditions Typ
- VDD 25 °C 55 °C 85 °C
1.8 V 20.2 49.0 134.5
2.4 V 22.1 50.3 133.9
LDO 3.0 V 20.5 51.3 135.7
3.3 V 22.6 53.7 136.0
Supply current in Stop 1 mode, 3.6 V 20.9 56.0 152.5
IDD(Stop 1) µA
SRAM1 retained, ULPMEN = 1 1.8 V 10.5 26.8 85.0
2.4 V 8.2 20.9 66.1
SMPS 3.0 V 6.8 17.6 55.6
3.3 V 6.5 16.7 52.2
3.6 V 6.4 18.7 62.8
96/149 DS14127 Rev 5

Table 53. Current consumption in Standby retention mode(1)

Condition Typ
VDD 25 °C 55 °C 85 °C
1.8 V 2.25 4.85 14.8
2.4 V 2.40 5.41 15.1
LDO standby
3.0 V 2.39 5.66 15.5
retention mode
3.3 V 2.58 5.51 16.2
Supply current in Standby mode, 3.6 V 2.76 8.52 17.6
SRAM1 retained, ULPMEN = 1 1.8 V 1.07 2.85 9.83
2.4 V 0.87 2.35 8.35
SMPS standby
3.0 V 0.81 2.20 7.80
retention mode
3.3 V 0.93 2.35 7.99
3.6 V 1.23 2.88 8.83
IDD(Standby) µA
1.8 V 3.71 8.46 25.9
2.4 V 4.06 9.06 26.2
LDO standby
3.0 V 3.74 9.33 26.8
retention mode
3.3 V 4.23 10.1 27.4
Supply current in Standby mode, 3.6 V 4.89 13.1 29.0
all SRAMs + BLE retained, ULPMEN = 1 1.8 V 1.87 4.90 16.7
2.4 V 1.49 3.94 13.6
SMPS standby
3.0 V 1.31 3.50 12.1
retention mode
3.3 V 1.37 3.57 12.0
3.6 V 1.67 4.51 12.6
DS14127 Rev 5 97/149

136
Table 54. Current consumption in Standby mode(1)

Conditions Typ
- VDD 25 °C 55 °C 85 °C
1.8 V 0.16 0.58 3.02
2.4 V 0.18 0.64 3.29
ULPMEN = 1 3.0 V 0.24 0.79 3.81
3.3 V 0.37 1.06 4.50
Supply current in
Standby mode, 3.6 V 0.71 1.69 5.93
all peripherals 1.8 V 1.26 1.71 4.05
disabled
2.4 V 1.61 2.07 4.57
ULPMEN = 0 3.0 V 2.00 2.54 5.34
3.3 V 2.29 2.96 6.18
3.6 V 2.81 3.77 7.71
IDD(Standby) µA
1.8 V 1.44 1.82 3.74
2.4 V 1.81 2.22 4.25
Clocked by LSI1, ULPMEN = 0 3.0 V 2.24 2.71 4.99
3.3 V 2.55 3.14 5.78
Supply current in 3.6 V 3.07 3.91 7.18
Standby mode,
IWDG enabled 1.8 V 1.37 1.74 3.67
2.4 V 1.71 2.12 4.13
Clocked by LSI1 / 128,
3.0 V 2.10 2.58 4.85
ULPMEN = 0
3.3 V 2.40 2.98 5.61
3.6 V 2.89 3.73 7.01
98/149 DS14127 Rev 5

Table 54. Current consumption in Standby mode(1) (continued)

Conditions Typ
- VDD 25 °C 55 °C 85 °C
1.8 V 1.48 1.85 3.78
2.4 V 1.87 2.27 4.30
Clocked by LSI1, ULPMEN = 0 3.0 V 2.31 2.78 5.06
3.3 V 2.64 3.22 5.86
3.6 V 3.17 4.02 7.27
1.8 V 1.36 1.74 3.67
2.4 V 1.71 2.12 4.15
Clocked by LSI1 / 128,
3.0 V 2.11 2.58 4.85
ULPMEN = 0
3.3 V 2.40 2.98 5.61
Supply current in
IDD(Standby Standby mode, no 3.6 V 2.90 3.75 7.02
µA
with RTC) IWDG, 1.8 V 1.51 1.89 4.03
RTC enabled
2.4 V 1.91 2.32 4.55
Clocked by LSE bypass
3.0 V 2.36 2.84 5.36
32.768 kHz, ULPMEN = 0
3.3 V 2.70 3.28 6.16
3.6 V 3.24 4.06 7.61
1.8 V 1.66 1.98 3.43
Clocked by LSE crystal 2.4 V 2.03 2.37 3.90

32.768 kHz in medium 3.0 V 2.45 2.89 4.77
low-drive, ULPMEN = 0 3.3 V 2.76 3.32 5.54
3.6 V 3.29 4.06 6.84
Electrical charge
QDD
consumed during
(wake-up from - 3.0 V - TBD - nAs
wake-up from
Standby) Standby(2) mode
2. Wake-up with code execution from flash memory. Average value given for a typical wake-up time, as specified in Table 56.
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up or pull-down generate current consumption when the
pin is externally held to the opposite level. The value of this current consumption can be
simply computed by using the pull-up/pull-down resistors values given in Section 5.3.17.
For the output pins, any internal or external pull-up or pull-down and external load must also
be considered to estimate the current consumption.
An additional current consumption is due to I/Os configured as inputs when an intermediate
voltage level is applied externally. This is caused by the input Schmitt trigger circuits used to
discriminate the input value. Unless this specific configuration is required by the application,
DS14127 Rev 5 99/149

136
this supply current consumption can be avoided by configuring these I/Os in analog mode.
This is the case of ADC input pins, which must be configured as analog inputs.
Caution: Any floating input pin can settle to an intermediate voltage level or switch inadvertently, as a
result of external electromagnetic noise. To avoid current consumption related to floating
pins, they must be configured in analog mode, or forced internally to a definite digital value.
This can be done by using pull-up/down resistors, or by configuring the pins in output mode.
I/O dynamic current consumption
The I/Os used in application increase the consumption measured previously (see Table 55).
When an I/O pin switches, it uses the current from the I/O supply voltage to supply the pin
circuitry, and to charge/discharge the capacitive load (internal and external) connected to it:
I SW = V DD × f SW × C
where:
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
• VDD is the I/O supply voltage
• fSW is the I/O switching frequency
• C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
– CINT is the I/O pin capacitance
– CEXT is any connected external device pin capacitance
– CS is the PCB board capacitance
The pin is configured in push-pull output mode, and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The power consumption of the digital part of the peripherals is given in Table 55, while that
of the analog part (when applicable) is indicated in the related sections.
The MCU is put under the following conditions:
• All I/O pins are in analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• The ambient operating temperature and supply voltage conditions summarized in
Table 31
100/149 DS14127 Rev 5

Table 55. Peripheral typical dynamic current consumption(1)

Range 1 Range 2 Range 1 Range 2
Bus Peripheral Unit
LDO LDO SMPS SMPS
AHB1 bus 0.27 0.19 0.13 0.07

SRAM1 0.29 0.22 0.15 0.08
TSC 1.25 0.92 0.62 0.35
CRC 0.30 0.22 0.15 0.08
AHB1 RAMCFG 0.22 0.17 0.11 0.06 µA/MHz
GPDMA1 1.48 1.10 0.73 0.42
ICACHE 0.46 0.34 0.23 0.13
FLASH interface 1.70 1.26 0.85 0.48
GTZC1 0.48 0.36 0.24 0.14
AHB2 bus(2) 0.27 0.18 0.13 0.08
SRAM2 0.34 0.26 0.17 0.09
PKA 4.91 3.63 2.43 1.38
HSEM 0.08 0.07 0.04 0.02
SAES 65.22 48.52 32.36 18.44
RNG 0.88 0.69 0.44 0.25
AHB2 µA/MHz
HASH 1.47 1.11 0.74 0.41
AES 1.77 1.34 0.89 0.50
GPIOA 0.05 0.06 0.04 0.02
GPIOB 0.06 0.06 0.04 0.02
GPIOC 0.03 0.05 0.02 0.01
GPIOH 0.02 0.05 0.02 0.01
AHB4 bus 0.00 0.03 0.00 0.01
ADC4 kernel clock domain 1.60 1.17 0.79 0.46
AHB4 µA/MHz
ADC4 bus clock domain 2.76 2.03 1.37 0.77
PWR 0.04 0.02 0.03 0.01
(3)
AHB5 AHB5 bus + peripherals 0.07 0.05 0.03 0.02 µA/MHz
DS14127 Rev 5 101/149

136
Table 55. Peripheral typical dynamic current consumption(1) (continued)

Range 1 Range 2 Range 1 Range 2
Bus Peripheral Unit
LDO LDO SMPS SMPS
AHB to APB1(4) 0.00 0.00 0.00 0.00

TIM2 3.00 2.22 1.49 0.85
TIM3 2.65 1.96 1.31 0.74
WWDG 0.21 0.16 0.11 0.06
USART2 kernel clock domain 2.81 2.07 1.38 0.77
APB1 µA/MHz
USART2 bus clock domain 1.35 1.00 0.66 0.38
I2C1 kernel clock domain 1.79 1.34 0.90 0.51
I2C1 bus clock domain 2.52 1.85 1.24 0.70
LPTIM2 kernel clock domain 2.87 2.13 1.42 0.81
LPTIM2 bus clock domain 3.83 2.82 1.89 1.07
AHB to APB2(4) 0.62 0.46 0.31 0.18
TIM1 4.67 3.45 2.33 1.31
SPI1 kernel clock domain 0.91 0.68 0.45 0.25
SPI1 bus clock domain 2.45 1.82 1.20 0.69
TIM17 1.65 1.22 0.81 0.47
APB2 µA/MHz
TIM16 1.63 1.22 0.81 0.46
USART1 kernel clock domain 3.21 2.39 1.60 0.91
USART1 bus clock domain 4.66 3.45 2.31 1.31
SAI1 kernel clock domain 0.95 0.70 0.47 0.27
SAI1 bus clock domain 1.37 1.03 0.67 0.39
(4)
AHB to APB7 0.27 0.22 0.13 0.09
SYSCFG 0.32 0.24 0.16 0.09
SPI3 kernel clock domain 1.01 0.74 0.50 0.28
SPI3 bus clock domain 2.32 1.71 1.16 0.65
LPUART1 kernel clock domain 2.79 2.05 1.37 0.78
LPUART1 bus clock domain 3.97 2.94 1.98 1.12
APB7 µA/MHz
I2C3 kernel clock domain 1.78 1.32 0.88 0.50
I2C3 bus clock domain 2.52 1.86 1.25 0.71
LPTIM1 kernel clock domain 4.40 3.26 2.19 1.25
LPTIM1 bus clock domain 5.33 3.96 2.65 1.51
COMP 0.19 0.14 0.09 0.05
RTC/TAMP 1.81 1.34 0.90 0.51
2. The AHB bus is automatically active when at least one peripheral is ON on the AHB or associated APB.
3. RADIO inactive.
102/149 DS14127 Rev 5

4. The AHB to APB bridge is automatically active when at least one peripheral is ON on the APB.
5.3.9 Wake-up time from low-power modes and voltage scaling

transition times
The times given in Table 56 are the latency between the event and the execution of the first
user instruction (FSTEN = 1 in PWR_CR3 if not mentioned differently).
The device goes in Low-power mode after the WFE (Wait For Event) instruction.
Table 56. Low-power mode wake-up timings - LDO(1)

Symbol Parameter Conditions Typ Max Unit
SLEEP_PD = 0 14 17 CPU clock cycles

tWU(Sleep) Wake-up time from Sleep to Run mode
SLEEP_PD = 1
TBD TBD µs
with HSE32 = 32 MHz
Wake-up time from Stop 0 to Run mode FLASHFWU = 1 TBD TBD

in flash memory, SRAMs retained FLASHFWU = 0 8.17 TBD
tWU(Stop 0) µs
Wake-up time from Stop 0 to Run mode
FLASHFWU = 0 TBD TBD
in SRAM2
Wake-up time from Stop 1 to Run mode FLASHFWU = 1 19.1 TBD

in flash memory, SRAMs retained FLASHFWU = 0 TBD TBD
tWU(Stop 1) µs
in SRAM2
tWU(Standby Wake-up time from Standby retention to FSTEN = 1 45.5 TBD

µs
with Retention) Run mode in flash memory FSTEN = 0 TBD TBD
Wake-up time from Standby to Run mode FSTEN = 1 TBD TBD

tWU(Standby) µs
in flash memory FSTEN = 0 TBD TBD
Table 57. Low-power mode wake-up timings - SMPS(1)

SLEEP_PD = 0 14 17 CPU clock cycles

tWU(Sleep) Wake-up time from Sleep to Run mode
SLEEP_PD = 1 TBD TBD µs

in flash memory, RAMs retained FLASHFWU = 0 TBD TBD
tWU(Stop 0) µs
in SRAM2

in flash memory, SRAMs retained FLASHFWU = 0 TBD TBD
tWU(Stop 1) µs
in SRAM2
DS14127 Rev 5 103/149

136
Table 57. Low-power mode wake-up timings - SMPS(1) (continued)

tWU(Standby Wake-up time from Standby retention to FSTEN = 1 TBD TBD

µs
with retention) Run mode in flash memory FSTEN = 0 TBD TBD
Wake-up time from Standby to Run FSTEN = 1 TBD TBD

tWU(Standby) µs
mode in flash memory FSTEN = 0 TBD TBD
Table 58. Regulator modes transition times(1)

Range 2 to range 1 - 43.4 TBD

tVOST(2) µs
Range 1 to range 2(3) - TBD TBD
2. Time for ACTVOSRDY in PWR_SVMSR to indicate selected new VOS range.
3. VOSRDY remains at 1 on a transition from range 1 to range 2.
Table 59. Wake-up time using USART/LPUART(1)

Symbol Parameter Typ Max Unit
Wake-up time needed to calculate the maximum USART/LPUART

,tWUUSART
baudrate needed to wake up from Stop mode when USART/LPUART - tsu(HSI16) max µs
tWULPUART
kernel clock source is HSI16
5.3.10 External clock source characteristics

High-speed external clock
The high-speed external (HSE32) clock can be supplied with a 32 MHz crystal or a clock
source.
The devices include internal programmable capacitances that can be used to trim the crystal
frequency, to compensate the PCB parasitic one.
Table 60. HSE32 crystal requirements(1)

fHSE Oscillator frequency(2) - - 32 - MHz

Includes initial accuracy,
stability over temperature,
Bluetooth
fTOL Frequency tolerance(3) aging, and frequency -50 - 50 ppm
Low Energy
pulling due to incorrect
load capacitance
CL Load capacitance - 8 - 18
pF
CO Shunt capacitance - - - 4
104/149 DS14127 Rev 5

Table 60. HSE32 crystal requirements(1) (continued)

ESR Equivalent series resistance - 60 - 150 Ω

Cbank Capacitor bank range - 6.6 - 23.6 pF
Cbank-step Capacitor bank step size - 215 270 325 fF
tSTAB Oscillator stabilization time - - 100 160 µs
IDDRF(HSE32) Current consumption - - TBD - µA
2. 32 MHz XTAL is specified for two specific references: NX2016SA and NX1612SA.
3. After capacitor bank trimming.
Table 61. HSE32 clock source requirements(1)

fHSE32 External clock source frequency(2) - - 32 - MHz

Includes initial Bluetooth Low
-50 - 50
accuracy, stability Energy
fTOL Frequency tolerance ppm
over temperature,
and aging IEEE802.15.4 -40 - 40
Input level 0 - 0.9 V

VHSE32 Clock input voltage limits
Amplitude(3) 200 - 900 mVPP
DuCyHSE32 Duty cycle - TBD - TBD %
Offset = 10 kHz - - -127
φn(HSE32) Phase noise for 32 MHz Offset = 100 kHz - - -135 dBc/Hz
Offset = 1 MHz - - -138
2. fHSE = 1 / tHSE.
3. AC coupling is supported (capacitor 470 pF to 100 nF).
Note: For information about oscillator trimming, refer to AN5042 “Precise HSE frequency and
startup time tuning for STM32 wireless MCUs”, available on www.st.com.
Low-speed external clock

The low-speed external (LSE) clock can be supplied with a crystal or a clock source. The
information provided in this section is based on design simulation results, obtained with the
typical external components specified in Table 62. In the application, the crystal and the load
capacitors must be placed as close as possible to the oscillator pins, to minimize output
distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more
details on the resonator characteristics (frequency, package, accuracy).
DS14127 Rev 5 105/149

136
Table 62. LSE oscillator characteristics(1)

32.000
fLSE Oscillator frequency(2) - - or - kHz
32.768
Includes initial accuracy, stability
over temperature, aging and Bluetooth
fTOL Frequency tolerance -500 - 500 ppm
frequency pulling due to incorrect Low Energy
load capacitance
LSEDRV = medium-low drive capability - 450 -
LSE current
IDD(LSE) LSEDRV = medium-high drive capability - 590 - nA
consumption
LSEDRV = high drive capability - 700 -
LSEDRV = medium-low drive capability - - 0.75
Maximum critical
Gmcritmax LSEDRV = medium-high drive capability - - 1.70 µA/V
crystal Gm
LSEDRV = high drive capability - - 2.70
Internal stray parasitic
CS_PARA - - 3 - pF
capacitance(3)
tSU(LSE) Startup time(4) VDD is stabilized - 2 - s
2. For information on selecting the crystal, refer to AN2867 ‘Oscillator design guide for STM8AF/AL/S, STM32 MCUs and
MPUs”.
3. CS_PARA is the equivalent capacitance seen by the crystal due to OSC32_IN and OSC32_OUT internal parasitic
capacitances.
4. Time measured from when the LSE is enabled by software, until a stable LSE oscillation is reached. This value is
measured for a standard crystal, and can vary significantly with the crystal used.
Figure 18. LSE typical application with a crystal
Resonator with integrated

capacitors
CL1
OSC32_IN fLSE
32.768 kHz Drive

resonator programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note: No external resistors are required between OSC32_IN and OSC32_OUT, and it is forbidden
to add one.
106/149 DS14127 Rev 5

Table 63. LSE clock source requirements(1)

External clock source

fLSE - 32.000 32.768 - kHz
frequency(2)
Includes initial accuracy, Bluetooth

-500 - 500
fTOL Frequency tolerance stability over Low Energy ppm
temperature, and aging Thread CSL -255 - 255
VLSE_ext Clock input voltage range - 0 - VDD V
Clock input peak-to-peak
VLSE_ext_PP - 0.3 - VDD V
amplitude(3)
DuCyLSE Duty cycle - 40 - 60 %
2. fLSE = 1/tLSE.
3. AC coupled is supported (capacitor TBD).
The clock input waveforms are shown in Figure 19 and Figure 20.
Figure 19. LSE external square clock source AC timing diagram

VLSE_ext
tLSE = 1/fLSE
VLSE_ext_PP
DT56259V1
t
DuCyLSE DuCyLSE
Figure 20. LSE external sinusoidal clock source AC timing diagram
VLSE_ext
tLSE = 1/fLSE
VLSE_ext_PP
DT56258V1
In bypass mode the LSE oscillator is switched off, and the input pin OSC32_IN is a standard
GPIO.
DS14127 Rev 5 107/149

136
Table 64. LSE external clock bypass mode characteristics(1)

External clock source

fLSE_ext - 32.000 32.768 - kHz
frequency(2)
Includes initial
Bluetooth
fTOL Frequency tolerance accuracy and stability -500 - 500 ppm
Low Energy
over temperature
OSC32_IN input low level
VIL - - - 0.3 x VDD V
voltage
OSC32_IN input high level
VIH - 0.7 x VDD - - V
voltage
tw(LSEH) OSC32_IN input high or
- 10 - - µs
tw(LSEL) low time for square signal
2. fLSE = 1/tLSE.
5.3.11 Internal clock source characteristics

The parameters given in the following tables are derived under ambient operating
temperature and supply voltage conditions summarized in Table 31.
High-speed internal (HSI16) RC oscillator
Table 65. HSI16 oscillator characteristics

VDD = 3.0 V, TJ = 30 °C
15.92 16 16.08
calibrated during production
1.71 V ≤ VDD ≤ 3.6 V,
fHSI16 Frequency after factory calibration 15.84 16 16.16 MHz
TJ = -10 °C to 100 °C(1)
1.71 V ≤ VDD ≤ 3.6 V,
15.65 16 16.35
TJ = -40 °C to 130 °C (1)
TRIM(2) User trimming step - 18 29 40 kHz
DuCyHSI16 (2) Duty cycle - 45 - 55 %
tsu(HSI16)(2) Startup time - - 2.5 3.6
μs
tstab(HSI16)(2) Stabilization time - - 4 6
IDD(HSI16)(2) Power consumption - - 150 210 μA
1. Evaluated by characterization, not tested in production, unless otherwise specified. It does not take into account package
and soldering effects.
108/149 DS14127 Rev 5

Low-speed internal (LSI) RC oscillator
Table 66. LSI1 oscillator characteristics

VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 1 0.245 0.25 0.255

VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 0 31.4 32.0 32.6
fLSI1 Frequency kHz
1.71 V ≤ VDD ≤ 3.6 V, TJ = -40 to 85 °C,
30.4 32.0 33.6
LSIPREDIV = 0 (1)
DuCyLSI1 Duty cycle LSIPREDIV = 1 - 50 - %
tSU(LSI1)(2) Startup time - - 230 260
μs
tSTAB(LSI1)(2) Stabilization time 5% of final frequency - 230 260
Power LSIPREDIV = 0 - 140 255

IDD(LSI1)(2) nA
consumption LSIPREDIV = 1 - 130 240
Table 67. LSI2 oscillator characteristics

fLSI2 Frequency - 24 32 48 kHz

tSU(LSI2)(1) Startup time - 550 - 750
μs
(1)
tSTAB(LSI2) Stabilization time 5% of final frequency - 650 1100
∆TEMP(2) Stability over temperature - -200 - 200 ppm/ °C
IDD(LSI2)(2) Power consumption - - 1 2 μA
5.3.12 PLL characteristics

The parameters given in Table 68 are derived from tests performed at ambient temperature
and under the supply voltage conditions summarized in Table 31.
Table 68. PLL characteristics

fPLL_IN(1) PLL input clock - 4 - 16 MHz

DuCyPLL_IN(1) PLL input clock duty cycle - 10 - 90 %
fPLL_OUT(1) PLL output clock P, Q, and R - 1 - 100 MHz
DuCyPLL_OUT(1) PLL output clock duty cycle Division 1 40 - 60 %
fVCO_OUT(1) PLL VCO output - 128 - 544 MHz
Integer mode - 25 54
tLOCK(2) PLL lock time(3) μs
Fractional mode - 40 65
DS14127 Rev 5 109/149

136
Table 68. PLL characteristics (continued)

Integer mode, VCO = 544 MHz - ±20 -

RMS cycle-to-cycle jitter
Fractional mode, VCO = 544 MHz - ±70 -
Integer mode, VCO = 544 MHz - ±35 -
Jitter(1) RMS period jitter ps
Fractional mode, VCO = 544 MHz - ±45 -
Long-term jitter(4) Integer mode, VCO = 544 MHz - ±160 -

fPLL_IN = 8 MHz Fractional mode, VCO = 544 MHz - ±170 -
VCO freq = 100 MHz - TBD -
PLL power consumption VCO freq = 200 MHz - 170 -

μA
on VDD VCO freq = 336 MHz - 230 -
VCO freq = 544 MHz - 340 -
IDD(PLL)(1)
VCO freq = 100 MHz 1 clock output - TBD -
VCO freq = 100 MHz 3 clock output - TBD -
PLL power consumption
VCO freq = 200 MHz 1 clock output 290 μA
on VDD.
VCO freq = 336 MHz 1 clock output 480
VCO freq = 544 MHz 1 clock output - 760 -
3. Lock time is the duration until PLL1RDY flag (2% of final frequency).
4. Measured on 5000 cycles.
5.3.13 Flash memory characteristics
Table 69. Flash memory characteristics

Symbol Parameter Conditions Typ Max(1) Unit
Normal mode 118 118

tprog(2) 128-bit programming time µs
Burst mode 48 48
fAHB = 100 MHz, normal mode TBD -
tprog_page(2) One 8-Kbyte page programming time
fAHB = 100 MHz, burst mode TBD -
fAHB = 100 MHz, normal mode TBD -
tprog_flash(2) 1-Mbyte programming time
fAHB = 100 MHz, burst mode TBD - ms
10 k endurance cycles 1.5 2.4
tERASE(2) One 8-Kbyte page erase time
100 k endurance cycles(3) 1.7 3.4
tME (2) Mass erase time 10 k endurance cycles 195 308
110/149 DS14127 Rev 5

Table 69. Flash memory characteristics (continued)

Symbol Parameter Conditions Typ Max(1) Unit
Write mode 2.1 -

Average consumption from VDD
Erase mode 1.3 -
IDD(4) mA
Write mode 2.6 -
Maximum current (peak) from VDD
Erase mode 3.0 -
1. Evaluated by characterization after cycling, not tested in production.
2. Specified by design, not tested in production, unless otherwise specified.
3. Erase time applies to all pages in user area in flash main memory (only 32 pages can be cycled more than 10 k times)
Table 70. Flash memory endurance and data retention(1)

Symbol Parameter Conditions Min Unit
Whole user flash 10

NEND Endurance TA = –40 to +85 °C kcycles
Limited to 32 pages in user area 100
TA = 85 °C after 1 kcycles 30
Whole user flash TA = 55 °C after 10 kcycles 30
tRET Data retention(2) TA = 85 °C after 10 kcycles 15 Years
Limited to 32 pages in user area
2. Cycling performed over the whole temperature range.
5.3.14 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling two LEDs through I/O ports),
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs as follows:
• ESD (electrostatic discharge), positive and negative: applied to all device pins until a
functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB (fast transient voltage burst), positive and negative: applied to VDD and VSS pins
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 71. They are based on the EMS levels and classes
defined in AN1709 “EMC design guide for STM8, STM32 and legacy MCUs”.
DS14127 Rev 5 111/149

136
Table 71. EMS characteristics(1)

Symbol Parameter Conditions Level/Class
Voltage limits to apply on any I/O pin to VDD = 3.3 V, TA = +25 °C, fHCLK1 = 100 MHz,
VFESD 3B
induce a functional disturbance UFQFPN48 conforming to IEC 61000-4-2
Fast transient voltage burst limits to apply
VDD = 3.3 V, TA = +25 °C, fHCLK1 = 100 MHz,
VEFTB through 100 pF on VDD and VSS pins to 5A
UFQFPN48 conforming to IEC 61000-4-4
induce a functional disturbance
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software.
Good EMC performance is highly dependent on the user application, and the software in
particular. Therefore, it is recommended that the user applies EMC software optimization
and prequalification tests in relation with the requested EMC level.
Software recommendations
The software flow must include the management of runaway conditions, such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or on the oscillator pins for
1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specified values. When an unexpected behavior is detected, the software can be hardened
to prevent the occurrence of unrecoverable errors. See AN1015 “Software techniques for
improving microcontrollers EMC performance” for more details.
Electromagnetic interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard, which specifies the test board and the pin loading.
Table 72. EMI characteristics for fHSE = 32 MHz and fHCLK = 100 MHz(1)
Symbol Parameter Conditions Monitored frequency band Value Unit
0.1 MHz to 30 MHz 23
Peak 30 MHz to 130 MHz 11

VDD = 3.6 V, TA = 25 °C, dBµV
SEMI level(2) UFQFPN48 package 130 MHz to 1 GHz 13
compliant with IEC 61967-2
1 GHz to 2 GHz 15
Level(3) EMI level 3.5 -
112/149 DS14127 Rev 5

2. Refer to AN1709, “EMI radiated test” section.

3. Refer to AN1709, “EMI level classification” section.
5.3.15 Electrical sensitivity characteristics

Based on three different tests (ESD, latch-up) using specific measurement methods, the
device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 73. ESD absolute maximum ratings(1)

Symbol Ratings Conditions Package Class Max Unit
Electrostatic discharge voltage TA = 25 °C, conforming to

VESD(HBM) All 2 2000
(human body model) ANSI/ESDA/JEDEC JS-001
UFQFPN32 V
Electrostatic discharge voltage TA = 25 °C, conforming to
VESD(CDM) UFQFPN48 C2A 500
(charge device model) ANSI/ESDA/JEDEC JS-002
UFBGA59
Static latch-up
The following complementary static tests are required on three parts to assess the latch-up
performance:
• a supply overvoltage is applied to each power supply pin
• a current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 74. Electrical sensitivity(1)

Symbol Parameter Conditions Class
LU Static latch-up class TJ = 130 °C conforming to JESD78E 2

5.3.16 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller if
abnormal injection accidentally happens, some susceptibility tests are performed on a
sample basis during device characterization.
DS14127 Rev 5 113/149

136
Functional susceptibility to I/O current injection

While a simple application is executed, the device is stressed by injecting current into the
I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at
a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter, such as an ADC error above a certain
limit (higher than 5 LSB ET), out of conventional limits of induced leakage current on
adjacent pins (out of the -5 µA / 0 µA range) or other functional failure (for example reset
occurrence or oscillator frequency deviation).
The characterization results are given in Table 75. The negative/positive induced leakage
current is caused by the negative/positive injection.
Table 75. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative injection Positive injection
IINJ Injected current on all pins 5 N/A mA

5.3.17 I/O port characteristics

General input/output characteristics
The parameters given in Table 76 are derived from tests performed at ambient temperature
and under the supply voltage conditions summarized in Table 31. All I/Os are designed as
CMOS- and TTL-compliant.
Note: For information on I/O configuration, refer to AN4899 “STM32 GPIO configuration for
hardware settings and low-power consumption”.
Table 76. I/O static characteristics

I/O input
VIL - - 0.3 x VDD
low level voltage
1.58 V ≤ VDD ≤ 3.6 V V
I/O input
VIH 0.7 x VDD - -
high level voltage
Vhys(1) Input hysteresis - - 250 - mV
VIN ≤ Max(VDD, VDDA) - - 150
(1) I/O input leakage
Ilkg Max(VDD, VDDA) < VIN ≤ Max(VDD, VDDA) + 1 V - - 2000 nA
current(2)(3)
Max(VDD, VDDA) + 1 V < VIN ≤ 5.5 V - - 500
Weak pull-up
RPU - 30 40 50
equivalent resistor(4)
kΩ
Weak pull-down
RPD - 30 40 50
equivalent resistor(4)
CIO I/O pin capacitance - - 5 - pF
114/149 DS14127 Rev 5

2. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] x Ilkg max.
3. To sustain a voltage higher than Min (VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be disabled.
4. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10%).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 21.
Figure 21. I/O input characteristics (all I/Os except PH3)
MSv69136V1
Output driving current

The I/Os can sink or source up to ±8 mA, up to ±20 mA with a relaxed VOL / VOH.
In the user application, the number of I/O pins that can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2.
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 28).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 28).
Output voltage levels

Unless otherwise specified, the parameters given in Table 77 are at ambient temperature
and under the supply voltage conditions summarized in Table 31. All I/Os are CMOS- and
TTL-compliant.
DS14127 Rev 5 115/149

136
Table 77. Output voltage characteristics(1)

VOL Output low level voltage - 0.4

|IIO| = 8 mA, 2.7 V ≤ VDD ≤ 3.6 V
VOH Output high level voltage VDD - 0.4 -
VOL(2) Output low level voltage - 1.3
|IIO| = 20 mA, 2.7 V ≤ VDD ≤ 3.6 V
VOH(2) Output high level voltage VDD - 1.3 -
V
(2)
VOL Output low level voltage - 0.4
|IIO| = 4 mA, 1.58 V ≤ VDD ≤ 3.6 V
VOH(2) Output high level voltage VDD - 0.4 -
Output low level voltage for an I/O pin |IIO| = 20 mA, 2.7 V ≤ VDD ≤ 3.6 V - 0.4
VOLFM+(2)
in Fm+ mode |IIO| = 10 mA, 1.58 V ≤ VDD ≤ 3.6 V - 0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 27, and
the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute
maximum ratings ΣI(PIN).
Output AC characteristics
The definition and values of output AC characteristics are given, respectively, in Figure 22
and in Table 78.
Table 78. Output AC characteristics(1)(2)

Speed(3) Symbol Parameter Conditions Min Max Unit
CL = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12.5

CL = 50 pF, 1.58 V ≤ VDD < 2.7 V - 5
Fmax Maximum frequency MHz
CL = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDD < 2.7 V - 5
00
CL = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 17
Output rise and fall CL = 50 pF, 1.58 V ≤ VDD < 2.7 V - 33

tr/tf ns
time CL = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDD < 2.7 V - 25
CL = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 55
CL = 30 pF, 1.58 V ≤ VDD < 2.7 V - 12.5
CL = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 55
CL = 10 pF, 1.58 V ≤ VDD < 2.7 V - 12.5
01
CL = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.8
Output rise and fall CL = 30 pF, 1.58 V ≤ VDD < 2.7 V - 10

tr/tf ns
time CL = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.2
CL = 10 pF, 1.58 V ≤ VDD < 2.7 V - 7.5
116/149 DS14127 Rev 5

Table 78. Output AC characteristics(1)(2) (continued)

Speed(3) Symbol Parameter Conditions Min Max Unit
CL = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100

CL = 30 pF, 1.58 V ≤ VDD < 2.7 V - 33
CL = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100
CL = 10 pF, 1.58 V ≤ VDD < 2.7 V - 40
10(4)
CL = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.3
Output rise and fall CL = 30 pF, 1.58 V ≤ VDD < 2.7 V - 6.0
tr/tf ns
time CL = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.0
CL = 10 pF, 1.58 V ≤ VDD < 2.7 V - 4.1
Fmax Maximum frequency CL = 550 pF, 1.58 V ≤ VDD ≤ 3.6 V - 1 MHz
Fm+ CL = 550 pF, 1.58 V ≤ VDD ≤ 3.6 V - 100
tf Output fall time(5) ns
CL = 100 pF, 1.58 V ≤ VDD < 3.6 V - 50
2. PB15 and PH3 output and input frequency must not exceed 16 kHz, PC14 and PC15 output and input
frequency must not exceed 250 kHz, for these IOs OSPEED must be kept at low speed.
3. The I/O speed is configured using the OSPEED bits, Fm+ is configured in SYSCFG. Refer to the product
reference manual for the description.
4. I/O compensation system enabled.
5. The fall time is defined between 70% and 30% of the output waveform according to the I2C specification.
Figure 22. Output AC characteristics definition

90% 10%
50% 50%
10% 90%
t r(IO)out t f(IO)out
Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.
MS32132V4
5.3.18 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU.
DS14127 Rev 5 117/149

136
Table 79. NRST pin characteristics(1)

VIL(NRST) Input low level voltage - - - 0.3 x VDD

V
VIH(NRST) Input high level voltage - 0.7 x VDD - -
Vhys(NRST) Schmitt trigger voltage hysteresis - - 200 - mV
RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ
tF(NRST) Input filtered pulse - - - 50
1.71 V ≤ VDD ≤ 3.6 V 330 - - ns
tNF(NRST) Input not-filtered pulse
1.58 V ≤ VDD < 1.71 V 1000 - -
2. The pull-up is designed with a true resistance in series with a switchable PMOS, whose contribution to the series resistance
is minimal (~10%).
Figure 23. Recommended NRST pin protection
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF(3)
MS19878V3
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) maximum level specified
in Table 79, or the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.19 Extended interrupt and event controller input (EXTI) characteristics

Pulses on the extended interrupt and event controller inputs must have a minimal length, to
guarantee they are detected.
Table 80. EXTI input characteristics(1)
t(EXTI) Pulse length to event controller - 20 - - ns

118/149 DS14127 Rev 5

5.3.20 Wake-up pin (WKUP) characteristics

Pulses on the wake-up pin inputs must have a minimal length, to ensure their detection.
Table 81. WKUP input characteristics(1)
t(WKUP) Pulse length to wake up - TBD - - ns

5.3.21 Analog switch booster
Table 82. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit
VDD Supply voltage 1.6 1.8 3.6 V

tSU(BOOST) Booster startup time - - 50 µs
IDD(BOOST) Booster consumption - - 125 µA
5.3.22 12-bit Analog-to-Digital converter (ADC4) characteristics

Unless otherwise specified, the parameters given in the following tables are derived at
ambient temperature, and under the fHCLK frequency and supply voltage conditions
summarized in Table 31.
Note: It is recommended to perform a calibration after each power-up.
Table 83. 12-bit ADC4 characteristics (1) (2)

VDDA Analog supply voltage - 1.62 - 3.6 V

fADC ADC clock frequency - 0.14 - 55 MHz
DuCyADC ADC clock duty cycle - 45 - 55 %
Resolution 12 bits 0.01 - 2.75
fs Sampling rate Msps
tTRIG External trigger period Resolution 12 bits 16 - - 1/fADC
Conversion voltage
VAIN(3) - 0 - VDDA V
range
Resolution 12 bits, Tj = 130 °C - - 2.2
External input Resolution 10 bits, Tj = 130 °C - - 6.8

RAIN(4) kΩ
impedance Resolution 8 bits, Tj = 130 °C - - 33.0
Resolution 6 bits, Tj = 130 °C - - 47.0
DS14127 Rev 5 119/149

136
Table 83. 12-bit ADC4 characteristics (1) (2) (continued)

Internal sample and

CADC - - 5 - pF
hold capacitor
ADC voltage regulator
tADCVREG_STUP - - - 25 µs
startup time
tSTAB ADC power-up time - (3 x 1/fADC) + 1 conversion cycle
tOFF_CAL Offset calibration time - 82
WAIT = 0, AUTOFF = 0,
4
DPD = 0, fADC = HCLK
Trigger conversion WAIT = 0, AUTOFF = 1,
tLATR 4
latency DPD = 0, fADC = HCLK/2
WAIT = 0, AUTOFF = 1,
3.75
DPD = 1, fADC = HCLK/4
ts Sampling time - 1.5 - 814.5 1/fADC
Resolution = N bits,
ts + N + 0.5
VREFPROTEN = 0
Total conversion time ts + N + ts + N +
VREFPROTEN = 1, -
tCONV (including sampling 0.5 1.5
VREFSECSMP = 0
time)
ts + N + ts + N +
VREFPROTEN = 1, -
0.5 2.5
VREFSECSMP = 1
fs = 2.5 Msps - 378 -
fs = 1 Msps - 190 -
fs = 10 ksps - 10 -
ADC consumption
IDDA(ADC) µA
on VDDA AUTOFF = 1, DPD = 0,
- 9 -
no conversion
AUTOFF = 1, DPD = 1,
- 0.11 -
no conversion
2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches).
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. The tolerance is two LSBs.
Table 84. Maximum RAIN for 12-bit ADC4(1) (2) (3)

Resolution RAIN (Ω) Sampling time (ns) Sampling cycles at 35 MHz Sampling cycles at 55 MHz
47 276
68 288
12 bits 12.5 19.5
100 306
150 336
120/149 DS14127 Rev 5

Table 84. Maximum RAIN for 12-bit ADC4(1) (2) (3) (continued)
220 377
330 442 19.5
39.5
470 526
680 650
1000 840 39.5
79.5
1500 1134
12 bits 2200 1643 79.5

(continued) 3300 2395
4700 3342
6800 4754 814.5
10000 6840 814.5
15000 9967
22000 14068
33000 19933 N/A
47 86
68 90 3.5
100 95
7.5
150 108
220 116
330 136 7.5
470 161
12.5
680 212
1000 276 12.5 19.5
10 bits 1500 376 39.5
19.5
2200 516
3300 735 79.5
39.5
4700 1012
6800 1423 79.5 814.5
10000 2040
15000 2978
22000 4356 814.5 814.5
33000 6443
47000 8925
DS14127 Rev 5 121/149

136
47 45
68 46
100 48 3.5
150 53 3.5
220 59
330 69
470 81
7.5
680 101
1000 130 7.5
8 bits 1500 177 12.5
2200 242
12.5 19.5
3300 345
4700 475 19.5
39.5
6800 670
39.5
10000 963
79.5
15000 1417
79.5
22000 2040
33000 2995 814.5
814.5
47000 4158
47 32
68 32
100 33
1.5
150 35
3.5
220 37
330 41
470 49
6 bits 680 61 3.5
1000 79
7.5
1500 106
2200 146 7.5
12.5
3300 207
4700 286 12.5 19.5
6800 404 19.5
39.5
10000 584 39.5
122/149 DS14127 Rev 5

22000 1250 79.5

6 bits 79.5
33000 1853
(continued) 814.5
47000 2607 814.5
2. BOOSTEN and ANASWVDD configured according to VDD and VDDA levels.
3. Values without external capacitance.
Table 85. 12-bit ADC4 accuracy(1)(2)(3)

ET Total unadjusted error - ±3 ±7.5

EO Offset error - ±2 ±5.5
EG Gain error - ±2 ±6.5 LSB
ED Differential linearity error - -0.9/+1.0 -0.9/+1.5
EL Integral linearity error - - ±2 ±3.5
ENOB Effective number of bits 9.9 10.9 - bits
SINAD Signal-to-noise and distortion ratio 61.4 67.4 -
SNR Signal-to-noise ratio 61.6 67.5 - dB
THD Total harmonic distortion - -74 -70
2. ADC DC accuracy values are measured after internal calibration.
3. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (resolution = 12 bits, no
oversampling).
Figure 24. ADC accuracy characteristics
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
DS14127 Rev 5 123/149

136
Figure 25. Typical connection diagram when using the ADC

with FT/TT pins featuring analog switch function
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing
VSS VSS VSSA
MSv67871V3
1. Refer to Table 83 for the values of RAIN and CADC.

2. Cparasitic represents the PCB capacitance (dependent on soldering and PCB layout quality) plus the pad
capacitance (refer to Table 76 for the value of the pad capacitance). A high Cparasitic value downgrades the
conversion accuracy. As a remedy, reduce fADC.
3. Refer to Table 76 for the values of Ilkg.
4. Refer to Figure 13, Figure 14, and Figure 15.
5.3.23 Temperature sensor characteristics
Table 86. Temperature sensor characteristics

TL(1)(2) VSENSE linearity with temperature - - 1.3 °C

(3)
Avg_Slope Average slope 2 2.5 3.0 mV/ °C
VSENSE30 (4) VSENSE voltage at VDDA = 3.0 V (±10 mV) and 30 °C (±1 °C) 700 742 800 mV
(Vcontinous0 -
Voltage difference between continuous and sampling modes(5) -10 - +4 mV
Vsampling)(2)
tSTART(TS_BUF)(2) Sensor buffer startup time - 1 10 µs
tS_temp(2) ADC sampling time when reading the temperature 13 - - µs
IDD(TS)(2) Consumption from VDD, when selected by ADC - 14 20 µA

1. VSENSE linearity depends upon calibration points. When using TS_CALx calibration points, linearity within the calibration
limits is degraded by ±5 °C. Linearity outside the calibration limits is degraded more, due to the extrapolation.
4. The VSENSE30 ADC4 conversion result is stored in the TS_CAL1 field.
5. The temperature sensor is in continuous mode when the regulator is in range 1, in sampling mode when the regulator is in
range 2 or the device is in Stop 1 mode.
124/149 DS14127 Rev 5

5.3.24 VCORE monitoring characteristics
Table 87. VCORE monitoring characteristics(1)

TS_VCORE ADC sampling time when reading the VCORE voltage 1 - - µs

5.3.25 Comparator characteristics
Table 88. COMP characteristics(1)(2)

VDDA Analog supply voltage - 1.58 - 3.6

V
VIN Input voltage range - 0 - VDDA
High-speed mode - - 8
Startup time to reach Intermediate mode - - 12
tSTART(3) propagation delay µs
specification Medium mode - - 16
Ultra-low-power mode - - 60
High-speed mode - 50 100
Propagation delay for Intermediate mode - 240 490 ns
tD(3) 200 mV step with 100 mV
overdrive Medium mode - 400 740
Ultra-low-power mode - 4 7.5 µs
(3)
Voffset Offset error Full common mode range - ±8 ±20 mV
No hysteresis - 0 -
Low hysteresis - 13 -
Vhys(3) Hysteresis mV
Medium hysteresis - 26 -
High hysteresis - 39 -
Ibias(3) Input bias current - (4)
nA
Static - 43 72
High-speed
mode With 50 kHz ±100 mV
- 44 73
overdrive square signal
Static - 8.5 14
Intermediate
- 9 15
IDDA(COMP)(3) Consumption from VDDA µA
Static - 4.0 7.0
Medium
- 4.5 7.5
Static - 0.38 1.05
Ultra-low
power mode With 50 kHz ±100 mV
- 1.5 2.5
DS14127 Rev 5 125/149

136
1. Specified by design, not tested in production, unless otherwise specified.

2. Input capacitance is negligible when compared to the I/O capacitance.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 76: I/O static characteristics.
5.3.26 Timer characteristics

The parameters given in the following tables are specified by design. Refer to
Section 5.3.17 for details on the input/output alternate function characteristics (output
compare, input capture, external clock, PWM output).
Table 89. TIMx(1) characteristics(2)

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 100 MHz 10 - ns
Timer external clock frequency - 0 fTIMxCLK/2

fEXT MHz
on CH1 to CH4 fTIMxCLK = 100 MHz 0 50
TIM1, TIM3, TIM16, TIM17 - 16
ResTIM Timer resolution bit
TIM2 - 32
- 1 216 tTIMxCLK
tCOUNTER16 16-bit counter period
fTIMxCLK = 100 MHz 0.01 655.36 µs
- 1 232 tTIMxCLK
tCOUNTER32 32-bit counter period
fTIM2CLK = 100 MHz 0,01 42.94 s
1. TIMx, is used as a general term, where x stands for 1, 2, 3, 16, or 17.
Table 90. IWDG min/max timeout period at 32 kHz(1)(2)

Prescaler divider PR[3:0] bits Min timeout RL[11:0] = 0x002 Max timeout RL[11:0] = 0xFFF Unit
/4 0 0.325 512
/8 1 0.750 1024
/16 2 1.500 2048
/32 3 3.0 4096
/64 4 6.0 8192 ms
/128 5 12.0 16384
/256 6 24.0 32768
/512 7 48.0 65536
/1024 Others 96.0 131072
1. The exact timings depend upon the phasing of the APB interface clock vs. the IWDG kernel clock, hence there is always a
full kernel clock period of uncertainty.
126/149 DS14127 Rev 5

Table 91. WWDG min/max timeout value at 100 MHz (PCLK)

Prescaler divider WDGTB[2:0] Min timeout value Max timeout value Unit
/1 0 0.040 1.621
/2 1 0.081 5.242
/4 2 0.163 10.485
/8 3 0.327 20.971
ms
/16 4 0.655 41.943
/32 5 1.310 83.886
/64 6 2.621 167.772
/128 7 5.242 335.544
5.3.27 I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): bit rate up to 100 kbit/s
• Fast-mode (Fm): bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.
The I2C timings are valid when the I2C peripheral is properly configured (see the reference
manual).
The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL
I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. I2C SDA and SCL use I/O FT
structure with _f option supporting Fm+ low-level output-current maximum requirement.
Refer to Section 5.3.17 for I2C I/O characteristics.
All I2C SDA and SCL I/Os embed an analog filter, refer to Table 92 for its characteristics.
Table 92. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
tAF Maximum pulse width of spikes suppressed by the analog filter 50(2) 190(3) ns
2. Spikes with widths below tAF min are filtered.
3. Spikes with widths above tAF max are not filtered.
DS14127 Rev 5 127/149

136
5.3.28 USART characteristics

Unless otherwise specified, the parameters given in Table 93 are derived under the ambient
temperature, fPCLKx frequency and supply voltage conditions summarized in Table 31, with
the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30pF
• Measurement points are done at 0.5 x VDD
• I/O compensation cell activated
• Voltage scaling range 1
Refer to Section 5.3.17 for more details on the I/O input/output characteristics (NSS, CK,
TX, RX for USART).
Table 93. USART characteristics(1)

Master mode, 1.71 V ≤ VDD ≤ 3.6 V - - 12.5
fCK USART clock Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V - - 33

MHz
1/tCK frequency Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V - - 32
Slave transmitter, 1.71 V ≤ VDD < 2.7 V - - 22.5
tsu(NSS) NSS setup time Slave mode(2) Tker + 2 - -
th(NSS) NSS hold time Slave mode 4 - -
tw(CKH) SCK high and
Master mode tCK / 2 - 1 tCK / 2 tCK / 2 + 1
tw(CKL) low time
Data input setup Master mode 19 - -

tsu(RX)
time Slave mode 1.5 - -
Data input hold Master mode 1 - - ns

th(RX)
time Slave mode 2 - -
Slave mode, 2.7 V ≤ VDD ≤ 3.6 V - 12 15.5
Data output
tv(TX) Slave mode, 1.71 V ≤ VDD < 2.7 V - 12 22
valid time
Master mode - 1 TBD
Data output Slave mode 9 - -

th(TX)
hold time Master mode 0 - -
2. Tker is the usart_ker_ck_pres clock period.
128/149 DS14127 Rev 5

Figure 26. USART timing diagram in master mode
1/fCK
CK output
CPHA = 0
CPOL = 0
CPHA = 0
CK output CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(CKH)
tsu(RX) tw(CKL)
RX
INPUT MSB IN BIT6 IN LSB IN
th(RX)
TX
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX)
MSv65386V4
Figure 27. USART timing diagram in slave mode
NSS
input
1/fCK th(NSS)
tsu(NSS) tw(CKH)
CPHA = 0
CK input
CPOL = 0
CPHA = 0
CPOL = 1
tw(CKL) tv(TX) th(TX)
TX output First bit OUT Next bits OUT Last bit OUT
th(RX)
tsu(RX)
RX input First bit IN Next bits IN Last bit IN

MSv65387V4
5.3.29 SPI characteristics

Unless otherwise specified, the parameters given in Table 94 are under the ambient
temperature, fPCLKx frequency and supply voltage conditions summarized in Table 31, with
the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
Refer to Section 5.3.17 for more details on the I/O input/output characteristics (NSS, SCK,
MOSI, MISO for SPI).
DS14127 Rev 5 129/149

136
Table 94. SPI characteristics(1)

Master receiver mode

50
2.7 ≤ VDD ≤ 3.6 V
Master receiver mode
33
1.71 ≤ VDD < 2.7 V
Master transmitter mode
50
2.7 ≤ VDD < 3.6 V
Master transmitter mode
33
fSCK 1.71 ≤ VDD < 2.7 V
Clock frequency - - MHz
1/tSCK Slave receiver mode
100
1.71 ≤ VDD ≤ 3.6 V
Slave transmitter mode
35.5(2)
2.7 ≤ VDD ≤ 3.6 V, voltage range 1
24(2)
1.71 ≤ VDD < 2.7 V, voltage range 1
16
tsu(NSS) NSS setup time Slave mode 4*Tpclk - -
th(NSS) NSS hold time Slave mode 2*Tpclk - -
ns
tw(SCKH)
SCK high and low time Master mode(3) tSCK/2 - 1 tSCK/2 tSCK/2 + 1
tw(SCKL)
tsu(MI) Master mode 4.5 - -
Data input setup time
tsu(SI) Slave mode 2.5 - -
th(MI) Master mode 2.0 - -
Data input hold time ns
th(SI) Slave mode 1.0 - -
ta(SO) Data output access time 9 10.5 21.0
Slave mode
tdis(SO) Data output disable time 10.5 13.0 21.0
Slave mode (after enable edge)
- 10.5 14.0
- 16.5 20.5
tv(SO)
Data output valid time Slave mode (after enable edge)
- 14.0 18.5
ns
- 21.0 25.5
tv(MO) Master mode - 0.5 2.0
th(SO) Slave mode 7.5 - -
Data output hold time
th(MO) Master mode 0 - -
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which must fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when SPI communicates with a master having
tsu(MI) = 0 while Duty(SCK) = 50%.
130/149 DS14127 Rev 5

3. tSCK = tspi_ker_ck x baudrate prescaler
Figure 28. SPI timing diagram - Slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
Figure 29. SPI timing diagram - Slave mode and CPHA = 1

NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
DS14127 Rev 5 131/149

136
Figure 30. SPI timing diagram - Master mode

High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI)
tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT BIT1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136d
5.3.30 SAI characteristics

Unless otherwise specified, the parameters given in Table 95 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 31, with the following configuration:
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 3.14 and to Section 4.1 for more details on the input/output alternate
function characteristics (SCK, SD, WS).
Table 95. SAI characteristics(1)(2)

fMCK Main clock output - - 50

Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 25
Master transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 17
Master receiver, 1.71 V ≤ VDD ≤ 3.6 V - 17
Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V
- 26
Voltage range 1 MHz
fCK Clock frequency
Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V
- 18.5
Voltage range 1
Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V
- 14
Voltage range 2
Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V
- 50
Voltage range 2
132/149 DS14127 Rev 5

Table 95. SAI characteristics(1)(2) (continued)

Master mode, 2.7 V ≤ VDD ≤ 3.6 V - 19

tv(FS) FS valid time
Master mode, 1.71 V ≤ VDD ≤ 3.6 V - 29
tsu(FS) FS setup time Slave mode 1.5 -
Master mode 10 -
th(FS) FS hold time
Slave mode 1.5 -
tsu(SD_A_MR) Master receiver 5.0 -
Data input setup time
tsu(SD_B_SR) Slave receiver 3.5 -
th(SD_A_MR) Master receiver 1.5 -
Data input hold time
th(SD_B_SR) Slave receiver 0.5 -
Slave transmitter (after enable edge),
- 19
2.7 V ≤ VDD ≤ 3.6 V, voltage range 1
- 27 ns
tv(SD_B_ST) Data output valid time
- 27
- 35
Slave transmitter (after enable edge)
10.5 -
Voltage range 1
th(SD_B_ST) Data output hold time
Slave transmitter (after enable edge)
16 -
Voltage range 2
Master transmitter (after enable edge)
- 20
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
- 29
1.71 V ≤ VDD ≤ 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 8.5 -
1. Evaluated by characterization - Not tested in production.
2. APB clock frequency must be at least two times the SAI clock frequency.
DS14127 Rev 5 133/149

136
Figure 31. SAI master timing waveforms

1/fSCK
SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)
th(FS)
SAI_FS_X
(output)
tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
(transmit) Slot n Slot n+2
tsu(SD_MR) th(SD_MR)
SAI_SD_X
(receive) Slot n
MS32771V2
Figure 32. SAI slave timing waveforms

1/fSCK
SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input)
tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X Slot n Slot n+2

(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X
Slot n
(receive)
MS32772V2
5.3.31 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in the tables below are with the following
configuration:
• Capacitive load C = 30 pF
• I/O compensation cell disabled
134/149 DS14127 Rev 5

Table 96. JTAG characteristics(1)

fTCK 2.7 ≤ VDD ≤ 3.6 V - - 30

TCK clock frequency MHz
1/tc(TCK) 1.71 ≤ VDD < 2.7 V - - 20.5
tisu(TMS) TMS input setup time - 1.5 - -
tih(TMS) TMS input hold time - 3 - -
tisu(TDI) TDI input setup time - 9 - -
tih(TDI) TDI input hold time - 0 - - ns
2.7 ≤ VDD ≤ 3.6 V - 13 16.5
tov(TDO) TDO output valid time
1.71 ≤ VDD < 2.7 V - 13 24
toh(TDO) TDO output hold time - 10 - -
Table 97. SWD characteristics(1)

fSWCLK 2.7 ≤ VDD ≤ 3.6 V - - 62.5

SWCLK clock frequency MHz
1/tc(SWCLK) 1.71 ≤ VDD < 2.7 V - - 34
tisu(SWDIO) SWDIO input setup time - 1 - -
tih(SWDIO) SWDIO input hold time - 2.5 - -
2.7 ≤ VDD ≤ 3.6 V - 12 16 ns
tov(SWDIO) SWDIO output valid time
1.71 ≤ VDD < 2.7 V - 12 29
toh(SWDIO) SWDIO output hold time - 8.5 - -
Figure 33. JTAG timing diagram

tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
MSv40458V1
DS14127 Rev 5 135/149

136
Figure 34. SWD timing diagram

tc(SWCLK)
SWCLK
tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
136/149 DS14127 Rev 5

STM32WBA5xxx Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1 Device marking

Refer to “Reference device marking schematics for STM32 microcontrollers and
microprocessors” (TN1433), available on www.st.com, for the location of pin 1 / ball A1 as
well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.
6.2 UFQFPN32 package information (A0B8)

This UFQFPN is a 32-pin, 5 x 5 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 35. UFQFPN32 - Outline
ddd C
e A1
C
A3
SEATINGPLANE
D1
b
E2 b
E1 E
1
L
32
D2 L
PIN 1 Identifier
A0B8_ME_V3
1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is mandatory to connect and
DS14127 Rev 5 137/149

144
Package information STM32WBA5xxx
solder this back-side pad to PCB ground.
Table 98. UFQFPN32 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 - 0.300 0.0071 - 0.0118
D(2) 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 - 3.700 0.1339 - 0.1457
D2 3.400 - 3.600 0.1339 - 0.1417
(2)
E 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 - 3.700 0.1339 - 0.1457
E2 3.400 - 3.700 0.1339 - 0.1457
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimensions D and E do not include mold protrusion, not to exceed 0,15 mm.
Figure 36. UFQFPN32 - Recommended footprint
5.30
3.80
0.60
32 25
1 24
3.45
5.30 3.80
3.45
0.50
0.30 8 17
9 16 0.75
3.80
A0B8_FP_V2
1. Dimensions are expressed in millimeters.
138/149 DS14127 Rev 5

6.3 UFQFPN48 package information (A0B9)

UFQFPN48 is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 37. UFQFPN48 - Outline

Pin 1 identifier
laser marking area
D
A
E E
T Seating
plane
ddd A1
e b
Detail Y
D
Y
Exposed pad
area D2
1
L
48
C 0.500x45°
pin1 corner R 0.125 typ.
E2 Detail Z
48
Z
A0B9_ME_V3

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is mandatory to connect and
solder this back-side pad to PCB ground.
DS14127 Rev 5 139/149

144
Table 99. UFQFPN48 - Mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
Figure 38. UFQFPN48 - Recommended footprint
7.30
6.20
48 37
1 36
0.20 5.60
7.30
5.80
6.20
5.60
0.30
12 25
13 24
0.50 0.75
0.55
5.80
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
140/149 DS14127 Rev 5

6.4 UFBGA59 package information (B0FS)

This UFBGA is a 59-ball, 5 x 5 mm, 0.5 mm pitch, fine pitch, square ball grid array package.
Figure 39. UFBGA59 - Outline
ddd C
PIN A1 CORNER
A1
A
TOP VIEW A4 A2
SIDE VIEW
F
1 2 3 4 5 6 7 8
H
G
F
e E
D D1 D
C
B
A
b (nX)
e eee C A B
A
fff C
E1
B E
BOTTOM VIEW
B0FS_UFBGA59_ME_V1

2. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
A distinguishing feature is available on the bottom surface of the package to identify the terminal A1 corner.
Exact shape of each corner is optional.
3. The typical ball diameter before mounting is 0.20 mm.
DS14127 Rev 5 141/149

144
Table 100. UFBGA59 - Mechanical data

Symbol
A(2) - - 0.60 - - 0.024

A1 - - 0.11 - - 0.004
A2 - 0.13 - - 0.005 -
A4 - 0.32 - - 0.012 -
(3)
b 0.24 0.29 0.34 0.009 0.011 0.013
D 4.85 5.00 5.15 0.191 0.197 0.203
D1 - 3.50 - - 0.138 -
E 4.85 5.00 5.15 0.191 0.197 0.203
E1 - 3.50 - - 0.138 -
e - 0.50 - - 0.020 -
F - 0.75 - - 0.029 -
ddd - - 0.08 - - 0.003
(4)
eee - - 0.15 - - 0.006
(5)
fff - - 0.05 - - 0.002
2. Ultra thin profile: 0.50 ≤ 0.65 mm / Fine pitch: e < 1.00 mm pitch.
- The total profile height (Dim A) is measured from the seating plane to the top of the component.
- The maximum total package height is calculated by the following methodology:
A Max = A1 Typ + A2 Typ + A4 Typ + √(A1² + A2² + A4² tolerance values)
3. The typical ball diameter before mounting is 0.20 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datum A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
142/149 DS14127 Rev 5

Figure 40. UFBGA59 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 101. UFBGA59 - Recommended PCB design rules

Dimension Recommended values
Pitch 0.5 mm
Dpad 0,300 mm
Dsm 0.400 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.300 mm
Stencil thickness 0.100 mm
6.5 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the specified values.
TJ max (in Celsius degrees), can be calculated using the equation:
TJ max = TA max + (PD max x ΘJA)
where:
• TA max is the maximum ambient temperature in °C
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max)
• PINT max is the product of IDD and VDD, expressed in Watt (this is the maximum chip
internal power)
PI/O max represents the maximum power dissipation on output pins:
• PI/O max = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH)
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
DS14127 Rev 5 143/149

144
Table 102. Package thermal characteristics

Symbol Parameter Package Value Unit
UFQFPN32 - 5 mm x 5 mm 36.6
ΘJA Thermal resistance junction-ambient UFQFPN48 - 7 mm x 7 mm 28.4
UFBGA59 - 5 mm x 5 mm TBD
ΘJB Thermal resistance junction-board UFQFPN48 - 7 mm x 7 mm 12.8 °C / W
ΘJC Thermal resistance junction-case UFQFPN48 - 7 mm x 7 mm 10.0
144/149 DS14127 Rev 5

STM32WBA5xxx Ordering information
7 Ordering information
Example: STM32 WB A52 C G U 6 TR
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
WB = Wireless Bluetooth®
Device subfamily
A52 = Reduced set of features
A54 = Full set of features, LDO
A55 = Full set of features, SMPS
Pin count
K = 32 pins
C = 48 pins
U = 59 pins
Flash memory size
G = 1 Mbyte
E = 512 Kbytes
Package
U = UFQFPN
I = UFBGA
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
7 = Industrial temperature range, -40 to 105 °C (120 °C junction)
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (memory, package, and so on), or for further information on
any aspect of this device, contact your nearest ST sales office.
DS14127 Rev 5 145/149

145
Important security notice STM32WBA5xxx
8 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
146/149 DS14127 Rev 5

STM32WBA5xxx Revision history
9 Revision history
,
Table 103. Document revision history

Date Revision Changes
13-Dec-2022 1 Initial release.

19-Dec-2022 2 Changed document classification, from ST restricted to Public.
Document scope restricted to STM32WBA52Cx devices, hence:
– updated image on cover page
– updated Table 1: Device summary, Table 2: STM32WBA52xx device
features and peripheral counts, Table 24: Device pin definitions,
Table 31: General operating conditions, Table 44: Embedded internal
voltage reference, Table 73: ESD absolute maximum ratings, and
Table 103: Package thermal characteristics
– removed former Figure 6: UFQFPN32 pinout(1) (2)
27-Feb-2023 3 – removed former Section 6.1: UFQFPN32 package information
– updated Section 7: Ordering information.
Updated Section 5.1.2: Typical values and note in Section 5.3.10:
External clock source characteristics.
Updated Table 30: Main performance at VDD = 3.3 V, Table 36: RF
receiver Bluetooth Low Energy characteristics and Table 72: EMI
characteristics for fHSE = 32 MHz and fHCLK = 100 MHz.
Removed former footnote 4 of Table 85: 12-bit ADC4 accuracy.
Minor text edits across the whole document.
Reintroduced STM32WBA52Kx devices, hence:
– updated image on cover page
– updated Table 1: Device summary, Table 2: STM32WBA52xx device
features and peripheral counts, Table 24: Device pin definitions, and
Table 103: Package thermal characteristics
– added Figure 7: UFQFPN32 pinout(1) (2)
– added Section 6.2: UFQFPN32 package information (A0B8)
16-Jun-2023 4 – updated Section 7: Ordering information.
Updated Section 1: Introduction, Section 2: Description, Section 3.12.1:
Power supply schemes, Section 3.29: Tamper and backup registers
(TAMP), Device marking for UFQFPN32, and Device marking for
UFQFPN48.
Updated Table 11: Functionalities depending on the working mode.
Updated Figure 13: Power supply scheme with LDO.
DS14127 Rev 5 147/149

148
Revision history STM32WBA5xxx
Table 103. Document revision history (continued)

Date Revision Changes
Document scope extended to STM32WBA54xx and STM32WBA55xx

devices, hence updated image on cover page, Table 1: Device
summary, and Section 7: Ordering information.
Updated document title, Features, Section 2: Description, Section 3.10:
2.4 GHz RADIO, Section 3.11: PTA interface, Section 3.12: Power
supply management, Section 3.12.1: Power supply schemes, PWR
background autonomous mode (BAM), Section 3.13: Reset and clock
controller (RCC), and Section 5.1.6: Power supply scheme.
Added Section 3.11: PTA interface, Section 3.21: Comparators
(COMP), Section 3.33: Serial audio interfaces (SAI), Section 5.3.4: RF
IEEE802.15.4 characteristics, Section 5.3.30: SAI characteristics,
Section 6.1: Device marking, and Section 6.4: UFBGA59 package
information (B0FS).
Removed former High-speed external clock security, Low-speed
external clock security, Device marking for UFQFPN32, and Device
marking for UFQFPN48.
Updated Figure 1: Block diagram, Figure 2: 2.4 GHz RADIO block
diagram, Figure 6: Clock tree, and Figure 16: Current consumption
26-Feb-2024 5
measurement scheme.
Added Figure 3: Power supply overview with SMPS, Figure 9:
UFQFPN48 SMPS pinout(1) (2), Figure 10: UFBGA59 SMPS ballout(1),
Figure 14: Power supply scheme with SMPS, and Figure 15: Power
supply scheme with SMPS (high RF power).
Updated Table 10: Operating modes overview, Table 11: Functionalities
depending on the working mode, Table 24: Device pin definitions,
Table 27: Voltage characteristics, tables 30 to 32, tables 34 to 39, tables
in Section 5.1.7: Current consumption measurement, tables 61 to 63,
Table 67: LSI2 oscillator characteristics, Table 73: ESD absolute
maximum ratings, Table 88: COMP characteristics, Table 93: USART
characteristics, Table 94: SPI characteristics, and Table 102: Package
thermal characteristics.
Added Table 3: STM32WBA54/55xx device features and peripheral
counts, Table 57: Low-power mode wake-up timings - SMPS, Table 67:
LSI2 oscillator characteristics, and Table 88: COMP characteristics.
Removed former Table 55: Current under reset condition.
148/149 DS14127 Rev 5

STM32WBA5xxx
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2024 STMicroelectronics – All rights reserved
DS14127 Rev 5 149/149

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STM32WBA5xxx

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33 with

February 2024 DS14127 Rev 5 1/149

• Security and cryptography • ECOPACK2 compliant packages

Table 1. Device summary

2/149 DS14127 Rev 5

DS14127 Rev 5 3/149

3.16 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4/149 DS14127 Rev 5

3.34.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 65

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

DS14127 Rev 5 5/149

5.3.21 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6/149 DS14127 Rev 5

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DS14127 Rev 5 7/149

8/149 DS14127 Rev 5

Table 97. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

DS14127 Rev 5 9/149

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10/149 DS14127 Rev 5

DS14127 Rev 5 11/149

12/149 DS14127 Rev 5

Table 2. STM32WBA52xx device features and peripheral counts

Flash memory density 1024 KB 512 KB

DS14127 Rev 5 13/149

Table 2. STM32WBA52xx device features and peripheral counts (continued)

Public key accelerator (PKA) Yes

Table 3. STM32WBA54/55xx device features and peripheral counts

14/149 DS14127 Rev 5

Table 3. STM32WBA54/55xx device features and peripheral counts (continued)

DS14127 Rev 5 15/149

Figure 1. Block diagram

2.4 GHz RADIO VDDRF domain

(FPU, DSP) TXRX 2.4 GHz HSE32

APB7 100 MHz

I2C3 COMP1 COMP2

AHB4 100 MHz

16/149 DS14127 Rev 5

DS14127 Rev 5 17/149

3.2 ART Accelerator (ICACHE)

3.3 Memory protection unit

18/149 DS14127 Rev 5

3.4 Multi-AHB bus matrix

3.5 Embedded flash memory

1 Yes Yes Yes No No No(4)

DS14127 Rev 5 19/149

20/149 DS14127 Rev 5

3.5.1 Flash memory protections when TrustZone is activated

3.5.2 FLASH privilege protection

DS14127 Rev 5 21/149

3.6 Embedded SRAMs

3.6.1 SRAMs TrustZone security

3.6.2 SRAMs privilege protection

3.7 Boot modes

22/149 DS14127 Rev 5