Router 1x3 project by using 32nm technology node

Mini Project – Router 1x3
Technology Node: 32nm

Contents
o Project Overview
o Physical Design Flow
o Input to Physical Design
o Synthesis
o Floor Planning
o Power Planning
o Placement
o Clock Tree Synthesis
o Routing
o Static Timing Analysis
o Report
Project Overview
The objective is to design and optimize a Router 1x3 on the 32nm technology node using Synopsys EDA
tool Fusion Compiler.
Key Focus Areas:
o Efficient floorplan with minimal congestion.
o Meet timing requirements (setup, hold, clock skew).
o Power efficiency and reliability optimization.
o Ensuring zero DRCs and Violations.

Physical Design Flow
The Physical Design flow is the back-end flow in ASIC design flow, where the RTL code is converted into GDS II
Input to Physical Design
o Netlist ( .v): A logical representation of the design, typically in formats like Verilog or VHDL, that specifies the circuit's
connectivity.
o Liberty File (.lib): Contains information about the timing, power, and functional characteristics of standard cells used in
the design.
o Design Constraints File (.sdc): Specifies timing, area, and power constraints for the design.
o Floorplan and Pin Constraints: Defines the chip's physical dimensions, block placement, and locations of input/output
pins.
o Technology File (.tf): Includes details about the manufacturing process, such as metal layer stack-up, design rules, and
parasitic models.
o Design Exchange Format (.def): Describes the design layout, including floorplan, cell placement, and routing
information.
o Power Intent File (.upf): Specifies the power domains and power management strategies for low-power designs.
o Table Lookup Plus File (.tluplus): These files are crucial in the backend flow of VLSI physical design, specifically for
parasitic extraction and delay calculation. They provide interconnect resistance and capacitance values
Inputs to Physical Design ct……..
o set TECH_FILE "../../ref/tech/saed32nm_1p9m.tf“
o set REFLIB "../../ref/CLIBs“
o set REFERENCE_LIBRARY [join "
o $REFLIB/saed32_hvt.ndm $REFLIB/saed32_lvt.ndm
$REFLIB/saed32_rvt.ndm $REFLIB/saed32_sram_lp.ndm"
o Create_lib -technology $TECH_FILE -ref_libs

$REFERENCE_LIBRARY router.dlib
o analyze -format verilog [glob ../rtl/router_*.v]

o elaborate router_top
o set_top_module router_top
o source ../scripts/setup.tcl
o source ../mcmm/mcmm_router_top.tcl
Synthesis
Synthesis is the process of converting the technology-independent RTL into a technology-dependent
gate-level netlist, which consists of WVGtech Cells.
Input Files: Technology files, Verilog files, Reference libraries Output Files: Gate-level netlist file
Floor Planning
Floor Planning is the process where the die area and core area will be specified and also the macros, standard
cells, and the I/O ports are placed at this stage.
o initialize_floorplan -boundary {{0.000 0.000}

{110.489 125.664} } -core_offset {10}\
o -core_utilization 0.7
o shape_block
o create_voltage_area_shapes –region{ {0.0000

0.0000} {91.8080 118.7120}} \
o –voltage_areas fifo_mod\
o -guard_band {0 0 1 1}
o set_block_pin_constraints -self -
allowed_layers {M3 M4 M5 M6}
o place_pins -self
Power Planning
The UPF file defines power-related details such as supply ports, power domains, and level shifters, where we
intend the power details.
o create_supply_net
o create_supply_set
o create_power_domain
o create_supply_port
o connect_supply_net
o set_level_shifter
o add_power_state
o load_upf ../router/router.upf
Power Planning Ct………..
Power Planning Ct…..
By using Power Domain Network (PDN) we will distribute equal power to all the cells in the design.
o connect_pg_net
o create_pg_ring_pattern
o create_pg_mesh_pattern
o create_pg_std_cell_conn_pattern
o set_pg_strategy
o compile_pg
o source ./pns.tcl
Power Planning Reports
Reports of Power and Ground Planning
o Check_pg_drc
o Check_pg_connecitivity
o Check_pg_missing_vias
Codes
router.tcl
Pns.tcl
Placement
In Fusion Compiler the Placement of cells will be done by using the command “Compile_Fusion”. Which will
do seven steps. Another command is “Place_opt”.
o Initial_map
o Logic_opto
o Initial_place
o Initial_drc
o Initial_opto
o Final_place
o Final_opto
Placement
Initial_Place Final_opto
Clock Tree Synthesis
Clock Tree Synthesis is a process where we provide the clock to all the sink nodes of the cells with minimum
skew or zero skew. While doing cts we will provide the ndr rules.
o set CTS_CELLS [get_lib_cells "*/NBUFF*LVT *
/NBUFF*RVT \*/INVX*_LVT
*/INVX*RVT \*/CGL* */LSUP* */DFF* "]
o set_dont_touch $CTS_CELLS false

o set_lib_cell_purpose -exclude cts [get_lib_cells]
o set_lib_cell_purpose -include cts $CTS_CELLS
o set_app_options -name
clock_opt.flow.enable_ccd -value false
o Clock_opt –from build_clock –to final_opt
o Source ./ndr.tcl
Clock Tree Synthesis cntd.
Pre CTS Stage Post CTS Stage
Routing
Routing is the process where the interconnections between all the cells will be made physically at this stage. By
using “Route_auto”.
o Route_auto
o Route_opt
o Route_eco
Routing Ct……
After competing the checks of routing, we generate the GDS – II file.
Reports
Check_lvs Check_legality
Static Timing Analysis
Static Timing Analysis is a method used to evaluate all the paths in a design to confirm whether they meet the
required timing constraints.
Input Files
o.sdc
o .spef
o Routed netlist
o Libraries
Output Files
o Timing Reports
o Eco Files
Reports
Report_ timing Report_design

Reports
Check_lvs Check_legality
Reports
Report_congestion
THANK YOU
all for your Time
by
Srinivasulu gari Murali Mohan

Router 1x3 project by using 32nm technology node

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Mini Project – Router 1x3

Technology Node: 32nm

Key Focus Areas:

o Efficient floorplan with minimal congestion.

o Meet timing requirements (setup, hold, clock skew).

o Power efficiency and reliability optimization.

o Ensuring zero DRCs and Violations.

o Create_lib -technology $TECH_FILE -ref_libs

o analyze -format verilog [glob ../rtl/router_*.v]

o initialize_floorplan -boundary {{0.000 0.000}

o create_voltage_area_shapes –region{ {0.0000

o set_dont_touch $CTS_CELLS false

o Clock_opt –from build_clock –to final_opt

Report_ timing Report_design

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