EDC Lab Mannual (1)
EDC Lab Mannual (1)
EDC Lab Mannual (1)
Manual
Page 1
LIST OF EXPERIMENTS
Page 2
Ex.No.1a
CHARACTERISTICS OF PN JUNCTION DIODE
AIM:
To study the PN junction diode characteristics under Forward & Reverse
bias conditions.
1 R.P.S 1 Diode
2 Resistor
2 Ammeter Bread
3
Board
4 Wires
3 Voltmeter
THEORY:
A PN junction diode is a two terminal junction device. It conducts
only in one direction (only on forward biasing).
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier
potential. As the applied potential exceeds the barrier potential the
charge carriers gain sufficient energy to cross the potential barrier and
hence enter the other region. The holes, which are majority carriers in
the P-region, become minority carriers on entering the N-regions, and
electrons, which are the majority carriers in the N-region, become
minority carriers on entering the P-region. This injection of Minority
carriers results in the current flow, opposite to the direction of electron
movement.
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REVERSE BIAS:
On reverse biasing, the majority charge carriers are attracted
towards the terminals due to the applied potential resulting in the
widening of the depletion region. Since the charge carriers are pushed
towards the terminals no current flows in the device due to majority
charge carriers. There will be some current in the device due to the
thermally generated minority carriers. The generation of such carriers
is independent of the applied potential and hence the current is
constant for all increasing reverse potential. This current is referred to
as Reverse Saturation Current (IO) and it increases with temperature.
When the applied reverse voltage is increased beyond the certain limit,
it results in breakdown. During breakdown, the diode current increases
tremendously.
PROCEDURE:
FORWARD BIAS:
1. Connect the circuit as per the diagram.
2. Vary the applied voltage V in steps of 0.1V.
3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I
OBSERVATIONS
1. Find the d.c (static) resistance = V/I.
V V1
2. Find the a.c (dynamic) resistance r = V / I (r = V/I) = 2 .
I 2 I1
3. Find the forward voltage drop = [Hint: it is equal to 0.7 for Si
and 0.3 for Ge]
REVERSE BIAS:
1. Connect the circuit as per the diagram.
2. Vary the applied voltage V in steps of 1.0V.
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3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I
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5. Find the dynamic resistance r = V / I.
Io = I/[exp(V/VT)]-1
CIRCUIT DIAGRAM:
FORWARD BIAS:
(0-100)mA, MC
470 + -
+ +
(0-10)V (0-15)V, MC
RPS -
-
REVERSE BIAS:
(0-500)µA,MC
470 + -
+ +
(0-30)V (0-30)V, MC
RPS
- -
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Specification for 1N4001: Silicon Diode
Peak Inverse Voltage:
50V Idc = 1A.
Maximum forward voltage drop at 1 Amp is
1.1 volts Maximum reverse current @50 volts
is 5A TABULAR COLUMN:
FORWARD BIAS: REVERSE BIAS:
MODEL GRAPH
If (mA)
I2
Vb I1
V
( Volts) 1 V2 Vf
(Volts)
Ir (A)
Page
10
RESULT:
Forward and Reverse bias characteristics of the PN junction diode
and the dynamic resistance under
i) Forward bias = ---------------------
ii) Reverse bias =------------------.
iii) Reverse Saturation Current =----------.
Page
11
Page
12
Ex.No.1b
CHARACTERISTICS OF ZENER DIODE
AIM:
To determine the breakdown voltage of a given zener diode.
THEORY:
A properly doped crystal diode, which has a sharp breakdown voltage,
is known as zener diode.
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier
potential. As the applied potential increases, it exceeds the barrier
potential at one value and the charge carriers gain sufficient energy to
cross the potential barrier and enter the other region. the holes ,which
are majority carriers in p-region, become minority carriers on entering
the N-regions and electrons, which are the majority carriers in the N-
regions become minority carriers on entering the P-region. This
injection of minority carriers results current, opposite to the direction
of electron movement.
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13
REVERSE BIAS:
Page
14
When the reverse bias is applied due to majority carriers small
amount of current (ie) reverse saturation current flows across the
junction. As the reverse bias is increased to breakdown voltage,
sudden rise in current takes place due to zener effect.
ZENER EFFECT:
Normally, PN junction of Zener Diode is heavily doped. Due to
heavy doping the depletion layer will be narrow. When the reverse bias
is increased the potential across the depletion layer is more. This
exerts a force on the electrons in the outermost shell. Because of this
force the electrons are pulled away from the parent nuclei and become
free electrons. This ionization, which occurs due to electrostatic force
of attraction, is known as Zener effect. It results in large number of
free carriers, which in turn increases the reverse saturation current
PROCEDURE:
FORWARD BIAS:
1. Connect the circuit as per the circuit diagram.
2. Vary the power supply in such a way that the readings are
taken in steps of 0.1V in the voltmeter till the needle of power
supply shows 30V.
3. Note down the corresponding ammeter readings.
4. Plot the graph :V (vs) I.
5. Find the dynamic resistance r = V / I.
REVERSE BIAS:
1. Connect the circuit as per the diagram.
2. Vary the power supply in such a way that the readings are
taken in steps of 0.1V in the voltmeter till the needle of power
supply shows 30V.
3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I
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5. Find the dynamic resistance r = V / I.
6. Find the reverse voltage Vr at Iz=20 mA.
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CIRCUIT DIAGRAM:
FORWARD BIAS:
(0-10)mA
470 + -
+ +
(0-10) V 1 (0-15) V
-
-
REVERSE BIAS:
(0-500)µA, MC
1K + -
+ +
(0-30) V 1 (0-10) V, MC
-
-
Page 17
ZENER DIODE:
If ( mA)
I2
Vr
VB I1 Vf
(V)
V1 V2 (V
)
Ir (µA)
TABULAR COLUMN:
FORWARD BIAS: REVERSE BIAS:
RESULT:
Forward and Reverse bias characteristics of the zener diode was
studied and
Forward bias dynamic resistance = ---------------------
Reverse bias dynamic resistance = ----------------------
The reverse voltage at Iz =20 mA determined from the
reverse characteristics of the Zener diode is-------.
Page 18
Page 19
Ex. No. 2a
AIM:
To plot the transistor characteristics of CE configuration.
THEORY:
A BJT is a three terminal two – junction semiconductor device in
which the conduction is due to both the charge carrier. Hence it is a
bipolar device and it amplifier the sine waveform as they are
transferred from input to output. BJT is classified into two types – NPN
or PNP. A NPN transistor consists of two N types in between which a
layer of P is sandwiched. The transistor consists of three terminal
emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts
a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped
and is of hollow cross sectional area. Normally the transistor operates
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with the EB junction forward biased.
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In transistor, the current is same in both junctions, which
indicates that there is a transfer of resistance between the two
junctions. One to this fact the transistor is known as transfer resistance
of transistor.
PROCEDURE:
INPUT CHARACTERISTICS:
OUTPUT CHARACTERISTICS:
PIN DIAGRAM:
B
E C
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Page 23
(0 – 30)mA 1 K
- +
A
(0 – 250) A C
+ +
10 K
+ A - (0-30)V
B BC107 V (0-30)V -
+ +
-
(0-30)V (0-1)V V E
- -
CIRCUIT DIAGRAM:
MODEL GRAPH:
µA
mA
IC
IB
VCE = 0V
VCE = 5V
IB=60A
IB=40A IB=20A
0
VBE(V) 0
VCE(V)
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Page 25
TABULAR COLUMN:
INPUT CHARACTERISTICS:
VCE=1V VCE=2V
VBE(V) IB(µA) VBE(V) IB(µA)
OUTPUT CHARACTERISTICS:
IB=20A IB=40A
VCE(V) IC(mA) VCE(V) IC(mA)
RESULT:
The transistor characteristicsof a Common Emitter (CE)
configuration were plotted
Page 26
Ex.No.2b
THEORY:
In this configuration the base is made common to both the input
and out. The emitter is given the input and the output is taken across
the collector. The current gain of this configuration is less than unity.
The voltage gain of CB configuration is high. Due to the high voltage
gain, the power gain is also high. In CB configuration, Base is common
to both input and output. In CB configuration the input characteristics
relate IE and VEB for a constant VCB. Initially let VCB = 0 then the input
junction is equivalent to a forward biased diode and the characteristics
resembles that of a diode. Where VCB = +VI (volts) due to early effect IE
increases and so the characteristics shifts to the left. The output
characteristics relate IC and VCB for a constant IE. Initially IC increases
and then it levels for a value IC = IE. When IE is increased IC also
increases proportionality. Though increase in VCB causes an increase in
, since is a fraction, it is negligible and so IC remains a constant for
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all values of VCB once it levels off.
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PIN DIAGRAM:
B
E C
CIRCUIT DIAGRAM:
(0-1)mA (0-30)mA
10 K + - + - 1K
-
+ +
+
(0-30)V VEB (0-2)V (0-30)V (0-30)V
- - -
PROCEDURE:
INPUT CHARACTERISTICS:
It is the curve between emitter current IE and emitter-base voltage
VBE at constant collector-base voltage VCB.
1. Connect the circuit as per the circuit diagram.
2. Set VCE=5V, vary VBE in steps of 0.1V and note down the
corresponding IB. Repeat the above procedure for 10V, 15V.
3. Plot the graph VBE Vs IB for a constant VCE.
4. Find the h parameters.
OUTPUT CHARACTERISTICS:
It is the curve between collector current IC and collector-base voltage
VCB at constant emitter current IE.
1. Connect the circuit as per the circuit diagram.
2. Set IB=20A, vary VCE in steps of 1V and note down the
corresponding IC. Repeat the above procedure for 40A, 80A,
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etc.
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3. Plot the graph VCE Vs IC for a constant IB.
4. Find the h parameters
TABULAR COLUMN:
INPUT CHARACTERISTICS:
OUTPUT CHARACTERISTICS:
MODEL GRAPH:
INPUT CHARACTERISTICS:
Page 31
IC
(mA
)
VCB1
IE2
VCB2
OUTPUT CHARACTERISTICS:
IC
(mA) IE3
IC2 IE2
IC1
IE1
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Page 33
AIM:
To plot the transistor characteristics of CE configuration.
THEORY:
A BJT is a three terminal two – junction semiconductor device in
which the conduction is due to both the charge carrier. Hence it is a
bipolar device and it amplifier the sine waveform as they are
transferred from input to output. BJT is classified into two types – NPN
or PNP. A NPN transistor consists of two N types in between which a
layer of P is sandwiched. The transistor consists of three terminal
emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts
a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped
and is of hollow cross sectional area. Normally the transistor operates
with the EB junction forward biased.
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Bottom View BC107 Specification: BC107/50V/0.1A,0.3W,300MHz
E C
(0-30)mA 1 K
+- A
(0-250)µA +
1 K +
+ - +V (0-30)V
A (0-30)V
-
+ + -
(0-30)VV (0-30)V
- -
CIRCUIT DIAGRAM:
PROCEDURE:
INPUT CHARECTERISTICS:
OUTPUT CHARECTERISTICS:
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2. Set IB, Vary VCE in regular interval of steps and note down the
corresponding IC reading. Repeat the above procedure for
different values of IB.
3. Plot the graph: VCE Vs IC for a constant IB.
MODEL GRAPH:
INPUT CHARACTERISTICS: OUTPUT CHARACTERISTICS:
(A) (mA)
IB Ie
VCE=0 VCE=5V IB=60A
IB=40A
IB=20A
0 VBC(V) 0 VCE(V)
TABULAR COLUMN:
INPUT CHARACTERISTICS:
VCE=1V VCE=2V
VBC(V) IB(µA) VBC(V) IB(µA)
OUTPUT CHARACTERISTICS:
IB=20A IB=40A
VCE(V) IE(mA) VCE(V) IE(mA)
Page 38
RESULT:
The transistor characteristics of a Common Emitter (CC)
configuration were plotted.
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Ex.No.3
AIM:
To Plot the characteristics of given FET & determine rd, gm, , IDSS,VP.
1k 1
2 Ammeter (0–30)mA 1 2 Resistor
68K 1
Bread
(0–30)V 1 3 1
3 Voltmeter Board
(0-10)V 1 4 Wires
THEORY:
FET is a voltage operated device. It has got 3 terminals. They are
Source, Drain & Gate. When the gate is biased negative with respect
to the source, the pn junctions are reverse biased & depletion regions
are formed. The channel is more lightly doped than the p type gate, so
the depletion regions penetrate deeply in to the channel. The result is
that the channel is narrowed, its resistance is increased, & ID is
reduced. When the negative bias voltage is further increased, the
depletion regions meet at the center & ID is cutoff completely.
PROCEDURE:
DRAIN CHARACTERISTICS:
1. Connect the circuit as per the circuit diagram.
2. Set the gate voltage VGS = 0V.
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3. Vary VDS in steps of 1 V & note down the corresponding ID.
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4. Repeat the same procedure for VGS = -1V.
5. Plot the graph VDS Vs ID for constant VGS.
OBSERVATIONS
1. d.c (static) drain resistance, rD = VDS/ID.
2. a.c (dynamic) drain resistance, rd = VDS/ID.
3. Open source impedance, YOS = 1/ rd.
TRANSFER CHARACTERISTICS:
1. Connect the circuit as per the circuit diagram.
2. Set the drain voltage VDS = 5 V.
3. Vary the gate voltage VGS in steps of 1V & note down the corresponding ID.
4. Repeat the same procedure for VDS = 10V.
5. Plot the graph VGS Vs ID for constant VDS.
ID
Transconductance = VGS VDS
gm
SPECIFICATION:
Voltage : 30V, IDSS > 8mA.
MODEL GRAPH:
DRAIN CHARACTERISTICS:
ID (mA)
VGS = 0V
VGS = -1V
VGS = -2V
VGS = -3V
0
VDS (volts)
TRANSFER CHARACTERISTICS:
ID(mA)
VDS =Const
VGS (V)
Page 27
TABULAR COLUMN:
DRAIN CHARACTERISTICS:
TRANSFER CHARACTERISTICS:
RESULT:
Thus the Drain & Transfer characteristics of given FET is Plotted.
Rd =
gm =
=
IDSS =
Pinch off voltage VP =
Page 28
Ex.No.4
THEORY:
UJT(Double base diode) consists of a bar of lightly doped n-type
silicon with a small piece of heavily doped P type material joined to one
side. It has got three terminals. They are Emitter(E),
Base1(B1),Base2(B2).Since the silicon bar is lightly doped, it has a
high resistance & can be represented as two resistors, rB1 & rB2. When
VB1B2 = 0, a small increase in V E forward biases the emitter junction.
The resultant plot of VE & I E is simply the characteristics of forward
biased diode with resistance. Increasing VEB1 reduces the emitter
junction reverse bias. When VEB1 = VrB1 there is no forward or reverse
bias. & IE = 0. Increasing VEB1 beyond this point begins to forward bias
the emitter junction. At the peak point, a small forward emitter
current is flowing. This current is termed as peak current( IP ). Until
this point UJT is said to be operating in cutoff region. When IE increases
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beyond peak current the device enters the negative resistance region.
In which the resistance rB1 falls rapidly & VE falls to the valley
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voltage.Vv. At this point IE = Iv. A further increase of IE causes the
device to enter the saturation region.
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set VB1B2 = 0V, vary VEB1 , & note down the readings of IE & VEB1
3. Set VB1B2 = 10V , vary VEB1 , & note down the readings of IE & VEB1
4. Plot the graph : IE Versus VEB1 for constant VB1B2.
5. Find the intrinsic standoff ratio.
CIRCUIT DIAGRAM:
1KΩ B2
(0-30A)mA 1KΩ
VE V
(0-30)V (0-30)V
B2 (0-30)V
(0-30)V
PIN DIAGRAM:
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* Minimum Valley current = 4 mA
* Maximun Peak point emitter current 5 A
*Maximum emitter reverse current 12 A.
FORMULA FOR INTRINSIC STANDOFF RATIO:
= VP - VD/ VB1B2., where VD = 0.7V.
MODEL GRAPH:
Peak point
VP
IP
Negative resistance region
VEB1(V)
IV IE (mA)
TABULAR COLUMN:
VB1B2 = 0V VB1B2 = 10V
VEB1 (V) IE (mA) VEB1 (V) IE (mA)
Page 32
PROCEDURE:
1. Give the circuit connections as per the circuit diagram.
2. The dc input voltage is set to 20 V in RPS.
3. The output sweep waveform is measured using CRO.
4. The graph of output sweep waveform is plotted
RESULT:
1. Thus the characteristics of given UJT was Plotted & its intrinsic
standoff Ratio = ----.
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Page 34
Ex.No.5
CHARACTERISTICS OF PHOTO-DIODE AND
PHOTOTRANSISTOR
AIM:
THEORY:
PHOTODIODE:
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when no light is incident, the current is only the reverse saturation
current that flows
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through the reverse biased diode. This current is termed as the dark
current of the photo diode. Now when light is incident on the photo
diode then the thermally generated carriers increase resulting in an
increased reverse current which is proportional to the intensity of
incident light. A photo diode can turn on and off at a faster rate and so
it is used as a fast acting switch.
CIRCUIT DIAGRAM:
(0-30)mA
1K
(0-30)V (0-30)V
TABULAR COLUMN:
MODEL GRAPH:
R (K)
Illumination lm/m2
Page 37
Page 38
THEORY:
PHOTOTRANSISTOR:
CIRCUIT DIAGRAM:
N P N
1K
(0-30V)
S. No. VCE IC C
(in Volts) (in mA)
Page 39
MODEL GRAPH:
IC
(mA)
400 Lux
200 Lux
0 Lux
VCE(V)
PROCEDURE:
PHOTO DIODE:
PHOTOTRANSISTOR:
1. Rig up the circuit as per the circuit diagram.
2. Maintain a known distance (say 5 cm) between the DC bulb
and the phototransistor.
3. Set the voltage of the bulb (say, 2V), vary the voltage of
the diode in steps of 1V and note down the corresponding
diode current, Ir.
4. Repeat the above procedure for the various values of DC bulb.
5. Plot the graph: VD vs. Ir for a constant bulb voltage.
RESULT:
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Thus the characteristics of photo diode and phototransistor are studied.
Page 41
Ex.No.6
CHARACTERISTICS OF THERMISTOR
AIM:
To study the characteristics of Thermistor.
THEORY:
Thermistor or Thermal resistor is two – terminal semiconductor
device whose resistance is temperature sensitive. The value of such
resistors decreases with increase in temperature. Materials employed
in the manufacture of the thermistors include oxides of cobalt, nickel,
copper, iron uranium and manganese.
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temperature of the device can be changed internally or externally. An
increase in current through the device will raise its temperature
carrying a drop in its terminal resistance. Any externally
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heat source will result in an increase in its body temperature and drop
in resistance this type action (internal or external) lends itself well to
control mechanism.
SYMBOL:
MODEL GRAPH:
R
(-cm)
T (deg)
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is approximately
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3 – 60.
Thermistors are used measure temperature, flow pressure, liquid
level, voltage or power level, vacuum, composition of gases and
thermal conductivity and also in compensation network.
RESULT:
Thus the Characteristics of thermistor was studied.
Page 46
Page 47
Ex.No.7a
SINGLE PHASE HALF WAVE RECTIFIER
AIM:
To construct a Half wave rectifier using diode and to draw its
performance characteristics.
FORMULAE:
WITHOUT FILTER:
(i) Vrms = Vm / 2
(ii) Vdc = Vm /
(iii) Ripple Factor= (Vrms / Vdc)2 – 1
(iv) Efficiency = (Vdc / Vrms)2 x 100
WITH FILTER:
’2 2
(i) Vrms = (Vrms + Vdc )
(ii) Vrms’ = Vrpp / (3 x 2)
(iii) Vdc = Vm – V rpp /2
(iv) Ripple Factor= Vrms’/ Vdc
Page 48
PROCEDURE:
WITHOUT FILTER:
1. Give the connections as per the circuit diagram.
2. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
3. Take the rectifier output across the Load.
4. Plot its performance graph.
WITH FILTER:
1. Give the connections as per the circuit diagram.
2. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
3. Connect the Capacitor across the Load.
4. Take the rectifier output across the Load.
5. Plot its performance graph.
CIRCUIT DIAGRAM:
1 Transformer
230 V / 6V
1N 4007
1K
1, 230V, 100F
CRO
50Hz
AC supply
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TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms Vdc Ripple factor Efficiency
WITH FILTER:
Vrms Vrpp Vdc Ripple factor Efficiency
MODEL GRAPH:
Vin
(Volts)
t (ms)
Vo
(Volts) Without
t (ms)
Vo
(Volts) With
t (ms)
RESULT:
Thus the performance characteristics of 1 Half wave rectifier was obtained.
Page 50
Ex.No.7b
SINGLE PHASE FULL WAVE RECTIFIER
AIM:
To construct a Full wave rectifier using diode and to draw its
performance characteristics.
FORMULAE:
WITHOUT FILTER:
(i) Vrms = Vm / 2
(ii) Vdc = 2Vm /
(iii) Ripple Factor= (Vrms / Vdc)2 – 1
(iv) Efficiency = (Vdc / Vrms)2 x 100
WITH FILTER:
(i) Vrms = Vrpp /(2* 3)
(ii) Vdc = Vm – V rpp
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PROCEDURE:
WITHOUT FILTER:
1. Give the connections as per the circuit diagram.
2. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
3. Take the rectifier output across the Load.
4. Plot its performance graph.
WITH FILTER:
1. Give the connections as per the circuit diagram.
2. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
3. Connect the Capacitor across the Load.
4. Take the rectifier output across the Load.
5. Plot its performance graph.
CIRCUIT DIAGRAM:
1 Transformer 1N 4007
230 V / 6V
100F
1K
1, 230V,
CRO
50Hz
AC supply
1N 4007
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TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms Vdc Ripple factor Efficiency
WITH FILTER:
Vrms Vrpp Vdc Ripple factor Efficiency
MODEL GRAPH :
Vin
(Volts)
t (ms)
Vo
(Volts) Without Filter
t (ms)
Vo
(Volts) With Filter
t (ms)
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Ex.No.8
DIFFERENTIAL AMPLIFIER
AIM:
To construct a Differential amplifier in Common mode & Differential mode
configuration and to find common mode rejection ratio.
THEORY:
The Differential amplifier circuit is an extremely popular
connection used in IC units. The circuit has separate inputs , two
separate outputs and emitters are connected together. If the same
input is applied to both inputs, the operation is called common mode.
In double ended operation two input signals are applied , the difference
of the inputs resulting in outputs from both collectors due to the
difference of the signals applied to both the inputs. The main feature of
the differential amplifier is the very large gain when opposite signals
are applied to inputs as compared to small signal resulting from
common input. The ratio of this difference gain to the common gain is
called common mode rejection ratio.
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CIRCUIT DIAGRAM:
DIFFERENTIAL MODE:
3.9K 3.9K
Vo1Vo2
V1
12V V2
13V
3.3 K
-9V
9V
COMMON MODE:
3.9K 3.9K
Vo1 Vo2
V2
13V
3.3 K
© Copyright 2011-2015 – VidyarthiPlus.in (VP Group) Page 47
-9V
www.vidyarthiplus.in
PROCEDURE:
DIFFERENTIAL MODE:
1. Connect the circuit as per the circuit diagram.
2. Set V1 = 50mv and V2 =55mv using the signal generator.
3. Find the corresponding output voltages across V01 & V02 using CRO
4. Calculate common mode rejection ratio using the given formula.
COMMON MODE:
1. Connect the circuit as per the circuit diagram.
2. Set V1 = 50mv using the signal generator.
3. Find the output voltage across Vo using multimeter.
4. Calculte common mode rejection ratio using the given formula.
CALCULATION:
Common mode rejection ratio(CMRR) =
Ad / Ac Ad = Differential mode gain
Ac = Common mode
gain Where Ad =
Vo /Vd
Vo = Output voltage measured across
CRO Vd = V 1 – V2 , V 1 , V2 – input
voltage applied. Ac = Vo /Vc
Vc = (V 1 + V2 )/2
DIFFERENTIAL MODE: Ad=Vo/Vd =
V1
=
V2
=
Output voltage
=
Vd= V1-V2
=
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COMMON MODE: Output voltage =
Input voltage V1=V2 =
Vc=(V1+V2)/2 =
=
Exp. No: 12
PASSIVE FILTERS
Aim:
To attenuate unwanted frequency components from input signal by using resistor
and capacitor.
Apparatus required:
Name of the apparatus Range Type Quantity
S.No
1. Signal Generator 01
2. Resistor 01
3. Capacitor Ceramic 01
4. CRO 01
5. Breadboard 01
Theory:
A filter is an AC circuit that separates some frequencies from other in
within mixed – frequency signals. Audio equalizers and crossover networks are
two well-known applications of filter circuits. A Bode plot is a graph plotting
waveform amplitude or phase on one axis and frequency on the other.
A low-pass filter allows for easy passage of low-frequency signals from
source to load, and difficult passage of high-frequency signals. Capacitor low-pass
filters insert a resistor in series and a capacitor in parallel with the load as shown
in the circuit diagram. The former filter design tries to “block” the unwanted
frequency signal while the latter tries to short it out.
The cutoff frequency for a low-pass filter is that frequency at which the
output (load) voltage equals 70.7% of the input (Source) voltage. Above the cutoff
frequency, the output voltage is lower than 70.7% of the input, and vice-versa. See
the circuit diagram
1
Fcutoff = ----------
2RC
A high-pass filter allows for easy passage of high-frequency signals from source to
load, and difficult passage of low-frequency signals. Capacitor high-pass filters
insert a capacitor in series with the load as shown in the circuit diagram. The
former filter design tries to “brick” the unwanted frequency signal while the latter
tries to short it out.
The cutoff frequency for a high-pass filter is that frequency at which the
output (load) voltage equals 70.7% of the input (source) voltage. Above the cutoff
frequency, the output voltage is greater than 70.7% of the input, and vice-versa.
1
Fcutoff = ----------
2RC
A band – pass filter works to screen out frequencies that are too low or too
high, giving easy passage only to frequencies within a certain range. Stacking a
low-pass filter on the end of a high-pass filter, or vice-versa can make band-pass
filters. Refer the circuit diagrams
Placing a low-pass filter in parallel with a high-pass filter can make band-
stop filters. Commonly, both the low-pass and high-pass filter sections are of the
“T” configuration giving the name “Twin-T” to the band-stop combination. Refer
the fig.7.7, 7.8a and 7.8b.
Passes low frequencies
Low-pass filter
Signal Signal
Input Output
High-pass filter
Fig. 7.8a
The frequency of maximum attenuation is called the notch
frequency.
Procedure:
1. Give the connections as per circuit diagrams.
2. Switch on the main.
3. Change the frequency from minimum and find the output
voltage by using CRO.
4. Draw the graph.
5. Verify the cut off frequency.
6. Switch off the main.
Result:
Thus we analyze passive filter and various waveforms are noted
Exp. No :
10
STUDY OF CRO AND
POWER FACTOR MEASUREMENT USING CRO
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Aim:
To study cathode Ray Oscilloscope (CRO) and measurement of power factor using
CRO.
Apparatus required:
Name of the apparatus Range Type Quantity
S.No
1. Resistance Box 1
2. Capacitance Box 1
3. Inductance Box 1
4. Function Generator 1
5. Bread board 1
Theory:
The cathode ray oscilloscope is the most versatile measuring instrument
available. We can measure following parameters using the CRO:
1. AC or DC voltage.
2. Time (t=1/f).
3. Phase relationship
4. Waveform calculation: Rise time; fall time; on time; off-time
Distortion, etc.
We can also measure non-electrical physical quantities like pressure, strain,
temperature, acceleration, etc., by converting into electrical quantities using
a transducer.
Major blocks:
1. Cathode ray tube (CRT)
2. Vertical amplifier
3. Horizontal amplifier
4. Sweep generator
5. Trigger circuit
6. Associated power supply.
1. The cathode ray tube is the heart of CRO. The CRT is enclosed in an
evacuated glass envelope to permit the electron beam to traverse in the
tube easily. The main functional units of CRO are as follows.
Electron gun assembly
Deflection plate unit
Screen.
2. Vertical Amplifier is the main factor in determining the bandwidth and
sensitivity of an oscilloscope. Vertical sensitivity is a measure of how
much the electron beam will be deflected for a specified input signal.
On the front panel of the oscilloscope, one can see a knob attached to a
rotary switch labeled volts/division. The rotary switch is electrically
connected to the input attenuation network. The setting of the rotary
switch indicates what amplitude signal is required to deflect the beam
vertically by one division.
3. Horizontal amplifier Under normal mode of operation, the horizontal
amplifier will amplify the sweep generator input. When the CRO is
being used in the X-Y mode, the horizontal amplifier will amplify the
signal applied to the horizontal input terminal. Although the vertical
amplifier mush be able to faithfully reproduce low-amplitude and high
frequency signal with fast rise-time, the horizontal amplifier is only
required to provide a faithful reproduction of the sweep signal which
has a relatively high amplitude and slow rise time.
4. Sweep generator and Trigger circuit These two units form the Signal
Synchronization unit of the CRO.
5. Associated Power Supply: The input signal may come from an
external source when the trigger selector switch is set to EXT or from
proportional to the deflecting voltage, the CRT may be used as a linear measuring
device. The voltage being measured is applied to the vertical plates through an
iterative network, whose propagation time corresponds to the velocity of electrons,
thereby synchronizing the voltage applied to the vertical plate with the velocity of
the beam.
Synchronization of input signal: The sweep generator produces a saw tooth
waveform, which is used to synchronize the applied voltage to obtain a stationary-
applied signal. This requires that the time base be operated at a submultiples
frequency of the signal under measurement. If synchronization is not done, the
pattern is not stationary, but appears to drift across the screen in a random fashion.
Internal synchronization This trigger is obtained from the time base generator to
synchronize the signal.
External synchronization An external trigger source can also be used to
synchronize the signal being measured.
Auto Triggering Mode The time base used in this case in a self-oscillating
condition, i.e., it gives an output even in the absence of any Y-input. The
advantage of this mode is that the beam is visible on the screen under all
conditions, including the zero input. When the input exceeds a certain magnitude
then the internal free running oscillator locks on to the frequency.
Precautions:
1. The ammeter is connected using thick wires.
2. While reversing ammeter polarity, see to it that the capacitor is not
discharged.
Observation:
Sl.No Time Voltage Current
Unit (Sec) (Volts) (Amps)
LIST OF EXPERIMENTS
131351 ELECTRON DEVICES AND CIRCUITS LABORATORY LTPC
(B.E. (EEE), B.E. (E&I) and B.E. (I & C) 0032
(Revised)
Ex.No.1a
CHARACTERISTICS OF PN JUNCTION DIODE
AIM:
To study the PN junction diode characteristics under Forward & Reverse
bias conditions.
1 R.P.S 1 Diode
2 Resistor
2 Ammeter Bread
3
Board
4 Wires
3 Voltmeter
THEORY:
A PN junction diode is a two terminal junction device. It conducts
only in one direction (only on forward biasing).
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier
potential. As the applied potential exceeds the barrier potential the
charge carriers gain sufficient energy to cross the potential barrier and
hence enter the other region. The holes, which are majority carriers in
the P-region, become minority carriers on entering the N-regions, and
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electrons, which are the majority carriers in the N-region,
REVERSE BIAS:
On reverse biasing, the majority charge carriers are attracted
towards the terminals due to the applied potential resulting in the
widening of the depletion region. Since the charge carriers are pushed
towards the terminals no current flows in the device due to majority
charge carriers. There will be some current in the device due to the
thermally generated minority carriers. The generation of such carriers
is independent of the applied potential and hence the current is
constant for all increasing reverse potential. This current is referred to
as Reverse Saturation Current (IO) and it increases with temperature.
When the applied reverse voltage is increased beyond the certain limit,
it results in breakdown. During breakdown, the diode current increases
tremendously.
PROCEDURE:
FORWARD BIAS:
5. Connect the circuit as per the diagram.
6. Vary the applied voltage V in steps of 0.1V.
7. Note down the corresponding Ammeter readings I.
8. Plot a graph between V & I
OBSERVATIONS
4. Find the d.c (static) resistance = V/I.
V V1
5. Find the a.c (dynamic) resistance r = V / I (r = V/I) = 2 .
I 2 I1
6. Find the forward voltage drop = [Hint: it is equal to 0.7 for Si
and 0.3 for Ge]
REVERSE BIAS:
6. Connect the circuit as per the diagram.
7. Vary the applied voltage V in steps of 1.0V.
Io = I/[exp(V/VT)]-1
CIRCUIT DIAGRAM:
FORWARD BIAS:
(0-100)mA, MC
470 + -
+ +
(0-10)V (0-15)V, MC
RPS -
-
REVERSE BIAS:
(0-500)µA,MC
470 + -
+ +
(0-30)V (0-30)V, MC
RPS
- -
MODEL GRAPH
If (mA)
I2
Vb I1
V
( Volts) 1 V2 Vf
(Volts)
Ir (A)
RESULT:
Forward and Reverse bias characteristics of the PN junction diode
and the dynamic resistance under
i) Forward bias = ---------------------
ii) Reverse bias =------------------.
iii) Reverse Saturation Current =----------.
Ex.No.1b
CHARACTERISTICS OF ZENER DIODE
AIM:
To determine the breakdown voltage of a given zener diode.
THEORY:
A properly doped crystal diode, which has a sharp breakdown voltage,
is known as zener diode.
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier
potential. As the applied potential increases, it exceeds the barrier
potential at one value and the charge carriers gain sufficient energy to
cross the potential barrier and enter the other region. the holes ,which
are majority carriers in p-region, become minority carriers on entering
the N-regions and electrons, which are the majority carriers in the N-
regions become minority carriers on entering the P-region. This
injection of minority carriers results current, opposite to the direction
of electron movement.
ZENER EFFECT:
Normally, PN junction of Zener Diode is heavily doped. Due to
heavy doping the depletion layer will be narrow. When the reverse bias
is increased the potential across the depletion layer is more. This
exerts a force on the electrons in the outermost shell. Because of this
force the electrons are pulled away from the parent nuclei and become
free electrons. This ionization, which occurs due to electrostatic force
of attraction, is known as Zener effect. It results in large number of
free carriers, which in turn increases the reverse saturation current
PROCEDURE:
FORWARD BIAS:
1. Connect the circuit as per the circuit diagram.
2. Vary the power supply in such a way that the readings are
taken in steps of 0.1V in the voltmeter till the needle of power
supply shows 30V.
3. Note down the corresponding ammeter readings.
4. Plot the graph :V (vs) I.
5. Find the dynamic resistance r = V / I.
REVERSE BIAS:
7. Connect the circuit as per the diagram.
8. Vary the power supply in such a way that the readings are
taken in steps of 0.1V in the voltmeter till the needle of power
supply shows 30V.
9. Note down the corresponding Ammeter readings I.
10. Plot a graph between V & I
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11. Find the dynamic resistance r = V / I.
12. Find the reverse voltage Vr at Iz=20 mA.
CIRCUIT DIAGRAM:
FORWARD BIAS:
(0-10)mA
470 + -
+ +
(0-10) V 1 (0-15) V
-
-
REVERSE BIAS:
(0-500)µA, MC
1K + -
+ +
(0-30) V 1 (0-10) V, MC
-
-
ZENER DIODE:
If ( mA)
I2
Vr
VB I1 Vf
(V)
V1 V2 (V
)
Ir (µA)
TABULAR COLUMN:
FORWARD BIAS: REVERSE BIAS:
RESULT:
Forward and Reverse bias characteristics of the zener diode was
studied and
Forward bias dynamic resistance = ---------------------
Reverse bias dynamic resistance = ----------------------
The reverse voltage at Iz =20 mA determined from the
reverse characteristics of the Zener diode is-------.
Ex. No. 2a
AIM:
To plot the transistor characteristics of CE configuration.
THEORY:
A BJT is a three terminal two – junction semiconductor device in
which the conduction is due to both the charge carrier. Hence it is a
bipolar device and it amplifier the sine waveform as they are
transferred from input to output. BJT is classified into two types – NPN
or PNP. A NPN transistor consists of two N types in between which a
layer of P is sandwiched. The transistor consists of three terminal
emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts
a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped
and is of hollow cross sectional area. Normally the transistor operates
PROCEDURE:
INPUT CHARACTERISTICS:
OUTPUT CHARACTERISTICS:
PIN DIAGRAM:
B
E C
(0 – 30)mA 1 K
- +
A
(0 – 250) A C
+ +
10 K
+ A - (0-30)V
B BC107 V (0-30)V -
+ + -
(0-30)V (0-1)V V E
- -
CIRCUIT DIAGRAM:
MODEL GRAPH:
µA
mA
IC
IB
VCE = 0V
VCE = 5V
IB=60A
IB=40A IB=20A
0
VBE(V) 0
VCE(V)
TABULAR COLUMN:
INPUT CHARACTERISTICS:
VCE=1V VCE=2V
VBE(V) IB(µA) VBE(V) IB(µA)
OUTPUT CHARACTERISTICS:
IB=20A IB=40A
VCE(V) IC(mA) VCE(V) IC(mA)
RESULT:
The transistor characteristicsof a Common Emitter (CE)
configuration were plotted
Ex.No.2b
THEORY:
In this configuration the base is made common to both the input
and out. The emitter is given the input and the output is taken across
the collector. The current gain of this configuration is less than unity.
The voltage gain of CB configuration is high. Due to the high voltage
gain, the power gain is also high. In CB configuration, Base is common
to both input and output. In CB configuration the input characteristics
relate IE and VEB for a constant VCB. Initially let VCB = 0 then the input
junction is equivalent to a forward biased diode and the characteristics
resembles that of a diode. Where VCB = +VI (volts) due to early effect IE
increases and so the characteristics shifts to the left. The output
characteristics relate IC and VCB for a constant IE. Initially IC increases
and then it levels for a value IC = IE. When IE is increased IC also
increases proportionality. Though increase in VCB causes an increase in
, since is a fraction, it is negligible and so IC remains a constant for
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all values of VCB once it levels off.
PIN DIAGRAM:
B
E C
CIRCUIT DIAGRAM:
(0-1)mA (0-30)mA
10 K + - + - 1K
-
+ +
+
(0-30)V VEB (0-2)V (0-30)V (0-30)V
- - -
PROCEDURE:
INPUT CHARACTERISTICS:
It is the curve between emitter current IE and emitter-base voltage
VBE at constant collector-base voltage VCB.
5. Connect the circuit as per the circuit diagram.
6. Set VCE=5V, vary VBE in steps of 0.1V and note down the
corresponding IB. Repeat the above procedure for 10V, 15V.
7. Plot the graph VBE Vs IB for a constant VCE.
8. Find the h parameters.
OUTPUT CHARACTERISTICS:
It is the curve between collector current IC and collector-base voltage
VCB at constant emitter current IE.
5. Connect the circuit as per the circuit diagram.
6. Set IB=20A, vary VCE in steps of 1V and note down the
corresponding IC. Repeat the above procedure for 40A, 80A,
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etc.
TABULAR COLUMN:
INPUT CHARACTERISTICS:
OUTPUT CHARACTERISTICS:
MODEL GRAPH:
INPUT CHARACTERISTICS:
IC
(mA
)
VCB1
IE2
VCB2
OUTPUT CHARACTERISTICS:
IC
(mA) IE3
IC2 IE2
IC1
IE1
AIM:
To plot the transistor characteristics of CE configuration.
THEORY:
A BJT is a three terminal two – junction semiconductor device in
which the conduction is due to both the charge carrier. Hence it is a
bipolar device and it amplifier the sine waveform as they are
transferred from input to output. BJT is classified into two types – NPN
or PNP. A NPN transistor consists of two N types in between which a
layer of P is sandwiched. The transistor consists of three terminal
emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts
a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped
and is of hollow cross sectional area. Normally the transistor operates
with the EB junction forward biased.
E C
(0-30)mA 1 K
+- A
(0-250)µA +
1 K +
+ - +V (0-30)V
A (0-30)V -
-
+ +
(0-30)VV (0-30)V
- -
CIRCUIT DIAGRAM:
PROCEDURE:
INPUT CHARECTERISTICS:
OUTPUT CHARECTERISTICS:
5. Set IB, Vary VCE in regular interval of steps and note down the
corresponding IC reading. Repeat the above procedure for
different values of IB.
6. Plot the graph: VCE Vs IC for a constant IB.
MODEL GRAPH:
INPUT CHARACTERISTICS: OUTPUT CHARACTERISTICS:
(A) (mA)
IB Ie
VCE=0 VCE=5V IB=60A
IB=40A
IB=20A
0 VBC(V) 0 VCE(V)
TABULAR COLUMN:
INPUT CHARACTERISTICS:
VCE=1V VCE=2V
VBC(V) IB(µA) VBC(V) IB(µA)
OUTPUT CHARACTERISTICS:
IB=20A IB=40A
VCE(V) IE(mA) VCE(V) IE(mA)
RESULT:
The transistor characteristics of a Common Emitter (CC)
configuration were plotted.
Ex.No.3
AIM:
To Plot the characteristics of given FET & determine rd, gm, , IDSS,VP.
1k 1
2 Ammeter (0–30)mA 1 2 Resistor
68K 1
Bread
(0–30)V 1 3 1
3 Voltmeter Board
(0-10)V 1 4 Wires
THEORY:
FET is a voltage operated device. It has got 3 terminals. They are
Source, Drain & Gate. When the gate is biased negative with respect
to the source, the pn junctions are reverse biased & depletion regions
are formed. The channel is more lightly doped than the p type gate, so
the depletion regions penetrate deeply in to the channel. The result is
that the channel is narrowed, its resistance is increased, & ID is
reduced. When the negative bias voltage is further increased, the
depletion regions meet at the center & ID is cutoff completely.
PROCEDURE:
DRAIN CHARACTERISTICS:
6. Connect the circuit as per the circuit diagram.
7. Set the gate voltage VGS = 0V.
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8. Vary VDS in steps of 1 V & note down the corresponding ID.
TRANSFER CHARACTERISTICS:
6. Connect the circuit as per the circuit diagram.
7. Set the drain voltage VDS = 5 V.
8. Vary the gate voltage VGS in steps of 1V & note down the corresponding ID.
9. Repeat the same procedure for VDS = 10V.
10. Plot the graph VGS Vs ID for constant VDS.
ID
Transconductance = VGS VDS
gm
PIN DIAGRAM:
BOTTOM VIEW OF BFW10:
SPECIFICATION:
Voltage : 30V, IDSS > 8mA.
MODEL GRAPH:
DRAIN CHARACTERISTICS:
ID (mA)
VGS = 0V
VGS = -1V
VGS = -2V
VGS = -3V
0
VDS (volts)
TRANSFER CHARACTERISTICS:
ID(mA)
VDS =Const
VGS (V)
TABULAR COLUMN:
DRAIN CHARACTERISTICS:
TRANSFER CHARACTERISTICS:
RESULT:
Thus the Drain & Transfer characteristics of given FET is Plotted.
Rd =
gm =
=
IDSS =
Pinch off voltage VP =
Ex.No.4
THEORY:
UJT(Double base diode) consists of a bar of lightly doped n-type
silicon with a small piece of heavily doped P type material joined to one
side. It has got three terminals. They are Emitter(E),
Base1(B1),Base2(B2).Since the silicon bar is lightly doped, it has a
high resistance & can be represented as two resistors, rB1 & rB2. When
VB1B2 = 0, a small increase in V E forward biases the emitter junction.
The resultant plot of VE & I E is simply the characteristics of forward
biased diode with resistance. Increasing VEB1 reduces the emitter
junction reverse bias. When VEB1 = VrB1 there is no forward or reverse
bias. & IE = 0. Increasing VEB1 beyond this point begins to forward bias
the emitter junction. At the peak point, a small forward emitter
current is flowing. This current is termed as peak current( IP ). Until
this point UJT is said to be operating in cutoff region. When IE increases
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beyond peak current the device enters the negative resistance region.
In which the resistance rB1 falls rapidly & VE falls to the valley
PROCEDURE:
6. Connect the circuit as per the circuit diagram.
7. Set VB1B2 = 0V, vary VEB1 , & note down the readings of IE & VEB1
8. Set VB1B2 = 10V , vary VEB1 , & note down the readings of IE & VEB1
9. Plot the graph : IE Versus VEB1 for constant VB1B2.
10. Find the intrinsic standoff ratio.
CIRCUIT DIAGRAM:
1KΩ B2
(0-30A)mA 1KΩ
VE V
(0-30)V (0-30)V
B2 (0-30)V
(0-30)V
PIN DIAGRAM:
MODEL GRAPH:
Peak point
VP
IP
Negative resistance region
VEB1(V)
IV IE (mA)
TABULAR COLUMN:
VB1B2 = 0V VB1B2 = 10V
VEB1 (V) IE (mA) VEB1 (V) IE (mA)
PROCEDURE:
5. Give the circuit connections as per the circuit diagram.
6. The dc input voltage is set to 20 V in RPS.
7. The output sweep waveform is measured using CRO.
8. The graph of output sweep waveform is plotted
RESULT:
1. Thus the characteristics of given UJT was Plotted & its intrinsic
standoff Ratio = ----.
Ex.No.5
CHARACTERISTICS OF PHOTO-DIODE AND
PHOTOTRANSISTOR
AIM:
THEORY:
PHOTODIODE:
through the reverse biased diode. This current is termed as the dark
current of the photo diode. Now when light is incident on the photo
diode then the thermally generated carriers increase resulting in an
increased reverse current which is proportional to the intensity of
incident light. A photo diode can turn on and off at a faster rate and so
it is used as a fast acting switch.
CIRCUIT DIAGRAM:
(0-30)mA
1K
(0-30)V (0-30)V
TABULAR COLUMN:
MODEL GRAPH:
R (K)
Illumination lm/m2
THEORY:
PHOTOTRANSISTOR:
CIRCUIT DIAGRAM:
N P N
1K
(0-30V)
S. No. VCE IC C
(in Volts) (in mA)
(mA)
400 Lux
200 Lux
0 Lux
VCE(V)
PROCEDURE:
PHOTO DIODE:
PHOTOTRANSISTOR:
6. Rig up the circuit as per the circuit diagram.
7. Maintain a known distance (say 5 cm) between the DC bulb
and the phototransistor.
8. Set the voltage of the bulb (say, 2V), vary the voltage of
the diode in steps of 1V and note down the corresponding
diode current, Ir.
9. Repeat the above procedure for the various values of DC bulb.
10. Plot the graph: VD vs. Ir for a constant bulb voltage.
RESULT:
Page 95
Thus the characteristics of photo diode and phototransistor are studied.
Page 96
Ex.No.6
CHARACTERISTICS OF THERMISTOR
AIM:
To study the characteristics of Thermistor.
THEORY:
Thermistor or Thermal resistor is two – terminal semiconductor
device whose resistance is temperature sensitive. The value of such
resistors decreases with increase in temperature. Materials employed
in the manufacture of the thermistors include oxides of cobalt, nickel,
copper, iron uranium and manganese.
Page 97
temperature of the device can be changed internally or externally. An
increase in current through the device will raise its temperature
carrying a drop in its terminal resistance. Any externally
Page 98
heat source will result in an increase in its body temperature and drop
in resistance this type action (internal or external) lends itself well to
control mechanism.
SYMBOL:
MODEL GRAPH:
R
(-cm)
T (deg)
Page 99
is approximately
Page
100
3 – 60.
Thermistors are used measure temperature, flow pressure, liquid
level, voltage or power level, vacuum, composition of gases and
thermal conductivity and also in compensation network.
RESULT:
Thus the Characteristics of thermistor was studied.
Page
101
Page
102
Ex.No.7a
SINGLE PHASE HALF WAVE RECTIFIER
AIM:
To construct a Half wave rectifier using diode and to draw its
performance characteristics.
FORMULAE:
WITHOUT FILTER:
(i) Vrms = Vm / 2
(ii) Vdc = Vm /
(iii) Ripple Factor= (Vrms / Vdc)2 – 1
(iv) Efficiency = (Vdc / Vrms)2 x 100
WITH FILTER:
’2 2
(i) Vrms = (Vrms + Vdc )
(ii) Vrms’ = Vrpp / (3 x 2)
(iii) Vdc = Vm – V rpp /2
(iv) Ripple Factor= Vrms’/ Vdc
Page 103
PROCEDURE:
WITHOUT FILTER:
5. Give the connections as per the circuit diagram.
6. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
7. Take the rectifier output across the Load.
8. Plot its performance graph.
WITH FILTER:
1. Give the connections as per the circuit diagram.
6. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
7. Connect the Capacitor across the Load.
8. Take the rectifier output across the Load.
9. Plot its performance graph.
CIRCUIT DIAGRAM:
1 Transformer
230 V / 6V
1N 4007
1K
1, 230V, 100F
CRO
50Hz
AC supply
Page 104
TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms Vdc Ripple factor Efficiency
WITH FILTER:
Vrms Vrpp Vdc Ripple factor Efficiency
MODEL GRAPH:
Vin
(Volts)
t (ms)
Vo
(Volts) Without
t (ms)
Vo
(Volts) With
t (ms)
RESULT:
Thus the performance characteristics of 1 Half wave rectifier was obtained.
Page 105
Ex.No.7b
SINGLE PHASE FULL WAVE RECTIFIER
AIM:
To construct a Full wave rectifier using diode and to draw its
performance characteristics.
FORMULAE:
WITHOUT FILTER:
(i) Vrms = Vm / 2
(ii) Vdc = 2Vm /
(iii) Ripple Factor= (Vrms / Vdc)2 – 1
(iv) Efficiency = (Vdc / Vrms)2 x 100
WITH FILTER:
(i) Vrms = Vrpp /(2* 3)
(ii) Vdc = Vm – V rpp
Page 106
PROCEDURE:
WITHOUT FILTER:
5. Give the connections as per the circuit diagram.
6. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
7. Take the rectifier output across the Load.
8. Plot its performance graph.
WITH FILTER:
1. Give the connections as per the circuit diagram.
6. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
7. Connect the Capacitor across the Load.
8. Take the rectifier output across the Load.
9. Plot its performance graph.
CIRCUIT DIAGRAM:
1 Transformer 1N 4007
230 V / 6V
100F
1K
1, 230V,
CRO
50Hz
AC supply
1N 4007
Page 107
TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms Vdc Ripple factor Efficiency
WITH FILTER:
Vrms Vrpp Vdc Ripple factor Efficiency
MODEL GRAPH :
Vin
(Volts)
t (ms)
Vo
(Volts) Without Filter
t (ms)
Vo
(Volts) With Filter
t (ms)
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Ex.No.8
DIFFERENTIAL AMPLIFIER
AIM:
To construct a Differential amplifier in Common mode & Differential mode
configuration and to find common mode rejection ratio.
THEORY:
The Differential amplifier circuit is an extremely popular
connection used in IC units. The circuit has separate inputs , two
separate outputs and emitters are connected together. If the same
input is applied to both inputs, the operation is called common mode.
In double ended operation two input signals are applied , the difference
of the inputs resulting in outputs from both collectors due to the
difference of the signals applied to both the inputs. The main feature of
the differential amplifier is the very large gain when opposite signals
are applied to inputs as compared to small signal resulting from
common input. The ratio of this difference gain to the common gain is
called common mode rejection ratio.
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CIRCUIT DIAGRAM:
DIFFERENTIAL MODE:
3.9K 3.9K
Vo1Vo2
V1
12V V2
13V
3.3 K
-9V
9V
COMMON MODE:
3.9K 3.9K
Vo1 Vo2
V2
13V
3.3
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K
-9V
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PROCEDURE:
DIFFERENTIAL MODE:
5. Connect the circuit as per the circuit diagram.
6. Set V1 = 50mv and V2 =55mv using the signal generator.
7. Find the corresponding output voltages across V01 & V02 using CRO
8. Calculate common mode rejection ratio using the given formula.
COMMON MODE:
5. Connect the circuit as per the circuit diagram.
6. Set V1 = 50mv using the signal generator.
7. Find the output voltage across Vo using multimeter.
8. Calculte common mode rejection ratio using the given formula.
CALCULATION:
Common mode rejection ratio(CMRR) =
Ad / Ac Ad = Differential mode gain
Ac = Common mode
gain Where Ad =
Vo /Vd
Vo = Output voltage measured across
CRO Vd = V 1 – V2 , V 1 , V2 – input
voltage applied. Ac = Vo /Vc
Vc = (V 1 + V2 )/2
DIFFERENTIAL MODE: Ad=Vo/Vd =
V1
=
V2
=
Output voltage
=
Vd= V1-V2
=
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COMMON MODE: Output voltage =
Input voltage V1=V2 =
Vc=(V1+V2)/2 =
=
Exp. No: 12
PASSIVE FILTERS
Aim:
To attenuate unwanted frequency components from input signal by using resistor
and capacitor.
Apparatus required:
Name of the apparatus Range Type Quantity
S.No
1. Signal Generator 01
2. Resistor 01
3. Capacitor Ceramic 01
4. CRO 01
5. Breadboard 01
Theory:
A filter is an AC circuit that separates some frequencies from other in
within mixed – frequency signals. Audio equalizers and crossover networks are
two well-known applications of filter circuits. A Bode plot is a graph plotting
waveform amplitude or phase on one axis and frequency on the other.
A low-pass filter allows for easy passage of low-frequency signals from
source to load, and difficult passage of high-frequency signals. Capacitor low-pass
filters insert a resistor in series and a capacitor in parallel with the load as shown
in the circuit diagram. The former filter design tries to “block” the unwanted
frequency signal while the latter tries to short it out.
The cutoff frequency for a low-pass filter is that frequency at which the
output (load) voltage equals 70.7% of the input (Source) voltage. Above the cutoff
frequency, the output voltage is lower than 70.7% of the input, and vice-versa. See
the circuit diagram
1
Fcutoff = ----------
2RC
A high-pass filter allows for easy passage of high-frequency signals from source to
load, and difficult passage of low-frequency signals. Capacitor high-pass filters
insert a capacitor in series with the load as shown in the circuit diagram. The
former filter design tries to “brick” the unwanted frequency signal while the latter
tries to short it out.
The cutoff frequency for a high-pass filter is that frequency at which the
output (load) voltage equals 70.7% of the input (source) voltage. Above the cutoff
frequency, the output voltage is greater than 70.7% of the input, and vice-versa.
1
Fcutoff = ----------
2RC
A band – pass filter works to screen out frequencies that are too low or too
high, giving easy passage only to frequencies within a certain range. Stacking a
low-pass filter on the end of a high-pass filter, or vice-versa can make band-pass
filters. Refer the circuit diagrams
Placing a low-pass filter in parallel with a high-pass filter can make band-
stop filters. Commonly, both the low-pass and high-pass filter sections are of the
“T” configuration giving the name “Twin-T” to the band-stop combination. Refer
the fig.7.7, 7.8a and 7.8b.
Passes low frequencies
Low-pass filter
Signal Signal
Input Output
High-pass filter
Fig. 7.8a
The frequency of maximum attenuation is called the notch
frequency.
Procedure:
7. Give the connections as per circuit diagrams.
8. Switch on the main.
9. Change the frequency from minimum and find the output
voltage by using CRO.
10. Draw the graph.
11. Verify the cut off frequency.
12. Switch off the main.
Result:
Thus we analyze passive filter and various waveforms are noted
Exp. No :
10
STUDY OF CRO AND
POWER FACTOR MEASUREMENT USING CRO
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Aim:
To study cathode Ray Oscilloscope (CRO) and measurement of power factor using
CRO.
Apparatus required:
Name of the apparatus Range Type Quantity
S.No
1. Resistance Box 1
2. Capacitance Box 1
3. Inductance Box 1
4. Function Generator 1
5. Bread board 1
Theory:
The cathode ray oscilloscope is the most versatile measuring instrument
available. We can measure following parameters using the CRO:
5. AC or DC voltage.
6. Time (t=1/f).
7. Phase relationship
8. Waveform calculation: Rise time; fall time; on time; off-time
Distortion, etc.
We can also measure non-electrical physical quantities like pressure, strain,
temperature, acceleration, etc., by converting into electrical quantities using
a transducer.
Major blocks:
7. Cathode ray tube (CRT)
8. Vertical amplifier
9. Horizontal amplifier
10. Sweep generator
6. The cathode ray tube is the heart of CRO. The CRT is enclosed in an
evacuated glass envelope to permit the electron beam to traverse in the
tube easily. The main functional units of CRO are as follows.
Electron gun assembly
Deflection plate unit
Screen.
7. Vertical Amplifier is the main factor in determining the bandwidth and
sensitivity of an oscilloscope. Vertical sensitivity is a measure of how
much the electron beam will be deflected for a specified input signal.
On the front panel of the oscilloscope, one can see a knob attached to a
rotary switch labeled volts/division. The rotary switch is electrically
connected to the input attenuation network. The setting of the rotary
switch indicates what amplitude signal is required to deflect the beam
vertically by one division.
8. Horizontal amplifier Under normal mode of operation, the horizontal
amplifier will amplify the sweep generator input. When the CRO is
being used in the X-Y mode, the horizontal amplifier will amplify the
signal applied to the horizontal input terminal. Although the vertical
amplifier mush be able to faithfully reproduce low-amplitude and high
frequency signal with fast rise-time, the horizontal amplifier is only
required to provide a faithful reproduction of the sweep signal which
has a relatively high amplitude and slow rise time.
9. Sweep generator and Trigger circuit These two units form the Signal
Synchronization unit of the CRO.
10. Associated Power Supply: The input signal may come from an
external source when the trigger selector switch is set to EXT or from
proportional to the deflecting voltage, the CRT may be used as a linear measuring
device. The voltage being measured is applied to the vertical plates through an
iterative network, whose propagation time corresponds to the velocity of electrons,
thereby synchronizing the voltage applied to the vertical plate with the velocity of
the beam.
Synchronization of input signal: The sweep generator produces a saw tooth
waveform, which is used to synchronize the applied voltage to obtain a stationary-
applied signal. This requires that the time base be operated at a submultiples
frequency of the signal under measurement. If synchronization is not done, the
pattern is not stationary, but appears to drift across the screen in a random fashion.
Internal synchronization This trigger is obtained from the time base generator to
synchronize the signal.
External synchronization An external trigger source can also be used to
synchronize the signal being measured.
Auto Triggering Mode The time base used in this case in a self-oscillating
condition, i.e., it gives an output even in the absence of any Y-input. The
advantage of this mode is that the beam is visible on the screen under all
conditions, including the zero input. When the input exceeds a certain magnitude
then the internal free running oscillator locks on to the frequency.
Precautions:
3. The ammeter is connected using thick wires.
4. While reversing ammeter polarity, see to it that the capacitor is not
discharged.
Observation:
Sl.No Time Voltage Current
Unit (Sec) (Volts) (Amps)
LIST OF EXPERIMENTS
131351 ELECTRON DEVICES AND CIRCUITS LABORATORY LTPC
(B.E. (EEE), B.E. (E&I) and B.E. (I & C) 0032
(Revised)
Ex.No.1a
CHARACTERISTICS OF PN JUNCTION DIODE
AIM:
To study the PN junction diode characteristics under Forward & Reverse
bias conditions.
1 R.P.S 1 Diode
2 Resistor
2 Ammeter Bread
3
Board
4 Wires
3 Voltmeter
THEORY:
A PN junction diode is a two terminal junction device. It conducts
only in one direction (only on forward biasing).
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier
potential. As the applied potential exceeds the barrier potential the
charge carriers gain sufficient energy to cross the potential barrier and
hence enter the other region. The holes, which are majority carriers in
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the P-region, become minority carriers on entering
the N-regions, and electrons, which are the majority carriers in the N-
region, become minority carriers on entering the P-region. This
injection of Minority carriers results in the current flow, opposite to the
direction of electron movement.
REVERSE BIAS:
On reverse biasing, the majority charge carriers are attracted
towards the terminals due to the applied potential resulting in the
widening of the depletion region. Since the charge carriers are pushed
towards the terminals no current flows in the device due to majority
charge carriers. There will be some current in the device due to the
thermally generated minority carriers. The generation of such carriers
is independent of the applied potential and hence the current is
constant for all increasing reverse potential. This current is referred to
as Reverse Saturation Current (IO) and it increases with temperature.
When the applied reverse voltage is increased beyond the certain limit,
it results in breakdown. During breakdown, the diode current increases
tremendously.
PROCEDURE:
FORWARD BIAS:
9. Connect the circuit as per the diagram.
10. Vary the applied voltage V in steps of 0.1V.
11. Note down the corresponding Ammeter readings I.
12. Plot a graph between V & I
OBSERVATIONS
7. Find the d.c (static) resistance = V/I.
V V1
8. Find the a.c (dynamic) resistance r = V / I (r = V/I) = 2 .
I 2 I1
9. Find the forward voltage drop = [Hint: it is equal to 0.7 for Si
and 0.3 for Ge]
REVERSE BIAS:
11. Connect the circuit as per the diagram.
12. Vary the applied voltage V in steps of 1.0V.
Io = I/[exp(V/VT)]-1
CIRCUIT DIAGRAM:
FORWARD BIAS:
(0-100)mA, MC
470 + -
+ +
(0-10)V (0-15)V, MC
RPS -
-
REVERSE BIAS:
(0-500)µA,MC
470 + -
+ +
(0-30)V (0-30)V, MC
RPS
- -
MODEL GRAPH
If (mA)
I2
Vb I1
V
( Volts) 1 V2 Vf
(Volts)
Ir (A)
RESULT:
Forward and Reverse bias characteristics of the PN junction diode
and the dynamic resistance under
i) Forward bias = ---------------------
ii) Reverse bias =------------------.
iii) Reverse Saturation Current =----------.
Ex.No.1b
CHARACTERISTICS OF ZENER DIODE
AIM:
To determine the breakdown voltage of a given zener diode.
THEORY:
A properly doped crystal diode, which has a sharp breakdown voltage,
is known as zener diode.
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier
potential. As the applied potential increases, it exceeds the barrier
potential at one value and the charge carriers gain sufficient energy to
cross the potential barrier and enter the other region. the holes ,which
are majority carriers in p-region, become minority carriers on entering
the N-regions and electrons, which are the majority carriers in the N-
regions become minority carriers on entering the P-region. This
injection of minority carriers results current, opposite to the direction
of electron movement.
ZENER EFFECT:
Normally, PN junction of Zener Diode is heavily doped. Due to
heavy doping the depletion layer will be narrow. When the reverse bias
is increased the potential across the depletion layer is more. This
exerts a force on the electrons in the outermost shell. Because of this
force the electrons are pulled away from the parent nuclei and become
free electrons. This ionization, which occurs due to electrostatic force
of attraction, is known as Zener effect. It results in large number of
free carriers, which in turn increases the reverse saturation current
PROCEDURE:
FORWARD BIAS:
1. Connect the circuit as per the circuit diagram.
2. Vary the power supply in such a way that the readings are
taken in steps of 0.1V in the voltmeter till the needle of power
supply shows 30V.
3. Note down the corresponding ammeter readings.
4. Plot the graph :V (vs) I.
5. Find the dynamic resistance r = V / I.
REVERSE BIAS:
13. Connect the circuit as per the diagram.
14. Vary the power supply in such a way that the readings are
taken in steps of 0.1V in the voltmeter till the needle of power
supply shows 30V.
15. Note down the corresponding Ammeter readings I.
16. Plot a graph between V & I
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17. Find the dynamic resistance r = V / I.
18. Find the reverse voltage Vr at Iz=20 mA.
CIRCUIT DIAGRAM:
FORWARD BIAS:
(0-10)mA
470 + -
+ +
(0-10) V 1 (0-15) V
-
-
REVERSE BIAS:
(0-500)µA, MC
1K + -
+ +
(0-30) V 1 (0-10) V, MC
-
-
ZENER DIODE:
If ( mA)
I2
Vr
VB I1 Vf
(V)
V1 V2 (V
)
Ir (µA)
TABULAR COLUMN:
FORWARD BIAS: REVERSE BIAS:
RESULT:
Forward and Reverse bias characteristics of the zener diode was
studied and
Forward bias dynamic resistance = ---------------------
Reverse bias dynamic resistance = ----------------------
The reverse voltage at Iz =20 mA determined from the
reverse characteristics of the Zener diode is-------.
Ex. No. 2a
AIM:
To plot the transistor characteristics of CE configuration.
THEORY:
A BJT is a three terminal two – junction semiconductor device in
which the conduction is due to both the charge carrier. Hence it is a
bipolar device and it amplifier the sine waveform as they are
transferred from input to output. BJT is classified into two types – NPN
or PNP. A NPN transistor consists of two N types in between which a
layer of P is sandwiched. The transistor consists of three terminal
emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts
a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped
and is of hollow cross sectional area. Normally the transistor operates
PROCEDURE:
INPUT CHARACTERISTICS:
OUTPUT CHARACTERISTICS:
PIN DIAGRAM:
B
E C
(0 – 30)mA 1 K
- +
A
(0 – 250) A C
+ +
10 K
+ A - (0-30)V
B BC107 V (0-30)V -
+ + -
(0-30)V (0-1)V V E
- -
CIRCUIT DIAGRAM:
MODEL GRAPH:
µA
mA
IC
IB
VCE = 0V
VCE = 5V
IB=60A
IB=40A IB=20A
0
VBE(V) 0
VCE(V)
TABULAR COLUMN:
INPUT CHARACTERISTICS:
VCE=1V VCE=2V
VBE(V) IB(µA) VBE(V) IB(µA)
OUTPUT CHARACTERISTICS:
IB=20A IB=40A
VCE(V) IC(mA) VCE(V) IC(mA)
RESULT:
The transistor characteristicsof a Common Emitter (CE)
configuration were plotted
Ex.No.2b
THEORY:
In this configuration the base is made common to both the input
and out. The emitter is given the input and the output is taken across
the collector. The current gain of this configuration is less than unity.
The voltage gain of CB configuration is high. Due to the high voltage
gain, the power gain is also high. In CB configuration, Base is common
to both input and output. In CB configuration the input characteristics
relate IE and VEB for a constant VCB. Initially let VCB = 0 then the input
junction is equivalent to a forward biased diode and the characteristics
resembles that of a diode. Where VCB = +VI (volts) due to early effect IE
increases and so the characteristics shifts to the left. The output
characteristics relate IC and VCB for a constant IE. Initially IC increases
and then it levels for a value IC = IE. When IE is increased IC also
increases proportionality. Though increase in VCB causes an increase in
, since is a fraction, it is negligible and so IC remains a constant for
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all values of VCB once it levels off.
PIN DIAGRAM:
B
E C
CIRCUIT DIAGRAM:
(0-1)mA (0-30)mA
10 K + - + - 1K
-
+ +
+
(0-30)V VEB (0-2)V (0-30)V (0-30)V
- - -
PROCEDURE:
INPUT CHARACTERISTICS:
It is the curve between emitter current IE and emitter-base voltage
VBE at constant collector-base voltage VCB.
9. Connect the circuit as per the circuit diagram.
10. Set VCE=5V, vary VBE in steps of 0.1V and
note down the corresponding IB. Repeat the above procedure
for 10V, 15V.
11. Plot the graph VBE Vs IB for a constant VCE.
12. Find the h parameters.
OUTPUT CHARACTERISTICS:
It is the curve between collector current IC and collector-base voltage
VCB at constant emitter current IE.
9. Connect the circuit as per the circuit diagram.
10. Set IB=20A, vary VCE in steps of 1V and note
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down the corresponding IC. Repeat the above procedure for
40A, 80A, etc.
TABULAR COLUMN:
INPUT CHARACTERISTICS:
OUTPUT CHARACTERISTICS:
MODEL GRAPH:
INPUT CHARACTERISTICS:
IC
(mA
)
VCB1
IE2
VCB2
OUTPUT CHARACTERISTICS:
IC
(mA) IE3
IC2 IE2
IC1
IE1
AIM:
To plot the transistor characteristics of CE configuration.
THEORY:
A BJT is a three terminal two – junction semiconductor device in
which the conduction is due to both the charge carrier. Hence it is a
bipolar device and it amplifier the sine waveform as they are
transferred from input to output. BJT is classified into two types – NPN
or PNP. A NPN transistor consists of two N types in between which a
layer of P is sandwiched. The transistor consists of three terminal
emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts
a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped
and is of hollow cross sectional area. Normally the transistor operates
with the EB junction forward biased.
E C
(0-30)mA 1 K
+- A
(0-250)µA +
1 K +
+ - +V (0-30)V
A (0-30)V -
-
+ +
(0-30)VV (0-30)V
- -
CIRCUIT DIAGRAM:
PROCEDURE:
INPUT CHARECTERISTICS:
OUTPUT CHARECTERISTICS:
8. Set IB, Vary VCE in regular interval of steps and note down the
corresponding IC reading. Repeat the above procedure for
different values of IB.
9. Plot the graph: VCE Vs IC for a constant IB.
MODEL GRAPH:
INPUT CHARACTERISTICS: OUTPUT CHARACTERISTICS:
(A) (mA)
IB Ie
VCE=0 VCE=5V IB=60A
IB=40A
IB=20A
0 VBC(V) 0 VCE(V)
TABULAR COLUMN:
INPUT CHARACTERISTICS:
VCE=1V VCE=2V
VBC(V) IB(µA) VBC(V) IB(µA)
OUTPUT CHARACTERISTICS:
IB=20A IB=40A
VCE(V) IE(mA) VCE(V) IE(mA)
RESULT:
The transistor characteristics of a Common Emitter (CC)
configuration were plotted.
Ex.No.3
AIM:
To Plot the characteristics of given FET & determine rd, gm, , IDSS,VP.
1k 1
2 Ammeter (0–30)mA 1 2 Resistor
68K 1
Bread
(0–30)V 1 3 1
3 Voltmeter Board
(0-10)V 1 4 Wires
THEORY:
FET is a voltage operated device. It has got 3 terminals. They are
Source, Drain & Gate. When the gate is biased negative with respect
to the source, the pn junctions are reverse biased & depletion regions
are formed. The channel is more lightly doped than the p type gate, so
the depletion regions penetrate deeply in to the channel. The result is
that the channel is narrowed, its resistance is increased, & ID is
reduced. When the negative bias voltage is further increased, the
depletion regions meet at the center & ID is cutoff completely.
PROCEDURE:
DRAIN CHARACTERISTICS:
11. Connect the circuit as per the circuit diagram.
12. Set the gate voltage VGS = 0V.
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13. Vary VDS in steps of 1 V & note down the corresponding ID.
TRANSFER CHARACTERISTICS:
11. Connect the circuit as per the circuit diagram.
12. Set the drain voltage VDS = 5 V.
13. Vary the gate voltage VGS in steps of 1V & note down the corresponding
ID.
14. Repeat the same procedure for VDS = 10V.
15. Plot the graph VGS Vs ID for constant VDS.
ID
Transconductance = VGS VDS
gm
PIN DIAGRAM:
BOTTOM VIEW OF BFW10:
SPECIFICATION:
Voltage : 30V, IDSS > 8mA.
MODEL GRAPH:
DRAIN CHARACTERISTICS:
ID (mA)
VGS = 0V
VGS = -1V
VGS = -2V
VGS = -3V
0
VDS (volts)
TRANSFER CHARACTERISTICS:
ID(mA)
VDS =Const
VGS (V)
TABULAR COLUMN:
DRAIN CHARACTERISTICS:
TRANSFER CHARACTERISTICS:
RESULT:
Thus the Drain & Transfer characteristics of given FET is Plotted.
Rd =
gm =
=
IDSS =
Pinch off voltage VP =
Ex.No.4
THEORY:
UJT(Double base diode) consists of a bar of lightly doped n-type
silicon with a small piece of heavily doped P type material joined to one
side. It has got three terminals. They are Emitter(E),
Base1(B1),Base2(B2).Since the silicon bar is lightly doped, it has a
high resistance & can be represented as two resistors, rB1 & rB2. When
VB1B2 = 0, a small increase in V E forward biases the emitter junction.
The resultant plot of VE & I E is simply the characteristics of forward
biased diode with resistance. Increasing VEB1 reduces the emitter
junction reverse bias. When VEB1 = VrB1 there is no forward or reverse
bias. & IE = 0. Increasing VEB1 beyond this point begins to forward bias
the emitter junction. At the peak point, a small forward emitter
current is flowing. This current is termed as peak current( IP ). Until
this point UJT is said to be operating in cutoff region. When IE increases
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beyond peak current the device enters the negative resistance region.
In which the resistance rB1 falls rapidly & VE falls to the valley
PROCEDURE:
11. Connect the circuit as per the circuit diagram.
12. Set VB1B2 = 0V, vary VEB1 , & note down the readings of IE & VEB1
13. Set VB1B2 = 10V , vary VEB1 , & note down the readings of IE & VEB1
14. Plot the graph : IE Versus VEB1 for constant VB1B2.
15. Find the intrinsic standoff ratio.
CIRCUIT DIAGRAM:
1KΩ B2
(0-30A)mA 1KΩ
VE V
(0-30)V (0-30)V
B2 (0-30)V
(0-30)V
PIN DIAGRAM:
MODEL GRAPH:
Peak point
VP
IP
Negative resistance region
VEB1(V)
IV IE (mA)
TABULAR COLUMN:
VB1B2 = 0V VB1B2 = 10V
VEB1 (V) IE (mA) VEB1 (V) IE (mA)
PROCEDURE:
9. Give the circuit connections as per the circuit diagram.
10. The dc input voltage is set to 20 V in RPS.
11. The output sweep waveform is measured using CRO.
12. The graph of output sweep waveform is plotted
RESULT:
1. Thus the characteristics of given UJT was Plotted & its intrinsic
standoff Ratio = ----.
Ex.No.5
CHARACTERISTICS OF PHOTO-DIODE AND
PHOTOTRANSISTOR
AIM:
THEORY:
PHOTODIODE:
through the reverse biased diode. This current is termed as the dark
current of the photo diode. Now when light is incident on the photo
diode then the thermally generated carriers increase resulting in an
increased reverse current which is proportional to the intensity of
incident light. A photo diode can turn on and off at a faster rate and so
it is used as a fast acting switch.
CIRCUIT DIAGRAM:
(0-30)mA
1K
(0-30)V (0-30)V
TABULAR COLUMN:
MODEL GRAPH:
R (K)
Illumination lm/m2
PHOTOTRANSISTOR:
CIRCUIT DIAGRAM:
N P N
1K
(0-30V)
S. No. VCE IC C
(in Volts) (in mA)
Page 148
MODEL GRAPH:
IC
(mA)
400 Lux
200 Lux
0 Lux
VCE(V)
PROCEDURE:
PHOTO DIODE:
PHOTOTRANSISTOR:
11. Rig up the circuit as per the circuit diagram.
12. Maintain a known distance (say 5 cm) between the
DC bulb and the phototransistor.
13. Set the voltage of the bulb (say, 2V), vary the
voltage of the diode in steps of 1V and note down the
corresponding diode current, Ir.
14. Repeat the above procedure for the various values of DC bulb.
15. Plot the graph: VD vs. Ir for a constant bulb voltage.
RESULT:
Page 149
Thus the characteristics of photo diode and phototransistor are studied.
Page 150
Ex.No.6
CHARACTERISTICS OF THERMISTOR
AIM:
To study the characteristics of Thermistor.
THEORY:
Thermistor or Thermal resistor is two – terminal semiconductor
device whose resistance is temperature sensitive. The value of such
resistors decreases with increase in temperature. Materials employed
in the manufacture of the thermistors include oxides of cobalt, nickel,
copper, iron uranium and manganese.
Page 151
temperature of the device can be changed internally or externally. An
increase in current through the device will raise its temperature
carrying a drop in its terminal resistance. Any externally
Page 152
heat source will result in an increase in its body temperature and drop
in resistance this type action (internal or external) lends itself well to
control mechanism.
SYMBOL:
MODEL GRAPH:
R
(-cm)
T (deg)
Page 153
is approximately
Page 154
3 – 60.
Thermistors are used measure temperature, flow pressure, liquid
level, voltage or power level, vacuum, composition of gases and
thermal conductivity and also in compensation network.
RESULT:
Thus the Characteristics of thermistor was studied.
Page 155
Page 156
Ex.No.7a
SINGLE PHASE HALF WAVE RECTIFIER
AIM:
To construct a Half wave rectifier using diode and to draw its
performance characteristics.
FORMULAE:
WITHOUT FILTER:
(i) Vrms = Vm / 2
(ii) Vdc = Vm /
(iii) Ripple Factor= (Vrms / Vdc)2 – 1
(iv) Efficiency = (Vdc / Vrms)2 x 100
WITH FILTER:
’2 2
(i) Vrms = (Vrms + Vdc )
(ii) Vrms’ = Vrpp / (3 x 2)
(iii) Vdc = Vm – V rpp /2
(iv) Ripple Factor= Vrms’/ Vdc
Page 157
PROCEDURE:
WITHOUT FILTER:
9. Give the connections as per the circuit diagram.
10. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
11. Take the rectifier output across the Load.
12. Plot its performance graph.
WITH FILTER:
1. Give the connections as per the circuit diagram.
10. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
11. Connect the Capacitor across the Load.
12. Take the rectifier output across the Load.
13. Plot its performance graph.
CIRCUIT DIAGRAM:
1 Transformer
230 V / 6V
1N 4007
1K
1, 230V, 100F
CRO
50Hz
AC supply
Page 158
TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms Vdc Ripple factor Efficiency
WITH FILTER:
Vrms Vrpp Vdc Ripple factor Efficiency
MODEL GRAPH:
Vin
(Volts)
t (ms)
Vo
(Volts) Without
t (ms)
Vo
(Volts) With
t (ms)
RESULT:
Thus the performance characteristics of 1 Half wave rectifier was obtained.
Page 159
Ex.No.7b
SINGLE PHASE FULL WAVE RECTIFIER
AIM:
To construct a Full wave rectifier using diode and to draw its
performance characteristics.
FORMULAE:
WITHOUT FILTER:
(i) Vrms = Vm / 2
(ii) Vdc = 2Vm /
(iii) Ripple Factor= (Vrms / Vdc)2 – 1
(iv) Efficiency = (Vdc / Vrms)2 x 100
WITH FILTER:
(i) Vrms = Vrpp /(2* 3)
(ii) Vdc = Vm – V rpp
Page 160
PROCEDURE:
WITHOUT FILTER:
9. Give the connections as per the circuit diagram.
10. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
11. Take the rectifier output across the Load.
12. Plot its performance graph.
WITH FILTER:
1. Give the connections as per the circuit diagram.
10. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
11. Connect the Capacitor across the Load.
12. Take the rectifier output across the Load.
13. Plot its performance graph.
CIRCUIT DIAGRAM:
1 Transformer 1N 4007
230 V / 6V
100F
1K
1, 230V,
CRO
50Hz
AC supply
1N 4007
Page 161
TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms Vdc Ripple factor Efficiency
WITH FILTER:
Vrms Vrpp Vdc Ripple factor Efficiency
MODEL GRAPH :
Vin
(Volts)
t (ms)
Vo
(Volts) Without Filter
t (ms)
Vo
(Volts) With Filter
t (ms)
Page 162
Ex.No.8
DIFFERENTIAL AMPLIFIER
AIM:
To construct a Differential amplifier in Common mode & Differential mode
configuration and to find common mode rejection ratio.
THEORY:
The Differential amplifier circuit is an extremely popular
connection used in IC units. The circuit has separate inputs , two
separate outputs and emitters are connected together. If the same
input is applied to both inputs, the operation is called common mode.
In double ended operation two input signals are applied , the difference
of the inputs resulting in outputs from both collectors due to the
difference of the signals applied to both the inputs. The main feature of
the differential amplifier is the very large gain when opposite signals
are applied to inputs as compared to small signal resulting from
common input. The ratio of this difference gain to the common gain is
called common mode rejection ratio.
Page 155
CIRCUIT DIAGRAM:
DIFFERENTIAL MODE:
3.9K 3.9K
Vo1Vo2
V1
12V V2
13V
3.3 K
-9V
9V
COMMON MODE:
3.9K 3.9K
Vo1 Vo2
V2
13V
3.3 K
Page 156
-9V
PROCEDURE:
DIFFERENTIAL MODE:
9. Connect the circuit as per the circuit diagram.
10. Set V1 = 50mv and V2 =55mv using the signal generator.
11. Find the corresponding output voltages across V01 & V02 using CRO
12. Calculate common mode rejection ratio using the given formula.
COMMON MODE:
9. Connect the circuit as per the circuit diagram.
10. Set V1 = 50mv using the signal generator.
11. Find the output voltage across Vo using multimeter.
12. Calculte common mode rejection ratio using the given formula.
CALCULATION:
Common mode rejection ratio(CMRR) =
Ad / Ac Ad = Differential mode gain
Ac = Common mode
gain Where Ad =
Vo /Vd
Vo = Output voltage measured across
CRO Vd = V 1 – V2 , V 1 , V2 – input
voltage applied. Ac = Vo /Vc
Vc = (V 1 + V2 )/2
DIFFERENTIAL MODE: Ad=Vo/Vd =
V1
=
V2
=
Output voltage
=
Vd= V1-V2
=
COMMON MODE: Output voltage =
Input voltage V1=V2 =
Vc=(V1+V2)/2 =
=
Exp. No: 12
PASSIVE FILTERS
Aim:
To attenuate unwanted frequency components from input signal by using resistor
and capacitor.
Apparatus required:
Name of the apparatus Range Type Quantity
S.No
1. Signal Generator 01
2. Resistor 01
3. Capacitor Ceramic 01
4. CRO 01
5. Breadboard 01
Theory:
A filter is an AC circuit that separates some frequencies from other in
within mixed – frequency signals. Audio equalizers and crossover networks are
two well-known applications of filter circuits. A Bode plot is a graph plotting
waveform amplitude or phase on one axis and frequency on the other.
A low-pass filter allows for easy passage of low-frequency signals from
source to load, and difficult passage of high-frequency signals. Capacitor low-pass
filters insert a resistor in series and a capacitor in parallel with the load as shown
in the circuit diagram. The former filter design tries to “block” the unwanted
frequency signal while the latter tries to short it out.
The cutoff frequency for a low-pass filter is that frequency at which the
output (load) voltage equals 70.7% of the input (Source) voltage. Above the cutoff
frequency, the output voltage is lower than 70.7% of the input, and vice-versa. See
the circuit diagram
1
Fcutoff = ----------
2RC
A high-pass filter allows for easy passage of high-frequency signals from source to
load, and difficult passage of low-frequency signals. Capacitor high-pass filters
insert a capacitor in series with the load as shown in the circuit diagram. The
former filter design tries to “brick” the unwanted frequency signal while the latter
tries to short it out.
The cutoff frequency for a high-pass filter is that frequency at which the
output (load) voltage equals 70.7% of the input (source) voltage. Above the cutoff
frequency, the output voltage is greater than 70.7% of the input, and vice-versa.
1
Fcutoff = ----------
2RC
A band – pass filter works to screen out frequencies that are too low or too
high, giving easy passage only to frequencies within a certain range. Stacking a
low-pass filter on the end of a high-pass filter, or vice-versa can make band-pass
filters. Refer the circuit diagrams
Low-pass filter
Signal Signal
Input Output
High-pass filter
Fig. 7.8a
The frequency of maximum attenuation is called the notch
frequency.
Procedure:
13. Give the connections as per circuit diagrams.
14. Switch on the main.
15. Change the frequency from minimum and find the output
voltage by using CRO.
16. Draw the graph.
17. Verify the cut off frequency.
18. Switch off the main.
Result:
Thus we analyze passive filter and various waveforms are noted
Exp. No :
10
STUDY OF CRO AND
POWER FACTOR MEASUREMENT USING CRO
Aim:
To study cathode Ray Oscilloscope (CRO) and measurement of power factor using
CRO.
Apparatus required:
Name of the apparatus Range Type Quantity
S.No
1. Resistance Box 1
2. Capacitance Box 1
3. Inductance Box 1
4. Function Generator 1
5. Bread board 1
Theory:
The cathode ray oscilloscope is the most versatile measuring instrument
available. We can measure following parameters using the CRO:
9. AC or DC voltage.
10. Time (t=1/f).
11. Phase relationship
12. Waveform calculation: Rise time; fall time; on time; off-time
Distortion, etc.
We can also measure non-electrical physical quantities like pressure, strain,
temperature, acceleration, etc., by converting into electrical quantities using
a transducer.
Major blocks:
13. Cathode ray tube (CRT)
14. Vertical amplifier
15. Horizontal amplifier
16. Sweep generator
17. Trigger circuit
18. Associated power supply.
11. The cathode ray tube is the heart of CRO. The CRT is enclosed in an
evacuated glass envelope to permit the electron beam to traverse in the
tube easily. The main functional units of CRO are as follows.
Electron gun assembly
Deflection plate unit
Screen.
12. Vertical Amplifier is the main factor in determining the bandwidth and
sensitivity of an oscilloscope. Vertical sensitivity is a measure of how
much the electron beam will be deflected for a specified input signal.
On the front panel of the oscilloscope, one can see a knob attached to a
rotary switch labeled volts/division. The rotary switch is electrically
connected to the input attenuation network. The setting of the rotary
switch indicates what amplitude signal is required to deflect the beam
vertically by one division.
13. Horizontal amplifier Under normal mode of operation, the horizontal
amplifier will amplify the sweep generator input. When the CRO is
being used in the X-Y mode, the horizontal amplifier will amplify the
signal applied to the horizontal input terminal. Although the vertical
amplifier mush be able to faithfully reproduce low-amplitude and high
frequency signal with fast rise-time, the horizontal amplifier is only
required to provide a faithful reproduction of the sweep signal which
has a relatively high amplitude and slow rise time.
14. Sweep generator and Trigger circuit These two units form the Signal
Synchronization unit of the CRO.
15. Associated Power Supply: The input signal may come from an
external source when the trigger selector switch is set to EXT or from
low amplitude AC voltage at line frequency when the switch is set to
LINE or from the vertical amplifier when the switch is set to INT. When
set for INT (internal triggering), the trigger circuit receives its inputs
from the vertical amplifier.
LIST OF EXPERIMENTS
131351 ELECTRON DEVICES AND CIRCUITS LABORATORY LTPC
(B.E. (EEE), B.E. (E&I) and B.E. (I & C) 0032
(Revised)
AIM:
To study the PN junction diode characteristics under Forward & Reverse
bias conditions.
1 R.P.S 1 Diode
2 Resistor
2 Ammeter Bread
3
Board
4 Wires
3 Voltmeter
THEORY:
A PN junction diode is a two terminal junction device. It conducts
only in one direction (only on forward biasing).
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier
potential. As the applied potential exceeds the barrier potential the
charge carriers gain sufficient energy to cross the potential barrier and
hence enter the other region. The holes, which are majority carriers in
the P-region, become minority carriers on entering
the N-regions, and electrons, which are the majority carriers in the N-
region, become minority carriers on entering the P-region. This
injection of Minority carriers results in the current flow, opposite to the
direction of electron movement.
REVERSE BIAS:
On reverse biasing, the majority charge carriers are attracted
towards the terminals due to the applied potential resulting in the
widening of the depletion region. Since the charge carriers are pushed
towards the terminals no current flows in the device due to majority
charge carriers. There will be some current in the device due to the
thermally generated minority carriers. The generation of such carriers
is independent of the applied potential and hence the current is
constant for all increasing reverse potential. This current is referred to
as Reverse Saturation Current (IO) and it increases with temperature.
When the applied reverse voltage is increased beyond the certain limit,
it results in breakdown. During breakdown, the diode current increases
tremendously.
PROCEDURE:
FORWARD BIAS:
13. Connect the circuit as per the diagram.
14. Vary the applied voltage V in steps of 0.1V.
15. Note down the corresponding Ammeter readings I.
16. Plot a graph between V & I
OBSERVATIONS
10. Find the d.c (static) resistance = V/I.
V2 V1
11. Find the a.c (dynamic) resistance r = V / I (r = V/I) = .
I 2 I1
12. Find the forward voltage drop = [Hint: it is equal to 0.7
for Si and 0.3 for Ge]
REVERSE BIAS:
16. Connect the circuit as per the diagram.
17. Vary the applied voltage V in steps of 1.0V.
18. Note down the corresponding Ammeter readings I.
19. Plot a graph between V & I
20. Find the dynamic resistance r = V / I.
Io = I/[exp(V/VT)]-1
CIRCUIT DIAGRAM:
FORWARD BIAS:
(0-100)mA, MC
470 + -
+ +
(0-10)V (0-15)V, MC
RPS -
-
REVERSE BIAS:
(0-500)µA,MC
470 + -
+ +
(0-30)V (0-30)V, MC
RPS
- -
Specification for 1N4001: Silicon Diode
Peak Inverse Voltage:
50V Idc = 1A.
Maximum forward voltage drop at 1 Amp is
1.1 volts Maximum reverse current @50 volts
is 5A TABULAR COLUMN:
FORWARD BIAS: REVERSE BIAS:
MODEL GRAPH
If (mA)
I2
Vb I1
V
( Volts) 1 V2 Vf
(Volts)
Ir (A)
RESULT:
Forward and Reverse bias characteristics of the PN junction diode
and the dynamic resistance under
i) Forward bias = ---------------------
ii) Reverse bias =------------------.
iii) Reverse Saturation Current =----------.
Ex.No.1b
CHARACTERISTICS OF ZENER DIODE
AIM:
To determine the breakdown voltage of a given zener diode.
THEORY:
A properly doped crystal diode, which has a sharp breakdown voltage,
is known as zener diode.
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier
potential. As the applied potential increases, it exceeds the barrier
potential at one value and the charge carriers gain sufficient energy to
cross the potential barrier and enter the other region. the holes ,which
are majority carriers in p-region, become minority carriers on entering
the N-regions and electrons, which are the majority carriers in the N-
regions become minority carriers on entering the P-region. This
injection of minority carriers results current, opposite to the direction
of electron movement.
REVERSE BIAS:
When the reverse bias is applied due to majority carriers small
amount of current (ie) reverse saturation current flows across the
junction. As the reverse bias is increased to breakdown voltage,
sudden rise in current takes place due to zener effect.
ZENER EFFECT:
Normally, PN junction of Zener Diode is heavily doped. Due to
heavy doping the depletion layer will be narrow. When the reverse bias
is increased the potential across the depletion layer is more. This
exerts a force on the electrons in the outermost shell. Because of this
force the electrons are pulled away from the parent nuclei and become
free electrons. This ionization, which occurs due to electrostatic force
of attraction, is known as Zener effect. It results in large number of
free carriers, which in turn increases the reverse saturation current
PROCEDURE:
FORWARD BIAS:
1. Connect the circuit as per the circuit diagram.
2. Vary the power supply in such a way that the readings are
taken in steps of 0.1V in the voltmeter till the needle of power
supply shows 30V.
3. Note down the corresponding ammeter readings.
4. Plot the graph :V (vs) I.
5. Find the dynamic resistance r = V / I.
REVERSE BIAS:
19. Connect the circuit as per the diagram.
20. Vary the power supply in such a way that the readings are
taken in steps of 0.1V in the voltmeter till the needle of power
supply shows 30V.
21. Note down the corresponding Ammeter readings I.
22. Plot a graph between V & I
23. Find the dynamic resistance r = V / I.
24. Find the reverse voltage Vr at Iz=20 mA.
CIRCUIT DIAGRAM:
FORWARD BIAS:
(0-10)mA
470 + -
+ +
(0-10) V 1 (0-15) V
-
-
REVERSE BIAS:
(0-500)µA, MC
1K + -
+ +
(0-30) V 1 (0-10) V, MC
-
-
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ZENER DIODE:
If ( mA)
I2
Vr
VB I1 Vf
(V)
V1 V2 (V
)
Ir (µA)
TABULAR COLUMN:
FORWARD BIAS: REVERSE BIAS:
RESULT:
Forward and Reverse bias characteristics of the zener diode was
studied and
Forward bias dynamic resistance = ---------------------
Reverse bias dynamic resistance = ----------------------
The reverse voltage at Iz =20 mA determined from the
reverse characteristics of the Zener diode is-------.
Ex. No. 2a
AIM:
To plot the transistor characteristics of CE configuration.
THEORY:
A BJT is a three terminal two – junction semiconductor device in
which the conduction is due to both the charge carrier. Hence it is a
bipolar device and it amplifier the sine waveform as they are
transferred from input to output. BJT is classified into two types – NPN
or PNP. A NPN transistor consists of two N types in between which a
layer of P is sandwiched. The transistor consists of three terminal
emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts
a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped
and is of hollow cross sectional area. Normally the transistor operates
PROCEDURE:
INPUT CHARACTERISTICS:
OUTPUT CHARACTERISTICS:
PIN DIAGRAM:
B
E C
(0 – 30)mA 1 K
- +
A
(0 – 250) A C
+ +
10 K
+ A - (0-30)V
B BC107 V (0-30)V -
+ + -
(0-30)V (0-1)V V E
- -
CIRCUIT DIAGRAM:
MODEL GRAPH:
µA
mA
IC
IB
VCE = 0V
VCE = 5V
IB=60A
IB=40A IB=20A
0
VBE(V) 0
VCE(V)
TABULAR COLUMN:
INPUT CHARACTERISTICS:
VCE=1V VCE=2V
VBE(V) IB(µA) VBE(V) IB(µA)
OUTPUT CHARACTERISTICS:
IB=20A IB=40A
VCE(V) IC(mA) VCE(V) IC(mA)
RESULT:
The transistor characteristicsof a Common Emitter (CE)
configuration were plotted
Ex.No.2b
THEORY:
In this configuration the base is made common to both the input
and out. The emitter is given the input and the output is taken across
the collector. The current gain of this configuration is less than unity.
The voltage gain of CB configuration is high. Due to the high voltage
gain, the power gain is also high. In CB configuration, Base is common
to both input and output. In CB configuration the input characteristics
relate IE and VEB for a constant VCB. Initially let VCB = 0 then the input
junction is equivalent to a forward biased diode and the characteristics
resembles that of a diode. Where VCB = +VI (volts) due to early effect IE
increases and so the characteristics shifts to the left. The output
characteristics relate IC and VCB for a constant IE. Initially IC increases
and then it levels for a value IC = IE. When IE is increased IC also
increases proportionality. Though increase in VCB causes an increase in
, since is a fraction, it is negligible and so IC remains a constant for
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all values of VCB once it levels off.
PIN DIAGRAM:
B
E C
CIRCUIT DIAGRAM:
(0-1)mA (0-30)mA
10 K + - + - 1K
-
+ +
+
(0-30)V VEB (0-2)V (0-30)V (0-30)V
- - -
PROCEDURE:
INPUT CHARACTERISTICS:
It is the curve between emitter current IE and emitter-base voltage
VBE at constant collector-base voltage VCB.
13. Connect the circuit as per the circuit diagram.
14. Set VCE=5V, vary VBE in steps of 0.1V and
note down the corresponding IB. Repeat the above procedure
for 10V, 15V.
15. Plot the graph VBE Vs IB for a constant VCE.
16. Find the h parameters.
OUTPUT CHARACTERISTICS:
It is the curve between collector current IC and collector-base voltage
VCB at constant emitter current IE.
13. Connect the circuit as per the circuit diagram.
14. Set IB=20A, vary VCE in steps of 1V and note
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down the corresponding IC. Repeat the above procedure for
40A, 80A, etc.
TABULAR COLUMN:
INPUT CHARACTERISTICS:
OUTPUT CHARACTERISTICS:
MODEL GRAPH:
INPUT CHARACTERISTICS:
IC
(mA
)
VCB1
IE2
VCB2
OUTPUT CHARACTERISTICS:
IC
(mA) IE3
IC2 IE2
IC1
IE1
AIM:
To plot the transistor characteristics of CE configuration.
THEORY:
A BJT is a three terminal two – junction semiconductor device in
which the conduction is due to both the charge carrier. Hence it is a
bipolar device and it amplifier the sine waveform as they are
transferred from input to output. BJT is classified into two types – NPN
or PNP. A NPN transistor consists of two N types in between which a
layer of P is sandwiched. The transistor consists of three terminal
emitter, collector and base. The emitter layer is the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts
a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped
and is of hollow cross sectional area. Normally the transistor operates
with the EB junction forward biased.
E C
(0-30)mA 1 K
+- A
(0-250)µA +
1 K +
+ - +V (0-30)V
A (0-30)V -
-
+ +
(0-30)VV (0-30)V
- -
CIRCUIT DIAGRAM:
PROCEDURE:
INPUT CHARECTERISTICS:
OUTPUT CHARECTERISTICS:
11. Set IB, Vary VCE in regular interval of steps and note down
the corresponding IC reading. Repeat the above procedure for
different values of IB.
12. Plot the graph: VCE Vs IC for a constant IB.
MODEL GRAPH:
INPUT CHARACTERISTICS: OUTPUT CHARACTERISTICS:
(A) (mA)
IB Ie
VCE=0 VCE=5V IB=60A
IB=40A
IB=20A
0 VBC(V) 0 VCE(V)
TABULAR COLUMN:
INPUT CHARACTERISTICS:
VCE=1V VCE=2V
VBC(V) IB(µA) VBC(V) IB(µA)
OUTPUT CHARACTERISTICS:
IB=20A IB=40A
VCE(V) IE(mA) VCE(V) IE(mA)
RESULT:
The transistor characteristics of a Common Emitter (CC)
configuration were plotted.
Ex.No.3
AIM:
To Plot the characteristics of given FET & determine rd, gm, , IDSS,VP.
1k 1
2 Ammeter (0–30)mA 1 2 Resistor
68K 1
Bread
(0–30)V 1 3 1
3 Voltmeter Board
(0-10)V 1 4 Wires
THEORY:
FET is a voltage operated device. It has got 3 terminals. They are
Source, Drain & Gate. When the gate is biased negative with respect
to the source, the pn junctions are reverse biased & depletion regions
are formed. The channel is more lightly doped than the p type gate, so
the depletion regions penetrate deeply in to the channel. The result is
that the channel is narrowed, its resistance is increased, & ID is
reduced. When the negative bias voltage is further increased, the
depletion regions meet at the center & ID is cutoff completely.
PROCEDURE:
DRAIN CHARACTERISTICS:
16. Connect the circuit as per the circuit diagram.
17. Set the gate voltage VGS = 0V.
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18. Vary VDS in steps of 1 V & note down the corresponding ID.
TRANSFER CHARACTERISTICS:
16. Connect the circuit as per the circuit diagram.
17. Set the drain voltage VDS = 5 V.
18. Vary the gate voltage VGS in steps of 1V & note down the corresponding
ID.
19. Repeat the same procedure for VDS = 10V.
20. Plot the graph VGS Vs ID for constant VDS.
ID
Transconductance = VGS VDS
gm
PIN DIAGRAM:
BOTTOM VIEW OF BFW10:
SPECIFICATION:
Voltage : 30V, IDSS > 8mA.
MODEL GRAPH:
DRAIN CHARACTERISTICS:
ID (mA)
VGS = 0V
VGS = -1V
VGS = -2V
VGS = -3V
0
VDS (volts)
TRANSFER CHARACTERISTICS:
ID(mA)
VDS =Const
VGS (V)
TABULAR COLUMN:
DRAIN CHARACTERISTICS:
TRANSFER CHARACTERISTICS:
RESULT:
Thus the Drain & Transfer characteristics of given FET is Plotted.
Rd =
gm =
=
IDSS =
Pinch off voltage VP =
Ex.No.4
THEORY:
UJT(Double base diode) consists of a bar of lightly doped n-type
silicon with a small piece of heavily doped P type material joined to one
side. It has got three terminals. They are Emitter(E),
Base1(B1),Base2(B2).Since the silicon bar is lightly doped, it has a
high resistance & can be represented as two resistors, rB1 & rB2. When
VB1B2 = 0, a small increase in V E forward biases the emitter junction.
The resultant plot of VE & I E is simply the characteristics of forward
biased diode with resistance. Increasing VEB1 reduces the emitter
junction reverse bias. When VEB1 = VrB1 there is no forward or reverse
bias. & IE = 0. Increasing VEB1 beyond this point begins to forward bias
the emitter junction. At the peak point, a small forward emitter
current is flowing. This current is termed as peak current( IP ). Until
this point UJT is said to be operating in cutoff region. When IE increases
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beyond peak current the device enters the negative resistance region.
In which the resistance rB1 falls rapidly & VE falls to the valley
PROCEDURE:
16. Connect the circuit as per the circuit diagram.
17. Set VB1B2 = 0V, vary VEB1 , & note down the readings of IE & VEB1
18. Set VB1B2 = 10V , vary VEB1 , & note down the readings of IE & VEB1
19. Plot the graph : IE Versus VEB1 for constant VB1B2.
20. Find the intrinsic standoff ratio.
CIRCUIT DIAGRAM:
1KΩ B2
(0-30A)mA 1KΩ
VE V
(0-30)V (0-30)V
B2 (0-30)V
(0-30)V
PIN DIAGRAM:
MODEL GRAPH:
Peak point
VP
IP
Negative resistance region
VEB1(V)
IV IE (mA)
TABULAR COLUMN:
VB1B2 = 0V VB1B2 = 10V
VEB1 (V) IE (mA) VEB1 (V) IE (mA)
PROCEDURE:
13. Give the circuit connections as per the circuit diagram.
14. The dc input voltage is set to 20 V in RPS.
15. The output sweep waveform is measured using CRO.
16. The graph of output sweep waveform is plotted
RESULT:
1. Thus the characteristics of given UJT was Plotted & its intrinsic
standoff Ratio = ----.
Ex.No.5
CHARACTERISTICS OF PHOTO-DIODE AND
PHOTOTRANSISTOR
AIM:
THEORY:
PHOTODIODE:
through the reverse biased diode. This current is termed as the dark
current of the photo diode. Now when light is incident on the photo
diode then the thermally generated carriers increase resulting in an
increased reverse current which is proportional to the intensity of
incident light. A photo diode can turn on and off at a faster rate and so
it is used as a fast acting switch.
CIRCUIT DIAGRAM:
(0-30)mA
1K
(0-30)V (0-30)V
TABULAR COLUMN:
MODEL GRAPH:
R (K)
Illumination lm/m2
THEORY:
PHOTOTRANSISTOR:
CIRCUIT DIAGRAM:
N P N
1K
(0-30V)
S. No. VCE IC C
(in Volts) (in mA)
MODEL GRAPH:
IC
(mA)
400 Lux
200 Lux
0 Lux
VCE(V)
PROCEDURE:
PHOTO DIODE:
PHOTOTRANSISTOR:
16. Rig up the circuit as per the circuit diagram.
17. Maintain a known distance (say 5 cm) between the
DC bulb and the phototransistor.
18. Set the voltage of the bulb (say, 2V), vary the
voltage of the diode in steps of 1V and note down the
corresponding diode current, Ir.
19. Repeat the above procedure for the various values of DC bulb.
20. Plot the graph: VD vs. Ir for a constant bulb voltage.
RESULT:
Ex.No.6
CHARACTERISTICS OF THERMISTOR
AIM:
To study the characteristics of Thermistor.
THEORY:
Thermistor or Thermal resistor is two – terminal semiconductor
device whose resistance is temperature sensitive. The value of such
resistors decreases with increase in temperature. Materials employed
in the manufacture of the thermistors include oxides of cobalt, nickel,
copper, iron uranium and manganese.
heat source will result in an increase in its body temperature and drop
in resistance this type action (internal or external) lends itself well to
control mechanism.
SYMBOL:
MODEL GRAPH:
R
(-cm)
T (deg)
3 – 60.
Thermistors are used measure temperature, flow pressure, liquid
level, voltage or power level, vacuum, composition of gases and
thermal conductivity and also in compensation network.
RESULT:
Thus the Characteristics of thermistor was studied.
Ex.No.7a
SINGLE PHASE HALF WAVE RECTIFIER
AIM:
To construct a Half wave rectifier using diode and to draw its
performance characteristics.
FORMULAE:
WITHOUT FILTER:
(i) Vrms = Vm / 2
(ii) Vdc = Vm /
(iii) Ripple Factor= (Vrms / Vdc)2 – 1
(iv) Efficiency = (Vdc / Vrms)2 x 100
WITH FILTER:
’2 2
(i) Vrms = (Vrms + Vdc )
(ii) Vrms’ = Vrpp / (3 x 2)
(iii) Vdc = Vm – V rpp /2
(iv) Ripple Factor= Vrms’/ Vdc
PROCEDURE:
WITHOUT FILTER:
13. Give the connections as per the circuit diagram.
14. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
15. Take the rectifier output across the Load.
16. Plot its performance graph.
WITH FILTER:
1. Give the connections as per the circuit diagram.
14. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
15. Connect the Capacitor across the Load.
16. Take the rectifier output across the Load.
17. Plot its performance graph.
CIRCUIT DIAGRAM:
1 Transformer
230 V / 6V
1N 4007
1K
1, 230V, 100F
CRO
50Hz
AC supply
TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms Vdc Ripple factor Efficiency
WITH FILTER:
Vrms Vrpp Vdc Ripple factor Efficiency
MODEL GRAPH:
Vin
(Volts)
t (ms)
Vo
(Volts) Without
t (ms)
Vo
(Volts) With
t (ms)
RESULT:
Thus the performance characteristics of 1 Half wave rectifier was obtained.
Ex.No.7b
SINGLE PHASE FULL WAVE RECTIFIER
AIM:
To construct a Full wave rectifier using diode and to draw its
performance characteristics.
FORMULAE:
WITHOUT FILTER:
(i) Vrms = Vm / 2
(ii) Vdc = 2Vm /
(iii) Ripple Factor= (Vrms / Vdc)2 – 1
(iv) Efficiency = (Vdc / Vrms)2 x 100
WITH FILTER:
(i) Vrms = Vrpp /(2* 3)
(ii) Vdc = Vm – V rpp
PROCEDURE:
WITHOUT FILTER:
13. Give the connections as per the circuit diagram.
14. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
15. Take the rectifier output across the Load.
16. Plot its performance graph.
WITH FILTER:
1. Give the connections as per the circuit diagram.
14. Give 230v, 50HZ I/P to the step down TFR where secondary
connected to the Rectifier I/P.
15. Connect the Capacitor across the Load.
16. Take the rectifier output across the Load.
17. Plot its performance graph.
CIRCUIT DIAGRAM:
1 Transformer 1N 4007
230 V / 6V
100F
1K
1, 230V,
CRO
50Hz
AC supply
1N 4007
TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms Vdc Ripple factor Efficiency
WITH FILTER:
Vrms Vrpp Vdc Ripple factor Efficiency
MODEL GRAPH :
Vin
(Volts)
t (ms)
Vo
(Volts) Without Filter
t (ms)
Vo
(Volts) With Filter
t (ms)
Ex.No.8
DIFFERENTIAL AMPLIFIER
AIM:
To construct a Differential amplifier in Common mode & Differential mode
configuration and to find common mode rejection ratio.
THEORY:
The Differential amplifier circuit is an extremely popular
connection used in IC units. The circuit has separate inputs , two
separate outputs and emitters are connected together. If the same
input is applied to both inputs, the operation is called common mode.
In double ended operation two input signals are applied , the difference
of the inputs resulting in outputs from both collectors due to the
difference of the signals applied to both the inputs. The main feature of
the differential amplifier is the very large gain when opposite signals
are applied to inputs as compared to small signal resulting from
common input. The ratio of this difference gain to the common gain is
called common mode rejection ratio.
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CIRCUIT DIAGRAM:
DIFFERENTIAL MODE:
3.9K 3.9K
Vo1Vo2
V1
12V V2
13V
3.3 K
-9V
9V
COMMON MODE:
3.9K 3.9K
Vo1 Vo2
V2
13V
3.3
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K
-9V
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PROCEDURE:
DIFFERENTIAL MODE:
13. Connect the circuit as per the circuit diagram.
14. Set V1 = 50mv and V2 =55mv using the signal generator.
15. Find the corresponding output voltages across V01 & V02 using CRO
16. Calculate common mode rejection ratio using the given formula.
COMMON MODE:
13. Connect the circuit as per the circuit diagram.
14. Set V1 = 50mv using the signal generator.
15. Find the output voltage across Vo using multimeter.
16. Calculte common mode rejection ratio using the given formula.
CALCULATION:
Common mode rejection ratio(CMRR) =
Ad / Ac Ad = Differential mode gain
Ac = Common mode
gain Where Ad =
Vo /Vd
Vo = Output voltage measured across
CRO Vd = V 1 – V2 , V 1 , V2 – input
voltage applied. Ac = Vo /Vc
Vc = (V 1 + V2 )/2
DIFFERENTIAL MODE: Ad=Vo/Vd =
V1
=
V2
=
Output voltage
=
Vd= V1-V2
=
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COMMON MODE: Output voltage =
Input voltage V1=V2 =
Vc=(V1+V2)/2 =
=
Exp. No: 12
PASSIVE FILTERS
Aim:
To attenuate unwanted frequency components from input signal by using resistor
and capacitor.
Apparatus required:
Name of the apparatus Range Type Quantity
S.No
1. Signal Generator 01
2. Resistor 01
3. Capacitor Ceramic 01
4. CRO 01
5. Breadboard 01
Theory:
A filter is an AC circuit that separates some frequencies from other in
within mixed – frequency signals. Audio equalizers and crossover networks are
two well-known applications of filter circuits. A Bode plot is a graph plotting
waveform amplitude or phase on one axis and frequency on the other.
A low-pass filter allows for easy passage of low-frequency signals from
source to load, and difficult passage of high-frequency signals. Capacitor low-pass
filters insert a resistor in series and a capacitor in parallel with the load as shown
in the circuit diagram. The former filter design tries to “block” the unwanted
frequency signal while the latter tries to short it out.
The cutoff frequency for a low-pass filter is that frequency at which the
output (load) voltage equals 70.7% of the input (Source) voltage. Above the cutoff
frequency, the output voltage is lower than 70.7% of the input, and vice-versa. See
the circuit diagram
1
Fcutoff = ----------
2RC
A high-pass filter allows for easy passage of high-frequency signals from source to
load, and difficult passage of low-frequency signals. Capacitor high-pass filters
insert a capacitor in series with the load as shown in the circuit diagram. The
former filter design tries to “brick” the unwanted frequency signal while the latter
tries to short it out.
The cutoff frequency for a high-pass filter is that frequency at which the
output (load) voltage equals 70.7% of the input (source) voltage. Above the cutoff
frequency, the output voltage is greater than 70.7% of the input, and vice-versa.
1
Fcutoff = ----------
2RC
A band – pass filter works to screen out frequencies that are too low or too
high, giving easy passage only to frequencies within a certain range. Stacking a
low-pass filter on the end of a high-pass filter, or vice-versa can make band-pass
filters. Refer the circuit diagrams
Placing a low-pass filter in parallel with a high-pass filter can make band-
stop filters. Commonly, both the low-pass and high-pass filter sections are of the
“T” configuration giving the name “Twin-T” to the band-stop combination. Refer
the fig.7.7, 7.8a and 7.8b.
Passes low frequencies
Low-pass filter
Signal Signal
Input Output
High-pass filter
Fig. 7.8a
The frequency of maximum attenuation is called the notch
frequency.
Procedure:
19. Give the connections as per circuit diagrams.
20. Switch on the main.
21. Change the frequency from minimum and find the output
voltage by using CRO.
22. Draw the graph.
23. Verify the cut off frequency.
24. Switch off the main.
Result:
Thus we analyze passive filter and various waveforms are noted
Exp. No :
10
STUDY OF CRO AND
POWER FACTOR MEASUREMENT USING CRO
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Aim:
To study cathode Ray Oscilloscope (CRO) and measurement of power factor using
CRO.
Apparatus required:
Name of the apparatus Range Type Quantity
S.No
1. Resistance Box 1
2. Capacitance Box 1
3. Inductance Box 1
4. Function Generator 1
5. Bread board 1
Theory:
The cathode ray oscilloscope is the most versatile measuring instrument
available. We can measure following parameters using the CRO:
13. AC or DC voltage.
14. Time (t=1/f).
15. Phase relationship
16. Waveform calculation: Rise time; fall time; on time; off-time
Distortion, etc.
We can also measure non-electrical physical quantities like pressure, strain,
temperature, acceleration, etc., by converting into electrical quantities using
a transducer.
Major blocks:
19. Cathode ray tube (CRT)
20. Vertical amplifier
21. Horizontal amplifier
22. Sweep generator
16. The cathode ray tube is the heart of CRO. The CRT is enclosed in an
evacuated glass envelope to permit the electron beam to traverse in the
tube easily. The main functional units of CRO are as follows.
Electron gun assembly
Deflection plate unit
Screen.
17. Vertical Amplifier is the main factor in determining the bandwidth and
sensitivity of an oscilloscope. Vertical sensitivity is a measure of how
much the electron beam will be deflected for a specified input signal.
On the front panel of the oscilloscope, one can see a knob attached to a
rotary switch labeled volts/division. The rotary switch is electrically
connected to the input attenuation network. The setting of the rotary
switch indicates what amplitude signal is required to deflect the beam
vertically by one division.
18. Horizontal amplifier Under normal mode of operation, the horizontal
amplifier will amplify the sweep generator input. When the CRO is
being used in the X-Y mode, the horizontal amplifier will amplify the
signal applied to the horizontal input terminal. Although the vertical
amplifier mush be able to faithfully reproduce low-amplitude and high
frequency signal with fast rise-time, the horizontal amplifier is only
required to provide a faithful reproduction of the sweep signal which
has a relatively high amplitude and slow rise time.
19. Sweep generator and Trigger circuit These two units form the Signal
Synchronization unit of the CRO.
20. Associated Power Supply: The input signal may come from an
external source when the trigger selector switch is set to EXT or from
proportional to the deflecting voltage, the CRT may be used as a linear measuring
device. The voltage being measured is applied to the vertical plates through an
iterative network, whose propagation time corresponds to the velocity of electrons,
thereby synchronizing the voltage applied to the vertical plate with the velocity of
the beam.
Synchronization of input signal: The sweep generator produces a saw tooth
waveform, which is used to synchronize the applied voltage to obtain a stationary-
applied signal. This requires that the time base be operated at a submultiples
frequency of the signal under measurement. If synchronization is not done, the
pattern is not stationary, but appears to drift across the screen in a random fashion.
Internal synchronization This trigger is obtained from the time base generator to
synchronize the signal.
External synchronization An external trigger source can also be used to
synchronize the signal being measured.
Auto Triggering Mode The time base used in this case in a self-oscillating
condition, i.e., it gives an output even in the absence of any Y-input. The
advantage of this mode is that the beam is visible on the screen under all
conditions, including the zero input. When the input exceeds a certain magnitude
then the internal free running oscillator locks on to the frequency.
Precautions:
7. The ammeter is connected using thick wires.
8. While reversing ammeter polarity, see to it that the capacitor is not
discharged.
Observation:
Sl.No Time Voltage Current
Unit (Sec) (Volts) (Amps)
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