TPS62130, TPS62130A

TPS62131, TPS62132, TPS62133

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3-17V 3A Step-Down Converter in 3x3 QFN Package

Check for Samples: TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133

1FEATURES DESCRIPTION
• DCS-Control Topology TM The TPS6213X family is an easy to use synchronous
step down DC-DC converter optimized for
• Input Voltage Range: 3 to 17V applications with high power density. A high switching
• Up to 3A Output Current frequency of typically 2.5MHz allows the use of small
• Adjustable Output Voltage from 0.9 to 6V inductors and provides fast transient response as well
as high output voltage accuracy by utilization of the
• Pin-Selectable Output Voltage (nominal, + 5%)
DCS-Control™ topology.
• Programmable Soft Start and Tracking
With its wide operating input voltage range of 3V to
• Seamless Power Save Mode Transition 17V, the devices are ideally suited for systems
• Quiescent Current of 17µA (typ.) powered from either a Li-Ion or other batteries as well
• Selectable Operating Frequency as from 12V intermediate power rails. It supports up
to 3A continuous output current at output voltages
• Power Good Output
between 0.9V and 6V (with 100% duty cycle mode).
• 100% Duty Cycle Mode
The output voltage startup ramp is controlled by the
• Short Circuit Protection soft-start pin, which allows operation as either a
• Over Temperature Protection standalone power supply or in tracking configurations.
• Available in a 3 × 3 mm, QFN-16 Package Power sequencing is also possible by configuring the
Enable and open-drain Power Good pins.
APPLICATIONS In Power Save Mode, the devices show quiescent
• Standard 12V Rail Supplies current of about 17μA from VIN. Power Save Mode,
entered automatically and seamlessly if load is small,
• POL Supply from Single or Multiple Li-Ion maintains high efficiency over the entire load range.
Battery In Shutdown Mode, the device is turned off and
• Solid-State Disk Drives shutdown current consumption is less than 2μA.
• Embedded Systems The device, available in adjustable and fixed output
• LDO replacement voltage versions, is packaged in a 16-pin QFN
• Mobile PC's, Tablet, Modems, Cameras package measuring 3 × 3 mm (RGT).

spacing

(3 .. 17)V 1 / 2.2 µH 1.8V / 3A

PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 22uF
TPS62131
SS/TR FB
3.3nF
DEF AGND

FSW PGND

Figure 1. Typical Application and Efficiency

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS62130, TPS62130A
TPS62131, TPS62132, TPS62133
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION (1)

TA OUTPUT VOLTAGE PART NUMBER (2) PACKAGE ORDERING PACKAGE
MARKING
adjustable TPS62130 TPS62130RGT PTSI
adjustable TPS62130A (3) TPS62130ARGT PA6I
-40°C to 85°C 1.8 V TPS62131 16-Pin QFN TPS62131RGT QVX
3.3 V TPS62132 TPS62132RGT QVY
5.0 V TPS62133 TPS62133RGT QVZ

(1) For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
(2) Contact the factory to check availability of other fixed output voltage versions.
(3) While TPS6213X has PG=High Z, TPS62130A features PG=Low, when device is in shutdown through EN, UVLO or Thermal Shutdown.

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
AVIN, PVIN –0.3 20
V
EN, SS/TR –0.3 VIN+0.3
Pin voltage range (2)
SW –0.3 VIN+0.3 V
DEF, FSW, FB, PG, VOS –0.3 7 V
Power Good sink current PG 10 mA
Operating junction temperature range, TJ –40 125
Temperature range °C
Storage temperature range, Tstg –65 150
HBM Human body model 2 kV
ESD rating (3)
CDM Charge device model 0.5 kV

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION
TPS6213X
THERMAL METRIC (1) UNITS
RGT 16 PINS
θJA Junction-to-ambient thermal resistance 29.1
θJC(TOP) Junction-to-case(top) thermal resistance 15
θJB Junction-to-board thermal resistance 11
°C/W
ψJT Junction-to-top characterization parameter 0.5
ψJB Junction-to-board characterization parameter 10
θJC(BOTTOM) Junction-to-case(bottom) thermal resistance 3.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
spacer

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
Supply Voltage, VIN (at AVIN and PVIN) 3 17 V
Operating free air temperature, TA –40 85 °C
Operating junction temperature, TJ –40 125 °C

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ELECTRICAL CHARACTERISTICS
over free-air temperature range (TA=-40°C to +85°C), typical values at VIN=12V and TA=25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range (1) 3 17 V
IQ Operating quiescent current EN=High, IOUT=0mA, device not switching 17 25 µA
ISD Shutdown current (2) EN=Low 1.5 4 µA
VUVLO Falling Input Voltage 2.6 2.7 2.8 V
Undervoltage lockout threshold
Hysteresis 200 mV
TSD Thermal shutdown temperature 160
°C
Thermal shutdown hysteresis 20
CONTROL (EN, DEF, FSW, SS/TR, PG)
High level input threshold voltage (EN,
VH 0.9 V
DEF, FSW)
VL Low level input threshold voltage (EN,
0.3 V
DEF, FSW)
ILKG Input leakage current (EN, DEF, FSW) EN=VIN or GND; DEF, FSW=VOUT or GND 0.01 1 µA
Rising (%VOUT) 92 95 98
VTH_PG Power good threshold voltage %
Falling (%VOUT) 87 90 94
VOL_PG Power good output low IPG=–2mA 0.07 0.3 V
ILKG_PG Input leakage current (PG) VPG=1.8V 1 400 nA
ISS/TR SS/TR pin source current 2.3 2.5 2.7 µA
POWER SWITCH
VIN≥6V 90 170
High-side MOSFET ON-resistance mΩ
VIN=3V 120
RDS(ON)
VIN≥6V 40 70
Low-side MOSFET ON-resistance mΩ
VIN=3V 50
ILIMF High-side MOSFET forward current limit (3) VIN =12V, TA= 25°C 3.6 4.2 4.9 A
OUTPUT
VREF Internal reference voltage (4) 0.8 V
ILKG_FB Input leakage current (FB) TPS62130, VFB=0.8V 1 100 nA
Output voltage range (TPS62130) VIN ≥ VOUT 0.9 6.0 V
DEF (Output voltage programming) DEF=0 (GND) VOUT
DEF=1 (VOUT) VOUT+5%
PWM mode operation, VIN ≥ VOUT +1V –1.8 1.8

VOUT (5) PWM mode operation, VIN ≥ VOUT +1V,

Initial output voltage accuracy –1.5 1.6 %
TA = –10°C to 85°C
Power Save Mode operation, COUT=22µF –2.3 2.8
Load regulation (6) VIN=12V, VOUT=3.3V, PWM mode operation 0.05 %/A
3V ≤ VIN ≤ 17V, VOUT=3.3V, IOUT= 1A, PWM 0.02 %/V
Line regulation (6)
mode operation

(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
(2) Current into AVIN+PVIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short
Circuit Protection section).
(4) This is the voltage regulated at the FB pin.
(5) This is the accuracy provided by the device itself (line and load regulation effects are not included). For the fixed voltage versions the
(internal) resistive divider is included.
(6) Line and load regulation depend on external component selection and layout (see Figure 17 and Figure 18).

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DEVICE INFORMATION

RGT PACKAGE
(TOP VIEW)

PGND

PGND

VOS

EN
16 15 14 13

SW 1 12 PVIN

SW 2 Exposed 11 PVIN
Thermal Pad
SW 3 10 AVIN

PG 4 9 SS/TR

5 6 7 8

FSW

DEF
FB

AGND

Terminal Functions
PIN (1)
I/O DESCRIPTION
NAME NO.
SW 1,2,3 O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
PG 4 O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor)
FB 5 I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended to
connect FB to AGND on fixed output voltage versions for improved thermal performance.
AGND 6 Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
FSW 7 I Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz (2) for typical operation) (3)
DEF 8 I Output Voltage Scaling (Low = nominal, High = nominal + 5%) (3)
Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise
SS/TR 9 I
time. It can be used for tracking and sequencing.
AVIN 10 I Supply voltage for control circuitry. Connect to same source as PVIN.
PVIN 11,12 I Supply voltage for power stage. Connect to same source as AVIN.
EN 13 I Enable input (High = enabled, Low = disabled) (3)
VOS 14 I Output voltage sense pin and connection for the control loop circuitry.
PGND 15,16 Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Exposed Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane (4). Must be soldered to
Thermal Pad achieve appropriate power dissipation and mechanical reliability.

(1) For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections.
(2) Connect FSW to VOUT or PG in this case.
(3) An internal pull-down resistor keeps logic level low, if pin is floating.
(4) See Figure 41.

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FUNCTIONAL BLOCK DIAGRAM

PG AVIN PVIN PVIN

Soft Thermal
UVLO PG control
start Shtdwn
HS lim

comp

EN*
SW
SS/TR
power gate
control logic SW
control drive
DEF*
SW
FSW*

comp

LS lim

VOS direct control

& ramp
compensation

_
FB comparator timer tON
error
amplifier
+
DCS - ControlTM

*
This pin is connected to a pull down resistor internally AGND PGND PGND
(see Detailed Description section).

Figure 2. TPS62130 (adjustable output voltage)

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PG AVIN PVIN PVIN

Soft Thermal
UVLO PG control
start Shtdwn
HS lim

comp

EN*
SW
SS/TR
power gate
control logic SW
control drive
*
DEF
SW
FSW*

comp

LS lim

VOS direct control

& ramp
compensation

_
FB* comparator timer tON
error
amplifier
+
DCS - ControlTM

*
This pin is connected to a pull down resistor internally AGND PGND PGND
(see Detailed Description section).

Figure 3. TPS62131/2/3 (fixed output voltage)

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PARAMETER MEASUREMENT INFORMATION

List of Components
REFERENCE DESCRIPTION MANUFACTURER
IC 17V, 3A Step-Down Converter, QFN TPS62130RGT, Texas Instruments
L1 2.2µH, 0.165 x 0.165 in XFL4020-222MEB, Coilcraft
Cin 10µF, 25V, Ceramic Standard
Cout 22µF, 6.3V, Ceramic Standard
Cs 3300pF, 25V, Ceramic
R1 depending on Vout
R2 depending on Vout
R3 100kΩ, Chip, 0603, 1/16W, 1% Standard

VIN L1 VOUT
PVIN SW

AVIN VOS R3

CIN EN FB
PG R1 COUT
TPS62130
SS/TR PG
FB

CSS DEF AGND R2

FSW PGND

Figure 4. Measurement Setup

TYPICAL CHARACTERISTICS
Table of Graphs
DESCRIPTION FIGURE
Efficiency vs output Current, vs Input Voltage 5–16
vs Output Current (Load regulation), vs Input Voltage (Line
Output voltage 17, 18
regulation)
vs Input Voltage 19
Switching Frequency
vs Output Current 20
Quiescent Current vs Input Voltage 21
Shutdown Current vs Input Voltage 22
Power FET RDS(on) vs Input Voltage (High-Side, Low-Side) 23, 24
Output Voltage Ripple vs Output Current 25
Maximum Output Current vs Input Voltage 26
Power Supply Rejection Ratio
vs Frequency 27, 28
(PSSR)
PWM-PSM-PWM Mode Transition 29
Load Transient Response 30–32
Waveforms Startup 33, 34
Typical PWM Mode Operation 35
Typical Power Save Mode Operation 36
vs Load Current 37
Maximum Ambient Temperature
vs Power Dissipation 38

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EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
100.0 100.0
90.0 90.0
80.0 80.0
VIN=17V
70.0 VIN=12V 70.0
Efficiency (%)

Efficiency (%)
60.0 60.0 IOUT=10mA IOUT=1A
50.0 50.0 IOUT=1mA IOUT=100mA
40.0 40.0
30.0 30.0
20.0 VOUT=5.0V 20.0 VOUT=5.0V
L=2.2uH (XFL4020) L=2.2uH (XFL4020)
10.0 10.0 Cout=22uF
Cout=22uF
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) G001 Input Voltage (V) G001

Figure 5. Efficiency with 1.25MHz, Vout=5V Figure 6. Efficiency with 1.25MHz, Vout=5V

EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
100.0 100.0
90.0 90.0
80.0 80.0
70.0 70.0
Efficiency (%)

Efficiency (%)

60.0 VIN=17V 60.0 IOUT=10mA IOUT=1A

50.0 VIN=12V 50.0 IOUT=1mA IOUT=100mA
40.0 40.0
30.0 30.0
20.0 VOUT=5.0V 20.0 VOUT=5.0V
L=2.2uH (XFL4020) L=2.2uH (XFL4020)
10.0 10.0 Cout=22uF
Cout=22uF
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) G001 Input Voltage (V) G001

Figure 7. Efficiency with 2.5MHz, Vout=5V Figure 8. Efficiency with 2.5MHz, Vout=5V

EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
100.0 100.0
90.0 90.0
80.0 80.0
70.0 VIN=12V VIN=17V 70.0
Efficiency (%)

Efficiency (%)

60.0 VIN=5V 60.0 IOUT=1A IOUT=100mA IOUT=10mA IOUT=1mA

50.0 50.0
40.0 40.0
30.0 30.0
20.0 20.0 VOUT=3.3V
VOUT=3.3V
L=2.2uH (XFL4020)
10.0 L=2.2uH (XFL4020) 10.0 Cout=22uF
Cout=22uF
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) G001 Input Voltage (V) G001

Figure 9. Efficiency with 1.25MHz, Vout=3.3V Figure 10. Efficiency with 1.25MHz, Vout=3.3V

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EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
100.0 100.0
90.0 90.0
80.0 80.0
70.0 70.0
Efficiency (%)

Efficiency (%)
60.0 VIN=12V VIN=17V 60.0 IOUT=100mA IOUT=1mA
50.0 VIN=5V 50.0 IOUT=10mA IOUT=1A
40.0 40.0
30.0 30.0
20.0 20.0 VOUT=3.3V
VOUT=3.3V
L=2.2uH (XFL4020)
10.0 L=2.2uH (XFL4020) 10.0 Cout=22uF
Cout=22uF
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) G001 Input Voltage (V) G001

Figure 11. Efficiency with 2.5MHz, Vout=3.3V Figure 12. Efficiency with 2.5MHz, Vout=3.3V

EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
100.0 100.0
90.0 90.0
80.0 80.0
70.0 70.0
Efficiency (%)

Efficiency (%)
VIN=12V VIN=17V IOUT=1A
60.0 60.0 IOUT=100mA
IOUT=10mA
50.0 VIN=5V 50.0 IOUT=1mA
40.0 40.0
30.0 30.0
20.0 20.0 VOUT=1.8V
VOUT=1.8V
L=2.2uH (XFL4020)
10.0 L=2.2uH (XFL4020) 10.0 Cout=22uF
Cout=22uF
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) G001 Input Voltage (V) G001

Figure 13. Efficiency with 1.25MHz, Vout=1.8V Figure 14. Efficiency with 1.25MHz, Vout=1.8V

EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
100.0 100.0
90.0 90.0
80.0 80.0
70.0 70.0
Efficiency (%)

Efficiency (%)

60.0 VIN=12V VIN=17V 60.0 IOUT=1A

50.0 50.0 IOUT=100mA
VIN=5V IOUT=10mA
40.0 40.0 IOUT=1mA
30.0 30.0
20.0 20.0 VOUT=0.9V
VOUT=0.9V
L=2.2uH (XFL4020)
10.0 L=2.2uH (XFL4020) 10.0 Cout=22uF
Cout=22uF
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) G001 Input Voltage (V) G001

Figure 15. Efficiency with 1.25MHz, Vout=0.9V Figure 16. Efficiency with 1.25MHz, Vout=0.9V

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OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs
OUTPUT CURRENT INPUT VOLTAGE
3.40 3.40

VIN=17V IOUT=10mA
IOUT=1mA
3.35 3.35
Output Voltage (V)

Output Voltage (V)

VIN=12V

3.30 3.30

VIN=5V IOUT=1A IOUT=100mA

3.25 3.25
VOUT=3.3V VOUT=3.3V
L=2.2uH (XFL4020) L=2.2uH (XFL4020)
Cout=22uF Cout=22uF
3.20 3.20
0.0001 0.001 0.01 0.1 1 10 4 7 10 13 16
Output Current (A) G001 Input Voltage (V) G001

Figure 17. Output Voltage Accuracy (Load Regulation) Figure 18. Output Voltage Accuracy (Line Regulation)

SWITCHING FREQUENCY SWITCHING FREQUENCY

vs vs
INPUT VOLTAGE OUTPUT CURRENT
4 4

3.5 3.5
IOUT=2A IOUT=3A
Switching Frequency (MHz)

3 Switching Frequency (MHz) 3

2.5 2.5

2 2
IOUT=0.5A IOUT=1A
1.5 1.5

1 1
VOUT=3.3V VIN=12V, VOUT=3.3V
0.5 L=2.2uH (XFL4020) 0.5 L=2.2uH (XFL4020)
Cout=22uF FSW=Low
0 0
4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3
Input Voltage (V) G000 Output Current (A) G000

Figure 19. Switching Frequency Figure 20. Switching Frequency

INPUT CURRENT INPUT CURRENT

vs vs
INPUT VOLTAGE INPUT VOLTAGE
50.0 5.0
45.0 4.5
40.0 4.0
Input Current (µA)

Input Current (µA)

35.0 3.5
85°C
30.0 3.0
25°C 85°C
25.0 2.5
20.0 2.0
15.0 1.5
10.0 1.0 −40°C 25°C
5.0 −40°C 0.5
0.0 0.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0 0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
Input Voltage (V) G001 Input Voltage (V) G001

Figure 21. Quiescent Current Figure 22. Shutdown Current

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STATIC DRAIN-SOURCE-RESISTANCE (RDSon) STATIC DRAIN-SOURCE-RESISTANCE (RDSon)

vs vs
INPUT VOLTAGE INPUT VOLTAGE
200.0 100.0
180.0
160.0 125°C 80.0
RDSon High−Side (mΩ)

RDSon Low−Side (mΩ)

140.0 125°C
120.0 85°C 60.0 85°C
100.0 25°C
25°C
80.0 40.0
60.0 −10°C
−10°C
40.0 −40°C 20.0 −40°C
20.0
0.0 0.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0 0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
Input Voltage (V) G001 Input Voltage (V) G001

Figure 23. High-Side Switch Resistance Figure 24. Low-Side Switch Resistance

OUTPUT VOLTAGE OUTPUT CURRENT

vs vs
OUTPUT CURRENT INPUT VOLTAGE
0.05 6
5.5
VOUT=3.3V,
L=2.2uH (XFL4020) 5
0.04 −40°C
Output Voltage Ripple (V)

Cout=22uF Output Current (A) 4.5

4
0.03 3.5
VIN=17V VIN=5V
3
2.5 25°C
0.02
85°C
2
1.5
0.01 VOUT=3.3V
1
0.5 L=2.2uH (XFL4020)
VIN=12V
Cout=22uF
0 0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) G000
Input Voltage (V) G000

Figure 25. Output Voltage Ripple Figure 26. Maximum Output Current

POWER SUPPLY REJECTION RATIO POWER SUPPLY REJECTION RATIO

vs vs
FREQUENCY FREQUENCY
100 100
90 VIN=5V 90 VIN=12V
80 80 VIN=5V
VIN=12V
70 VIN=17V 70 VIN=17V
PSRR (dB)

PSRR (dB)

60 60
50 50
40 40
30 30
20 VOUT=3.3V, IOUT=1A 20 VOUT=3.3V, IOUT=0.1A
10 L=2.2uH (XFL4020) 10 L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF Cin=10uF, Cout=22uF
0 0
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
Frequency (Hz) G000
Frequency (Hz) G000

Figure 27. Power Supply Rejection Ratio, fSW=2.5MHz Figure 28. Power Supply Rejection Ratio, fSW=2.5MHz

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OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs
TIME TIME

Figure 29. PWM-PSM-Transition (VIN=12V, VOUT=3.3V with Figure 30. Load Transient Response (IOUT= 0.5 to 3 to 0.5 A,
50mV/div) VIN=12V, VOUT=3.3V)

OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs
TIME TIME

Figure 31. Load Transient Response of Figure 30, rising Figure 32. Load Transient Response of Figure 30, falling
edge edge

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OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs
TIME TIME

Figure 33. Startup into 100mA (VIN=12V, VOUT=3.3V) Figure 34. Startup into 3A (VIN=12V, VOUT=3.3V)

PWM SIGNALS POWER SAVE MODE SIGNALS

vs vs
TIME TIME

Figure 35. Typical Operation in PWM Mode (IOUT=1A) Figure 36. Typical Operation in Power Save Mode
(IOUT=10mA)

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AMBIENT TEMPERATURE AMBIENT TEMPERATURE

vs vs
OUTPUT CURRENT OUTPUT POWER
125 125

115 115
Free−Air Temperature (°C)

Free−Air Temperature (°C)

105 105

95 95

85 85

75 TPS62130 EVM 75 TPS62130 EVM

L=2.2uH (XFL4020) L=2.2uH(XFL4020)
65 VIN=12V, VOUT=3.3V 65 VIN=12V, VOUT=3.3V

55 55
0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12
Output Current (A) G000 Output Power (W) G000

Figure 37. Maximum Ambient Temperature (fSW=2.5MHz) Figure 38. Maximum Ambient Temperature (fSW=2.5MHz)

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DETAILED DESCRIPTION

Device Operation
The TPS6213X synchronous switched mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage.
This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage.
It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage.
Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 3
external components. An internal current limit supports nominal output currents of up to 3A.
The TPS6213X family offers both excellent DC voltage and superior load transient regulation, combined with
very low output voltage ripple, minimizing interference with RF circuits.

Pulse Width Modulation (PWM) Operation

The TPS6213X operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25MHz, selectable with the FSW pin. The frequency variation in PWM is
controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output
current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device
enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output
current becomes smaller than half the inductor's ripple current.

Power Save Mode Operation

The TPS6213X's built in Power Save Mode will be entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
TPS6213X includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated as:
VOUT
t ON = × 400ns
V IN
(1)
For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using tON, the typical
peak inductor current in Power Save Mode can be approximated by:
(V IN - VOUT )
I LPSM ( peak ) = × t ON
L (2)
When VIN decreases to typically 15% above VOUT, the TPS6213X won't enter Power Save Mode, regardless of
the load current. The device maintains output regulation in PWM mode.

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100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal set
point. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL )
(3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RL is the DC resistance of the inductor used.

Enable / Shutdown (EN)

When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a
shutdown current of typically 1.5µA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must
be set externally to High or Low. An internal pull-down resistor of about 400kΩ is connected and keeps EN logic
low, if Low is set initially and then the pin gets floating. It is disconnected if the pin is set High.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.

Soft Start / Tracking (SS/TR)

The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-
impedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR
pin. See Figure 33 and Figure 34 for typical startup operation.
Connecting SS/TR directly to AVIN provides fastest startup behavior. The TPS6213X can start into a pre-biased
output. During monotonic pre-biased startup, both the power MOSFETs are not allowed to turn on until the
device's internal ramp sets an output voltage above the pre-bias voltage. As long as the output is below about
0.5V a reduced current limit of typically 1.6A is set internally. If the device is set to shutdown (EN=GND),
undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low
level. Returning from those states causes a new startup sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage
in both directions up and down (see APPLICATION INFORMATION).

Current Limit And Short Circuit Protection

The TPS6213X devices are protected against heavy load and short circuit events. If a short circuit is detected
(VOUT drops below 0.5V), the current limit is reduced to 1.6A typically. If the output voltage rises above 0.5V,
the device will run in normal operation again. At heavy loads, the current limit determines the maximum output
current. If the current limit is reached, the high-side FET will be turned off. Avoiding shoot through current, the
low-side FET will be switched on to sink the inductor current. The high-side FET will turn on again, only if the
current in the low-side FET has decreased below the low side current limit threshold.
The output current of the device is limited by the current limit (see ELECTRICAL CHARACTERISTICS). Due to
internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic
current limit can be calculated as follows:

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VL
I peak ( typ ) = I LIMF + × t PD
L (4)
where
ILIMF is the static current limit, specified in the ELECTRICAL CHARACTERISTICS,
L is the inductor value,
VL is the voltage across the inductor (VIN - VOUT) and
tPD is the internal propagation delay.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch peak current can be calculated as follows:

I peak (typ ) = I LIMF +

(VIN - VOUT )× 30ns
L (5)

Power Good (PG)

The TPS6213X has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and
maintain its specified logic low level. With TPS62130 it is high impedance when the device is turned off due to
EN, UVLO or thermal shutdown. TPS62130A features PG=Low in this case and can be used to actively
discharge Vout (see Figure 51). VIN must remain present for the PG pin to stay Low.

Pin-Selectable Output Voltage (DEF)

The output voltage of the TPS6213X devices can be increased by 5% above the nominal voltage by setting the
DEF pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal
voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed
information on voltage margining using TPS6213X can be found in SLVA489. A pull down resistor of about
400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating
after initially set to Low. The resistor is disconnected if the pin is set High.

Frequency Selection (FSW)

To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by
connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output
current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching
frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally
connected to the pin, acting the same way as at the DEF Pin (see above).

Under Voltage Lockout (UVLO)

If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV.

Thermal Shutdown
The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
(1) Maximum allowed voltage is 7V. Therefore it's recommended to connect it to VOUT or PG, not VIN.
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APPLICATION INFORMATION
The following information is intended to be a guideline through the individual power supply design process.

Programming The Output Voltage

While the output voltage of the TPS62130 is adjustable, the TPS62131/2/3 are programmed to fixed output
voltages. For fixed output versions, the FB pin is pulled down internally and may be left floating. It is
recommended to connect to AGND to improve thermal resistance. The adjustable version can be programmed
for output voltages from 0.9V to 6V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is
regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider from
Equation 6 (see Figure 4). It is recommended to choose resistor values which allow a current of at least 2uA,
meaning the value of R2 shouldn't exceed 400kΩ. Lower resistor values are recommended for highest accuracy
and most robust design. For applications requiring lowest current consumption, the use of fixed output voltage
versions is recommended.
æV ö
R1 = R 2 çç OUT - 1÷÷
è V REF ø (6)
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4V.

External Component Selection

The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS6213X is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered together, creating a double pole, responsible for the corner
frequency of the converter (see Output Filter And Loop Stability). Table 1 can be used to simplify the output filter
component selection.

Table 1. Recommended LC Output Filter Combinations (1)

4.7µF 10µF 22µF 47µF 100µF 200µF 400µF
0.47µH
1µH √ √ √ √
(2)
2.2µH √ √ √ √ √
3.3µH √ √ √ √
4.7µH

(1) The values in the table are nominal values.

(2) This LC combination is the standard value and recommended for most applications.

spacing
The TPS6213X can be run with an inductor as low as 1µH. FSW should be set Low in this case. However, for
applications running with the low frequency setting (FSW=High) or with low input voltages, 2.2µH is
recommended. More detailed information on further LC combinations can be found in SLVA463.

Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
spacing
DI L(max)
I L(max) = I OUT (max) +
2 (7)

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æ V ö
ç 1 - OUT ÷
ç V IN (max) ÷
DI L(max) = VOUT ×ç ÷
L ×f
ç (min) SW ÷
ç ÷
è ø (8)
where
IL(max) is the maximum inductor current,
ΔIL is the Peak to Peak Inductor Ripple Current,
L(min) is the minimum effective inductor value and
fSW is the actual PWM Switching Frequency.
spacing
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS6213X and are recommended for use:

Table 2. List of Inductors

Type Inductance [µH] Current [A] (1) Dimensions [LxBxH] MANUFACTURER
mm
XFL4020-102ME_ 1.0 µH, ±20% 4.7 4 x 4 x 2.1 Coilcraft
XFL4020-152ME_ 1.5 µH, ±20% 4.2 4 x 4 x 2.1 Coilcraft
XFL4020-222ME_ 2.2 µH, ±20% 3.8 4 x 4 x 2.1 Coilcraft
IHLP1212BZ-11 1.0 µH, ±20% 4.5 3 x 3.6 x 2 Vishay
IHLP1212BZ-11 2.2 µH, ±20% 3.0 3 x 3.6 x 2 Vishay
SRP4020-3R3M 3.3µH, ±20% 3.3 4.8 x 4 x 2 Bourns
VLC5045T-3R3N 3.3µH, ±30% 4.0 5 x 5 x 4.5 TDK

(1) Lower of IRMS at 40°C rise or ISAT at 30% drop.

spacing
The inductor value also determines the load current at which Power Save Mode is entered:
1
I load ( PSM ) = DI L
2 (9)
Using Equation 8, this current level can be adjusted by changing the inductor value.

Capacitor Selection

Output Capacitor
The recommended value for the output capacitor is 22uF. The architecture of the TPS6213X allows the use of
tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output
voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
Note: In power save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.

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Input Capacitor
For most applications, 10µF will be sufficient and is recommended, though a larger value reduces input current
ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter
from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied
from the same input source, it's required to place a capacitance of 0.1uF from AVIN to AGND, to avoid potential
noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required.

Soft Start Capacitor

A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the
output voltage. A constant current source supports 2.5µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
2.5mA
C SS = t SS × [F ]
1.25V
(10)
where
CSS is the capacitance (F) required at the SS/TR pin and
tSS is the desired soft-start ramp time (s).

spacing

NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.

spacing

Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50mV and 1.2V, the
FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 39.
spacing
VFB » 0.64 × VSS / TR (11)

VSS/TR
[V]
1.2

0.8

0.4

0.2 0.4 0.6 0.8 VFB [V]

Figure 39. Voltage Tracking Relationship

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Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN+0.3V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero,
independent of the tracking voltage. Figure 40 shows how to connect devices to get ratiometric and simultaneous
sequencing by using the tracking function.
spacing

VOUT1
PVIN SW

AVIN VOS

EN PG
TPS62130
SS/TR FB

DEF AGND

FSW PGND

VOUT2
PVIN SW

AVIN VOS

R1 EN PG
TPS62130
SS/TR FB

R2 DEF AGND

FSW PGND

Figure 40. Sequence for Ratiometric and Simultaneous Startup

spacing
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as
VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start
up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft
start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing
circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider
tolerance than specified.

Output Filter And Loop Stability

The devices of the TPS6213X family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 12:
1
f LC =
2p L × C (12)
Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which will be affected. More
information including a detailed LC stability matrix can be found in SLVA463.

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The TPS6213X devices, both fixed and adjustable versions, include an internal 25pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per equation Equation 13 and Equation 14:
spacing
1
f zero =
2p × R1 × 25 pF
(13)
spacing

1 æ 1 1 ö
f pole = × çç + ÷÷
2p × 25 pF è R1 R 2 ø (14)
spacing
Though the TPS6213X devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability vs. transient response can be found in SLVA289 and SLVA466.

Layout Considerations
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6213X demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
See Figure 41 for the recommended layout of the TPS6213X, which is designed for common external ground
connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the
PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system
ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output
capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g.
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB
resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground
plane.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the
EVM Gerber data are available for download here, SLVC394.

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GND
R2 R1

C C 8 7 6 5

9 4
PG
AVIN 10 3

11 2
PVIN

12 1

13 14 15 16

CIN EN
L1

VOUT
to GND
plane

COUT

GND

AGND
to
Figure 41. Layout Example

THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
The TPS6213X is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum
output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by
the package and the surrounding PCB structures. If the thermal resistance of the package is given, the size of
the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To
get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and
thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal
performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
Experimental data, taken from the TPS62130 EVM, shows the maximum ambient temperature (without additional
cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125°C (see
Figure 37).

Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: TPS62130, TPS62130A TPS62131 TPS62132 TPS62133
TPS62130, TPS62130A
TPS62131, TPS62132, TPS62133
SLVSAG7B – NOVEMBER 2011 – REVISED JUNE 2013 www.ti.com

Application Example As Power LED Supply

spacing
The TPS62130 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Since this pin provides 2.5µA, the feedback pin voltage can be adjusted by an external
resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62130.
Figure 42 shows an application circuit, tested with analog dimming:
spacing
(4 .. 17) V 2.2µH
PVIN SW

AVIN VOS

4.7uF EN PG 22uF
ADIM TPS62130
SS/TR FB

187k DEF AGND 0.1R

FSW PGND

Figure 42. Single Power LED Supply

spacing
The resistor at SS/TR sets the FB voltage to a level of about 300mV and is calculated from Equation 15.
spacing
V FB = 0.64 × 2.5mA × R SS / TR
(15)
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used.
More information is available in the Application Note SLVA451.
spacing

Typical Applications
spacing
spacing
(5 .. 17)V 1 / 2.2 µH 5V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 22uF
TPS62133
SS/TR FB
3.3nF
DEF AGND

FSW PGND

Figure 43. 5V/3A Power Supply

spacing
spacing

24 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated

Product Folder Links: TPS62130, TPS62130A TPS62131 TPS62132 TPS62133

 TPS62130, TPS62130A
TPS62131, TPS62132, TPS62133
www.ti.com SLVSAG7B – NOVEMBER 2011 – REVISED JUNE 2013

spacing
spacing
spacing
spacing
spacing
(3.3 .. 17)V 1 / 2.2 µH 3.3V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 22uF
TPS62132
SS/TR FB
3.3nF
DEF AGND

FSW PGND

Figure 44. 3.3V/3A Power Supply

spacing
spacing
spacing
(3 .. 17)V 1 / 2.2 µH 2.5V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 390k 22uF
TPS62130
SS/TR FB
3.3nF
DEF AGND 180k

FSW PGND

Figure 45. 2.5V/3A Power Supply

spacing
spacing
spacing
(3 .. 17)V 1 / 2.2 µH 1.8V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 22uF
TPS62131
SS/TR FB
3.3nF
DEF AGND

FSW PGND

Figure 46. 1.8V/3A Power Supply

spacing
spacing
spacing

Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: TPS62130, TPS62130A TPS62131 TPS62132 TPS62133
TPS62130, TPS62130A
TPS62131, TPS62132, TPS62133
SLVSAG7B – NOVEMBER 2011 – REVISED JUNE 2013 www.ti.com

spacing
spacing
spacing
spacing
spacing
(3 .. 17)V 1 / 2.2 µH 1.5V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 130k 22uF
TPS62130
SS/TR FB
3.3nF
DEF AGND 150k

FSW PGND

Figure 47. 1.5V/3A Power Supply

spacing
spacing
spacing
(3 .. 17)V 1 / 2.2 µH 1.2V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 75k 22uF
TPS62130
SS/TR FB
3.3nF
DEF AGND 150k

FSW PGND

Figure 48. 1.2V/3A Power Supply

spacing
spacing
spacing
(3 .. 17)V 1 / 2.2 µH 1V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 51k 22uF
TPS62130
SS/TR FB
3.3nF
DEF AGND 200k

FSW PGND

Figure 49. 1V/3A Power Supply

spacing
spacing

26 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated

Product Folder Links: TPS62130, TPS62130A TPS62131 TPS62132 TPS62133

 TPS62130, TPS62130A
TPS62131, TPS62132, TPS62133
www.ti.com SLVSAG7B – NOVEMBER 2011 – REVISED JUNE 2013

Application Example As Inverting Power Supply

spacing
The TPS62130 can be used as inverting power supply by rearranging external circuitry as shown in Figure 50.
As the former GND node now represents a voltage level below system ground, the voltage difference between
VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).
spacing
V IN + VOUT £ V IN max (16)
spacing

10uF

(3 .. 13.7)V 2.2µH
PVIN SW

AVIN VOS
10uF
EN PG 1.21M
TPS62130 22uF
SS/TR FB
3.3nF
DEF AGND 383k
-3.3V
FSW PGND

Figure 50. –3.3V Inverting Power Supply

spacing
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469.
spacing

Active Output Discharge

spacing
The TPS62130A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown.
Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 51). The
discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,
keep the maximum current into the PG pin less than 10mA.
spacing
(3 .. 17)V 1 / 2.2 µH Vout / 3A
PVIN SW
TPS62130A
AVIN VOS R3
10uF EN PG R1 22uF

SS/TR FB
3.3nF
DEF AGND R2

FSW PGND

Figure 51. Discharge Vout through PG pin

Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: TPS62130, TPS62130A TPS62131 TPS62132 TPS62133
TPS62130, TPS62130A
TPS62131, TPS62132, TPS62133
SLVSAG7B – NOVEMBER 2011 – REVISED JUNE 2013 www.ti.com

REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.

Changes from Revision A (September 2012) to Revision B Page

• Added device TPS62130A to data sheet Header ................................................................................................................. 1

• Added device TPS62130A to Ordering Information table. .................................................................................................... 2
• Added text to Power Good section regarding TPS63130A. ............................................................................................... 17
• Added pin option to Footnote statement for Pin-Selectable Output Voltage (DEF) section. .............................................. 17
• Added text to Frequency Selection (FSW) section regarding pin control. .......................................................................... 17
• Added text to Tracking Function section for clarification. ................................................................................................... 21
• Added application example regarding TPS62130A device. ............................................................................................... 27

28 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated

Product Folder Links: TPS62130, TPS62130A TPS62131 TPS62132 TPS62133

 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jun-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (3) (4/5)

TPS62130ARGTR PREVIEW QFN RGT 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR PA6I
& no Sb/Br)
TPS62130ARGTT PREVIEW QFN RGT 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR PA6I
& no Sb/Br)
TPS62130GRGTR PREVIEW QFN RGT 16 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2130G
& no Sb/Br)
TPS62130GRGTT PREVIEW QFN RGT 16 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2130G
& no Sb/Br)
TPS62130RGTR ACTIVE QFN RGT 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PTSI
& no Sb/Br)
TPS62130RGTRF0 ACTIVE QFN RGT 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PTSI
& no Sb/Br)
TPS62130RGTT ACTIVE QFN RGT 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PTSI
& no Sb/Br)
TPS62131RGTR ACTIVE QFN RGT 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVX
& no Sb/Br)
TPS62131RGTT ACTIVE QFN RGT 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVX
& no Sb/Br)
TPS62132RGTR ACTIVE QFN RGT 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVY
& no Sb/Br)
TPS62132RGTT ACTIVE QFN RGT 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVY
& no Sb/Br)
TPS62133RGTR ACTIVE QFN RGT 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVZ
& no Sb/Br)
TPS62133RGTT ACTIVE QFN RGT 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QVZ
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jun-2013

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62130GRGTR QFN RGT 16 0 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62130GRGTT QFN RGT 16 0 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62130RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62130RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62131RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62131RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62132RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62132RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62133RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62133RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62130GRGTR QFN RGT 16 0 552.0 367.0 36.0
TPS62130GRGTT QFN RGT 16 0 552.0 185.0 36.0
TPS62130RGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62130RGTT QFN RGT 16 250 552.0 185.0 36.0
TPS62131RGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62131RGTT QFN RGT 16 250 552.0 185.0 36.0
TPS62132RGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62132RGTT QFN RGT 16 250 552.0 185.0 36.0
TPS62133RGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62133RGTT QFN RGT 16 250 552.0 185.0 36.0

Pack Materials-Page 2
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