TPS54395

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3A Dual Channel Synchronous Step-Down Switcher with Integrated FET

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1FEATURES APPLICATIONS
2• D-CAP2™ Control Mode • Point-of-Load Regulation in Low Power
– Fast Transient Response Systems for Wide Range of Applications
– No External Parts Required For Loop – Digital TV Power Supply
Compensation – Networking Home Terminal
– Compatible with Ceramic Output – Digital Set Top Box (STB)
Capacitors – DVD Player/Recorder
• Wide Input Voltage Range : 4.5 V to 18 V – Gaming Consoles and Other
• Output Voltage Range : 0.76V to 7.0V
• Highly Efficient Integrated FETs Optimized for DESCRIPTION
Low Duty Cycle Applications The TPS54395 is a dual, adaptive on-time D-CAP2™
– 90 mΩ (High Side) and 60 mΩ (Low Side) mode synchronous buck converter. The TPS54395
enables system designers to complete the suite of
• High Initial Reference Accuracy various end equipment’s power bus regulators with a
• Supports Constant 3A at Both Channels cost effective, low component count, and low standby
• Low-Side rDS(on) Loss-Less Current Sensing current solution. The main control loops of the
TPS54395 use the D-CAP2™ mode control which
• Adjustabel Soft Start provides a very fast transient response with no
• Non-Sinking Pre-Biased Soft Start external compensation components. The adaptive on-
• 700 kHz Switching Frequency time control supports seamless transition between
PWM mode at higher load conditions and Eco-
• Cycle-by-Cycle Over-Current Limit Control mode™ operation at light loads. Eco-mode™ allows
• OCL/UVLO/TSD Protections the TPS54395 to maintain high efficiency during
• Hiccup Timer for Overload Protection lighter load conditions. The TPS54395 is able to
adapt to both low equivalent series resistance (ESR)
• Adaptive Gate Drivers with Integrated Boost
output capacitors such as POSCAP or SP-CAP, and
PMOS Switch ultra-low ESR, ceramic capacitors. The device
• OCP Constant Due To Thermally Compensated provides convenient and efficient operation with input
rDS(on) with 4000ppm/℃℃ voltages from 4.5V to 18V.
• 16-Pin HTSSOP, 16-Pin VQFN The TPS54395 is available in a 4.4 mm × 5 mm 16-
• Auto-Skip Eco-mode™ for High Efficiency at pin TSSOP (PWP) and 4 mm x 4 mm 16-pin VQFN
Light Load (RSA) package, and is specified for an ambient
temperature range from –40°C to 85°C.
Input Voltage

Vout(50mV/div)
1 VIN1 VIN2 16

C11 2 VBST1 VBST2 15 C12

VO1 L11 C31 C32 L12 VO2
3 SW1 SW2 14
C21 C22
4 PGND1 TPS54395 PGND2 13
PGND HTSSOP16 PGND
5 EN1 EN2 12
Iout(2A/div)
C41 C42
6 SS1 SS2 11

R11 SGND SGND R12

7 VFB1 VFB2 10
R21 C5 R22
8 GND VREG5 9 100 ms/div

PGND
SGND SGND
1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 D-CAP2, Eco-mode, Eco-Mode are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION (1)

TA PACKAGE (2) (3)
ORDERING PART NUMBER PINS OUTPUT SUPPLY
TPS54395PWPR Tape-and-Reel
PWP 16
TPS54395PWP Tube
–40℃ to 85℃
TPS54395RSAR
RSA 16 Tape-and-Reel
TPS54395RSAT

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All packaging options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1) (2)

VALUE UNIT
VIN1, VIN2, EN1, EN2 –0.3 to 20
VBST1, VBST2 –0.3 to 26
VBST1, VBST2 (10ns transient) –0.3 to 28
Input voltage range VBST1–SW1 , VBST2–SW2 –0.3 to 6.5 V
VFB1, VFB2 –0.3 to 6.5
SW1, SW2 –2 to 20
SW1, SW2 (10ns transient) –3 to 22
VREG5, SS1, SS2 –0.3 to 6.5
Output voltage range V
PGND1, PGND2 –0.3 to 0.3
Human Body Model (HBM) 2 kV
Electrostatic discharge
Charged Device Model (CDM) 500 V
TA Operating ambient temperature range –40 to 85 °C
TSTG Storage temperature range –55 to 150 °C
TJ Junction temperature range –40 to 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to IC GND terminal.

THERMAL INFORMATION
TPS54395
THERMAL METRIC (1) UNITS
PWP (16) PINS PWP (16) PINS
θJA Junction-to-ambient thermal resistance 41.4 32.8
θJCtop Junction-to-case (top) thermal resistance 27.8 35.4
θJB Junction-to-board thermal resistance 23.2 9.9
°C/W
ψJT Junction-to-top characterization parameter 0.9 0.4
ψJB Junction-to-board characterization parameter 23.0 10.0
θJCbot Junction-to-case (bottom) thermal resistance 3.5 1.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
VALUES
UNIT
MIN MAX
Supply input voltage range VIN1, VIN2 4.5 18 V
VBST1, VBST2 –0.1 24
VBST1, VBST2 (10ns transient) –0.1 27
VBST1–SW1, VBST2–SW2 –0.1 5.7
Input voltage range VFB1, VFB2 –0.1 5.7 V
EN1, EN2 –0.1 18
SW1, SW2 –1.0 18
SW1, SW2 (10ns transient) –3 21
VREG5, SS1, SS2 –0.1 5.7
Output voltage range PGND1, PGND2 –0.1 0.1 V
VO1, VO2 0.76 7.0
TA Operating free-air temperature –40 85 °C
TJ Operating Junction Temperature –40 150 °C

ELECTRICAL CHARACTERISTICS (1)

over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
TA = 25°C, EN1 = EN2 = 5 V,
IIN VIN supply current 1200 2000 µA
VFB1 = VFB2 = 0.8 V
IVINSDN VIN shutdown current TA = 25°C, EN1 = EN2 = L after H 15 20 µA
FEEDBACK VOLTAGE
VVFBTHLx VFBx threshold voltage TA = 25°C, CH1 = 3.3 V, CH2 = 1.5 V 758 765 773 mV
TCVFBx Temperature coefficient On the basis of 25°C (2) –115 115 ppm/℃
IVFBx VFBx Input Current VFBx = 0.8 V, TA = 25°C –0.4 0.2 0.4 µA
VREG5 OUTPUT
TA = 25°C, 6 V < VIN1 < 18 V,
VVREG5 VREG5 output voltage 5.5 V
IVREG = 5 mA
VIN1 = 6 V, VREG5 = 4.0 V,
IVREG5 Output current 75 mA
TA = 25°C (2)
MOSFETs
(2)
rDS(on)H High side switch resistance TA = 25℃, VBSTx-SWx = 5.5 V 90 mΩ
(2)
rDS(on)L Low side switch resistance TA = 25℃ 60 mΩ
ON-TIME TIMER CONTROL
TON1 SW1 On Time SW1 = 12 V, VO1 = 1.2 V 165 ns
TON2 SW2 On Time SW2 = 12 V, VO2 = 1.2 V 165 ns
(2)
TOFF1 SW1 Min off time TA = 25℃, VFB1 = 0.7 V 220 ns
TOFF2 SW2 Min off time TA = 25℃, VFB2 = 0.7 V (2) 220 ns
SOFT START
ISSC SSx charge current VSSx = 0.5 V, TA = 25℃ –8.4 –8.0 –7.6 µA
TCISSC ISSC temperature coefficient On the basis of 25°C (2) –5 4 nA/°C
ISSD SSx discharge current VSSx = 0.5 V 3 7 10 mA

(1) x means either 1 or 2, that is, VFBx means VFB1 or VFB2.

(2) Specified by design. Not production tested.

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ELECTRICAL CHARACTERISTICS(1) (continued)

over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
UVLO
VREG5 rising 3.83
VUVREG5 VREG5 UVLO threshold V
Hysteresis 0.6
LOGIC THRESHOLDs
VENxH ENx H-level threshold voltage 2.0 V
VENxL ENx L-level threshold voltage 0.4 V
RENx_IN ENx input resistance ENx = 12V 225 450 900 kΩ
CURRENT LIMITs
IOCLx Current limit LOUTx = 2.2 µH (3) 3.5 4.7 6.5 A
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION (UVP, OVP)
VUVP Output UVP trip threshold measured on VFBx 63% 68% 73%
TUVPDEL Output UVP delay time 1.5 ms
TUVPEN Output UVP enable delay UVP enable delay / softstart time x 1.4 x 1.7 x 2.0
THERMAL SHUTDOWN
Shutdown temperature (3) 155
TSD Thermal shutdown threshold °C
Hysteresis (3) 25

(3) Specified by design. Not production tested.

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DEVICE INFORMATION

HTSSOP PACKAGE
(TOP VIEW) RSA PACKAGE (TOP VIEW)

PGND2
SW2

EN2

SS2
1 VIN1 VIN2 16

16 15 14 13

2 VBST1 VBST2 15

VBST2 1 12 VFB2
3 SW1 SW 2 14

VIN2 2 11 VREG5
4 PGND1 TPS54395 PGND 2 13 PowerPAD

HTSSOP16 VIN1 3 10 GND

5 EN1 EN2 12

VBST1 4 9 VFB1
6 SS1 SS2 11

PowerPAD
5 6 7 8
7 VFB1 VFB2 10

SW1

PGND1

EN1

SS1
8 GND VREG5 9

PIN FUNCTIONS (1)

PIN I/O
DESCRIPTION
NAME PWP RSA
VIN1 1 3 I Power inputs and connects to both high side NFET drains.
VIN2 16 2 I Supply Input for 5.5V linear regulator.
VBST1 2 4 I Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor
between VBSTx and SWx pins. An internal diode is connected between VREG5 and
VBST2 15 1 I VBSTx
SW1 3 5 I/O Switch node connections for both the high-side NFETs and low–side NFETs. Input of
SW2 14 16 I/O current comparator.
PGND1 4 6 I/O
Ground returns for low-side MOSFETs. Input of current comparator.
PGND2 13 15 I/O
EN1 5 7 I
Enable. Pull High to enable according converter.
EN2 12 14 I
SS1 6 8 O Soft-Start Programming Pin. Connect Capacitor from SSx pin to GND to program Soft-
SS2 11 13 O Start time.
VFB1 7 9 I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
VFB2 10 12 I
GND 8 10 I/O Signal GND. Connect sensitive SSx and VFBx returns to GND at a single point.
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at
VREG5 9 11 O
least 1.0 µF. VREG5 is active when ENx is high.
Exposed Thermal Back Back I/O Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must
Pad side side be connected to GND.

(1) x means either 1 or 2, that is, VFBx means VFB1 or VFB2.

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FUNCTIONAL BLOCK DIAGRAM

VIN1 VIN1

- 32 UV1 VBST1
UV
0.1uF

SW1
VO1

Ref1 Err PGND1

SS1 Comp PGND1

VFB1
Ref_OCL PGND1
SW1
SW1
OCP1 ZC1
EN1
EN
EN2 EN Logic
Logic
VIN1

VREG5
GND
CH1 Min- off timer 5VREG
1.0 uF

SS1 CH2 Min- off timer Ref1 REF

Ref2
SS1
SS2 SoftStart
SS2 UV1
UV2 UVLO
Protection VIN2
CSS1 UVLO Logic VIN2
CSS2 TSD

-32 VBST2
UV2
UV

0.1uF

VO2

SW2

Ref2 Err PGND2

SS2
Comp PGND2
VFB2

Ref_OCL PGND2
SW2 SW2
OCP2 ZC2

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OVERVIEW
The TPS54395 is a 3A/3A dual synchronous step-down (buck) converter with two integrated N-channel
MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™
control reduces the required output capacitance to meet a specific level of performance. Proprietary internal
circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.

DETAILED DESCRIPTION

PWM Operation
The main control loop of the TPS54395 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal
timer expires. This timer is set by the converter’s input voltage, VINx, and the output voltage, VOx, to maintain a
pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset
and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage.
An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR
induced output ripple from D-CAP™ control.

PWM Frequency and Adaptive On-Time Control

TPS54395 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54395 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set
the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,
therefore, when the duty ratio is VOx/VINx, the frequency is constant.

Auto-Skip Eco-Mode™ Control

The TPS54395 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where
its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with
smaller load current to the nominal output voltage. The transition point to the light load operation IOx(LL) current
can be estimated with Equation 1 with 700-kHz used as fSW.
1 (VINx - VOx ) ´ VOx
IOx(LL) = ´
2 ´ L1x ´ fSW VINx (1)

Soft Start and Pre-Biased Soft Start

The soft start time is adjustable. When the ENx pin becomes high, 8-µA current begins charging the capacitor
which is connected from the SSx pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFBx voltage is 0.765-V and SSx pin source current
is 8-µA.
C4x(nF) ´ VFBx(V) C4x(nF) ´ 0.765 V
TSS (ms) = =
ISS (m A) 8 mA (2)
The TPS54395 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than internal feedback voltage VFBx), the controller slowly activates synchronous rectification
by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx)
starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.

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Current Sensing and Over-Current Protection

The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit.
The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx
pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the
measurement accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VINx,
VOx, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOx. If the sensed voltage on the
low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on
until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle
begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is
monitored in the same manner.
Important considerations for this type of over-current protection: The load current is one half of the peak-to-peak
inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage
tends to fall as the demanded load current may be higher than the current available from the converter. When
the over current condition is removed, the output voltage returns to the regulated value. This protection is non-
latching.

Undervoltage Protection and Hiccup Mode

Hiccup mode of operation protects the power supply from being damaged during an over-current fault condition.
If the OCL comparator circuit detects an over-current event the output voltage falls. When the feedback voltage
falls below 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay
counter begins counting. After counting UVP delay time, the TPS54395 shuts off the power supply for a given
time (7x UVP Enable Delay Time) and then tries to re-start the power supply. If the over-load condition has been
removed, the power supply starts and operates normally; otherwise, the TPS54395 detects another over-current
event and shuts off the power supply again, repeating the previous cycle. Excess heat due to overload lasts for
only a short duration in the hiccup cycle, therefore the junction temperature of the power device is much lower.

UVLO Protection
Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than the UVLO threshold, the TPS54395 shuts down. As soon as the voltage increases above the UVLO
threshold, the converter starts again.

Thermal Shutdown
TPS54395 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the device
shuts down. When the temperature falls below the threshold, the IC starts again.
When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is
lower than 155°C. As long as VIN1 rises, TJ must be kept below 110°C.

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TYPICAL CHARACTERISTICS
One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).
2000 20
VIN1 = VIN2 = 12 V,
1800 EN1 = EN2 = ON 18

Ivccsdn - Shutdown Current - mA

1600 16
ICC - Supply Current - mA

1400 IIN 14 IVINSDN

1200 12

1000 10

800 8

600 6

400 4

200 2

0 0
-50 0 50 100 150 -50 0 50 100 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 1. Input Current vs Junction Temperature Figure 2. Input Shutdown Current vs Junction Temperature

60 3.4

3.38
50 EN2 3.36
VO - Output Voltage - V

3.34 VIN = 18 V
EN Input Current - mA

40 VIN = 12 V

3.32

30 3.3
EN1
3.28
20
3.26
VIN = 6 V
3.24
10
3.22

0 3.2
0 5 10 15 20 0 0.5 1 1.5 2 2.5 3
EN Input Voltage - V IO - Output Current - A
Figure 3. EN Current vs EN Voltage (VEN=12V) Figure 4. VO1=3.3V Output Voltage vs Output Current

1.55 3.4

1.54 3.38

1.53 3.36
VIN = 18 V
VIN = 12 V
VO - Output Voltage - V

1.52
VO - Output Voltage - V

3.34 IO = 10 mA

1.51 3.32

1.5 3.3

1.49 3.28

1.48 VIN = 5 V IO = 1 A
3.26

1.47 3.24

1.46 3.22

1.45 3.2
0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 14 16 18 20
IO - Output Current - A VI - Input Voltage - V
Figure 5. VO2=1.5V Output Voltage vs Output Current Figure 6. VO1=3.3V Output Voltage vs Input Voltage

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TYPICAL CHARACTERISTICS (continued)

One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).
1.55

1.54

1.53 IO = 10 mA Vout(50mV/div)

1.52
VO - Output Voltage - V

1.51

1.5

1.49 Iout(2A/div)
IO = 1 A
1.48

1.47

1.46
100 ms/div
1.45
0 2 4 6 8 10 12 14 16 18 20
VI - Input Voltage - V
Figure 7. VO2=1.5V Output Voltage vs Input Voltage Figure 8. VO1=3.3V, 0A to 3A Load Transient Response

EN1(10V/div)

Vout(50mV/div)

Vout(1V/div)

Iout(2A/div)

SS1(2V/div)

100 ms/div 400 ms/div

Figure 9. VO2=1.5V, 0A to 3A Load Transient Response Figure 10. VO1=3.3V, SoftStart

100

EN2(10V/div)
90

VIN = 6 V VIN = 12 V
80
Vout2(0.5V/div)
VIN = 18 V
Efficiency - %

70

60

SS2(2V/div)
50

400 ms/div 40
0 0.5 1 1.5 2 2.5 3
IO - Output Current - A
Figure 11. VO2=1.5V, SoftStart Figure 12. VO1=3.3V, Efficiency vs Output Current

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TYPICAL CHARACTERISTICS (continued)

One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).
100 100

90 VIN = 5 V
VIN = 6 V
90
80

70 VIN = 18 V
80

Efficiency - %
Efficiency - %

60 VIN = 12 V
VIN = 18 V
VIN = 12 V
50 70

40
60
30

20
50
10

0 40
0.001 0.01 0.1 1 10 0 0.5 1 1.5 2 2.5 3
IO - Output Current - A IO - Output Current - A
Figure 13. VO1=3.3V, Efficiency vs Output Current Figure 14. VO2=1.5V, Efficiency vs Output Current

100 800

90
VIN = 6 V 750
80
fsw - Switching Frequency - kHz

700 IO = 1 A
70
VIN = 18 V
650
Efficiency - %

60
VIN = 12 V
50 600

40
550
30
500
20

10 450

0 400
0.001 0.01 0.1 1 10 0 2 4 6 8 10 12 14 16 18 20
IO - Output Current - A VI - Input Voltage - V
Figure 15. VO2=1.5V, Efficiency vs Output Current Figure 16. VO1=3.3V, SW-frequency vs Input Voltage

800 800

750 700
fsw - Switching Frequency - kHz

fsw - Switching Frequency - kHz

700 600 VIN = 12 V

650 500

IO = 1 A
600 400

550 300

500 200

450 100

400 0
0 2 4 6 8 10 12 14 16 18 20 0.01 0.1 1 10
VI - Input Voltage - V IO - Output Current - A

Figure 17. VO2=1.5V, SW-frequency vs Input Voltage Figure 18. VO1=3.3V, SW-frequency vs Output Current

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TYPICAL CHARACTERISTICS (continued)

One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).
800

700 VO = 3.3 V VO1(10mV/div)

fsw - Switching Frequency - kHz

600

VIN = 12 V
500

400
SW1(5V/div)

300

200

100

0
0.01 0.1 1 10
IO - Output Current - A
Figure 19. VO2=1.5V, SW-frequency vs Output Current Figure 20. VO1=3.3V, VO1 Ripple Voltage (IO1= 3A)

VO = 3.3 V
VIN1(50mV/div)
VO = 1.5 V VO2(10mV/div)

SW2(5V/div) SW1(5V/div)

Figure 21. VO2=1.5V, Ripple Voltage (IO2= 3A) Figure 22. VIN1 Input Voltage Ripple (IO1= 3A)

VO = 1.5 V VIN2(50mV/div)

SW2(5V/div)

Figure 23. VIN2 Input Voltage Ripple (IO2= 3A)

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www.ti.com SLVSBC8A – JUNE 2012 – REVISED MAY 2013

DESIGN GUIDE

Step By Step Design Procedure

To begin the design process, you must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated
switching frequency of 700 kHz is used.

VINx
12V ± 10%

1 VIN1 VIN2 16

C11 2 VBST1 VBST2 15 C12

VO1 10 mF L11 L12 VO2
C31 C32 10 mF
3.3 V 2.2 mH 1.5 mH 1.5 V
0.1 mF 0.1 mF
3 SW1 SW2 14
C21 C22
22 mF 22 mF
x2 4 PGND1 TPS54395 PGND2 13 x2
PGND HTSSOP16 PGND
5 EN1 EN2 12

C41 C42
6 SS1 SS2 11
R11
SGND SGND R12
73.2 kW
7 VFB1 VFB2 10
21.5 kW
R21 C5 1uF R22
22.1 kW
22.1 kW
8 GND VREG5 9

PGND
SGND SGND

Figure 24. Schematic Diagram for the Design Example

Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOx.
To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values
will be more susceptible to noise and voltage errors due to the VFBx input current will be more noticeable.
æ R1x ö
VOx = 0.765 V ´ ç 1+ ÷
è R2x ø (3)

Output Filter Selection

The output filter used with the TPS54395 is an LC circuit. This LC filter has double pole at:
1
FP =
2p L1x ´ C1x (4)

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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54395. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1.

Table 1. Recommended Component Values

Output Voltage (V) R1x (kΩ) R2x (kΩ) Cffx (pF) (1) L1x (µH) C2x (µF)
1 6.81 22.1 1.5 - 2.2 20 - 68
1.05 8.25 22.1 1.5 - 2.2 20 - 68
1.2 12.7 22.1 1.5 - 2.2 20 - 68
1.5 21.5 22.1 1.5 - 2.2 20 - 68
1.8 30.1 22.1 5 - 22 2.2 - 3.3 20 - 68
2.5 49.9 22.1 5 - 22 2.2 - 3.3 20 - 68
3.3 73.2 22.1 5 - 22 2.2 - 3.3 20 - 68
5 124 22.1 5 - 22 4.7 20 - 68
6.5 165 22.1 5 - 22 4.7 20 - 68

(1) Optional

For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (Cffx) in parallel with R1x.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the
peak current of Equation 6 and the RMS current of Equation 7.
VOx VINx(MAX) - VOx
ΔIL1x = ´
VINx(MAX) L1x ´ fSW
(5)
ΔI
IL1xpeak = IOx + L1x
2 (6)
1
IL1x(RMS) = IOx 2 + DIL1x 2
12 (7)
For the above design example, the calculated peak current is 3.46 A and the calculated RMS current is 3.01 A
for VO2. The inductor used is a TDK CLF7045T-2R2N with a rated current of 5.5A based on the inductance
change, and of 4.3A based on the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54395 is intended for use
with ceramic or other low ESR capacitors. The recommended value range is from 20µF to 68µF. Use Equation 8
to determine the required RMS current rating for the output capacitor(s).
VOx ´ (VINx - VOx )
IC2x(RMS) =
12 ´ VINx ´ L1x ´ fSW (8)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.19A and each output capacitor is rated for 4A.

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Input Capacitor Selection

The TPS54395 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1
µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the
SWx node overshoots. The capacitors voltage rating needs to be greater than the maximum input voltage.

Bootstrap Capacitor Selection

A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is
recommended to use ceramic capacitors with a dielectric of X5R or better.

VREG5 Capacitor Selection

A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is
recommended to use a ceramic capacitor with a dielectric of X5R or better.

Thermal Information
This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to
the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of
thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical
schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB.
This design optimizes the heat transfer from the integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature
No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.

Figure 25. Thermal Pad Dimensions

Layout Considerations
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal
pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching currents to flow under the device.
6. Keep the pattern lines for VINx and PGNDx broad.
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7. Exposed pad of device must be soldered to PGND.

8. VREG5 capacitor should be placed near the device, and connected to GND.
9. Output capacitors should be connected with a broad pattern to the PGND.
10. Voltage feedback loops should be as short as possible, and preferably with ground shields.
11. Kelvin connections should be brought from the output to the feedback pin of the device.
12. Providing sufficient vias is preferable for VIN, SW and PGND connections.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.

VIN2
VIN HIGH
FREQUENCY VIN INPUT
BYPASS BYPASS
CAPACITOR CAPACITOR
～0.1µF 10µF x2
Switching noise
VIN1 1 16 VIN2 flows through IC
and CIN . It avoids
the thermal Pad.
OUTPUT
VBST 1 2 15 VBST2 FILTER
CAPACITOR VO2
SW 1 3 14
OUTPUT
SW2
INDUCTOR
Recommend to keep
PGND 1 4 13 PGND 2 distance more than 3-4mm.
(to avoid noise scattering,
TO ENABLE especially GND plane.)
EN1 5 12 EN2
CONTROL
Keep
SS1 6 11 SS2 distance more
than 1 inch
VFB1 7 10 VFB2
POWER GND

8 VREG 5
To feedback
GND 9
Feedback resisters
BIAS resisters
CAP
Symmetrical Layout
for CH1 and CH2

GND
PLANE
2,3 or bottom
layer

Via to GND Plane

- Blue parts can be placed on the bottom side
- Connect the SWx pins through another layer with the inductor
(yellow line)
Figure 26. TPS54395 Layout

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VOUT2 KEEP
VIAS > 3-4 mm
FROM OUTPUT
OUTPUT2 CAPACITORS
FILTER
CAPACITORS
POWER
GROUND
OUTPUT2 KEEP OUTPUT
INDUCTOR VIAS > 25 mm
FROM INPUT VIAS
TO ENABLE
VIN INPUT CONTROL
BYPASS
CAPACITORS

KEEP
VIAS > 3-4 mm
FROM INPUT
CAPACITORS

VIN HIGH

PGND2
FREQUENCY
BYPASS TO POWER

SW2

PG2
EN2
CAPACITOR GOOD PULL
UP 2
BOOST 16 15 14 13
CAPACITOR FEEDBACK
RESISTORS
EXPOSED THERMAL
VBST2 1 PAD AREA 12 VFB2

VIN2 2 11 VREG5
VIN BIAS ANALOG
CAP GROUND
VIN1 3 10 GND
TRACE
VBST1 4 9 VFB1
BOOST
CAPACITOR FEEDBACK
5 6 7 8 RESISTORS
SW1

PGND1

EN 1

PG1

TO POWER
VIN HIGH GOOD PULL
FREQUENCY
BYPASS
UP 1
CAPACITOR

KEEP
VIAS > 3-4 mm
FROM INPUT
CAPACITORS

VIN INPUT
VIA to Internal or
BYPASS
Bottom Layer Ground Plane TO ENABLE
CAPACITORS
VIA to internal or CONTROL
Bottom Layer Etch KEEP OUTPUT
OUTPUT1 VIAS > 25 mm
Etch or Copper Fill INDUCTOR FROM INPUT VIAS
on Top Layer
Internal or Bottom POWER
Layer Ground Plane GROUND
Etch on Bottom Layer, OUTPUT1
Internal Layer or FILTER
CAPACITORS KEEP
Under Component VIAS > 3-4 mm
FROM OUTPUT
NOTE: IT IS POSSIBLE TO PLACE
SOME COMPONENTS SUCH AS
VOUT1 CAPACITORS INTERNAL OR
BOTTOM LAYER
BOOST CAPACITOR AND FEEDBACK GROUND PLANE
RESISTORS ON BOTTOM LAYER

Figure 27. RSA Package Layout

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REVISION HISTORY

Changes from Original (June 2012) to Revision A Page

• Added 16-pin VQFN to the Features and Description .......................................................................................................... 1

• Added the 16-pin package to the Ordering Information table ............................................................................................... 2
• Added the RSA package to the Thermal Information table .................................................................................................. 2
• Added the RSA 16 pin package pinout image, pin names and functions to the DEVICE INFORMATION section ............. 5
• Added Figure 27 ................................................................................................................................................................. 17

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 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS54395PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54395

TPS54395PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54395

TPS54395RSAR ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
54395
TPS54395RSAT ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
54395

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54395PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS54395RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS54395RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54395PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0
TPS54395RSAR QFN RSA 16 3000 346.0 346.0 33.0
TPS54395RSAT QFN RSA 16 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54395PWP PWP HTSSOP 16 90 530 10.2 3600 3.5

Pack Materials-Page 3
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